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Number 2845
A Tektronix Company
ACS Integrated Test System for
Application Note Multi-Site Parallel Test
Series
Solution Concept System Architecture
First, consider the device under test It is easiest to think of a multi-site
(DUT). A DUT often includes a number tester as a system of mini testers. Each
of elements that need to be tested. In a mini tester consists of all the resources
sequential test regime, the testing of each needed to execute a suite of tests on a
element, no matter how simple, adds single site. Figure 3 shows a system of
to the overall test time. If two identical two mini testers. Each mini tester has
elements can be tested in parallel, or several analog source-measure units
even better, two identical and physically (SMUs), a test sequencer/controller, and an
adjacent chips (as shown in Figure optional switch matrix. The independent
2) can be tested in parallel, the total controllers allow each mini tester to
test throughput can be doubled. Not operate autonomously from the other
only is the tester throughput doubled, mini testers and the system controller.
the number of prober moves is cut in In this way, the system controller does
half, resulting in significant test system not gate the execution of the testing,
throughput improvement. but rather initiates test sequences and
It is important to pay critical attention organizes the resulting test data.
to the possible parasitic interactions Keithley's ACS integrated test systems
between chips. For instance, the coupling support the mini tester architecture
Figure 1. This example ACS integrated test system through the wafer substrate may require through the use of our Series 2600B
is configured for parallel, multi-site testing, which that certain low current tests be executed System SourceMeter