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JM3 Power-up Sequence
1. To know JM3 Power-Up Sequence.
2. More easy to find out the root-cause if system
Lock-Up of No-Power.
3. To realize each step before BIOS is working.
4. Summarized preliminary Power-Up sequence
diagram.
5. Power-up sequence after POWER_SW# in the
Nutshell.
Block High Volt.
Section
DCIN+ +DC_IN DC_IN+ SDC_IN+
Adapter is
12V alive Charging PBATT+ PWR_SRC
System on, Bat V-CHG
powered only
SBATT+
Charging
PWR-
charging
PCIRST#
Warm swap only D/D Power GOOD,
CPURST# RBAT_7.2V +RTCSRC D/D
shutdown
+3VALW,5VALW
Section
+5VSUS,
Banias CPU +RTC_PWR3_3V +RTC_PWR5V +1_5VSUS +3VSUS
+2_5VSUS
FSB THERM_STP#
LIVE_ON_BATT
VCCRTC
Montara GM ALWON
RTCRST# ACAV_IN
HUB -LINK
BUS
SUSPWROK
Section 1715PWROK
SUS_ON
ICH4 AUX_EN
+VCC1_2_GMCH,
LPC VTT, SLP_S3#
ICH4
MACALLEN
SIO 12V
(LPC47N254)
(MACALLEN) RUN_ON
+5VRUN, +3VRUN,
+1_5VRUN, +2_5VRUN,
X-BUS Delay VHCORE +1_8VRUN
RUNPWROK
Flash ROM (3~12mS) (IMVP IV)
(8M bit) DELAY_IMVP_PWRGD
Binchuan:
Binchuan:
(1).ADP-IN
(1).ADP-IN
(2).+DC_IN
(2).+DC_IN
ADAPTER-IN(P29)
(3).DC_IN+
(3).DC_IN+
Schematic page 29
Schematic page 29
R380 D24
2 1 D13R_VCC 2
DC_IN+
15K 3 SBATT_CH
1
+12V
1
PWR_SRC
RB715F R379
10K
+RTCSRC Binchuan:
Binchuan:
Q48
D25 FDG316P
6 H H : :High Level.
2
30 RBAT_7.2V
2 1 4 5
2
H High Level.
TRACE:20MIL TRACE:20MIL 1
C208
1N5819HW
LL: :Low Level
Low Level
TRACE:20MIL
1000P
RP97 And so on.
And so on.
3
2
4
1
3 L
4P2R-S-100K
+3VALW
3
Near JDCIN1
2 47K Q46
21 SYS_SUSPEND
DTC144EUA
ADP-IN (1)
1
2
47K
2
Near JDCIN1 D44 D45 C855
+DC_IN (2) DC_IN+ (3)
DA204U 100P_50V
1
UDZ3.6B_NC
C856
Near JDCIN1
3
1
100P_50V
Q37
RV3 +DC_IN FDS6679
JDCIN1 1 2 DC_IN+
POWER_JACK 8
1
L27 BLM11B102S VZ0603M260APT
PS_ID 22,34
H
1
2
3
7
6
5
H
H
1
1
2 DCIN+ 2 3 C35
1
DCIN- 1 4
3 C857 .47U_0805 R27 C38 C41 C357 C42 C363 R542
+
FL1 CM1922 .1U_50V 25V 240K .01U .1U_50V .1U_50V .1U_50V 10U_25V_1210 4.7K
4
1
1
RV2 RV1
CM1922 C858
9
8
7
6
5
4
2
2
2
VZ0603M260APT 0.01U_50V Q49_G
R22 47K
2
2
1 2
VZ0603M260APT
Binchuan:
Binchuan:
(4). DC_IN+ to SDC_IN+
(4). DC_IN+ to SDC_IN+
Schematic page 37
SDC_IN+(P31)
Schematic page 37
SDC_IN+(4)
H
H
DC_IN+
Binchuan:
Binchuan:
(5). SDC_IN+ to PWR_SRC
(5). SDC_IN+ to PWR_SRC
Schematic page 36
PWR_SRC(P36)
Schematic page 36
H
PWR_SRC
H
Binchuan:
Binchuan:
+RTCSRC supply +RTC_PWR5V
+RTCSRC supply +RTC_PWR5V
and +RTC_PWR3_3V
+RTCSRC(P41,43)
and +RTC_PWR3_3V
R380 D24
2 1 D13R_VCC 2
DC_IN+
15K 3 SBATT_CH
1
1
+12V
+RTCSRC PWR_SRC
RB715F R379 +RTCSRC
10K
D25
Q48
FDG316P
PWR_SRC
6
2
2 1 4 5
30 RBAT_7.2V
C208
TRACE:20MIL 1N5819HW TRACE:20MIL
H 2
1 H
TRACE:20MIL
1000P
RP97
3
2 1
4 3
4P2R-S-100K
3
2 47K Q46
21 SYS_SUSPEND
DTC144EUA
47K
1
+RTCSRC
+RTCSRC H
+RTCSRC +RTCSRC
R382 10K H R394 10K H
H 1 2
U35 MAX1615
1 2
U39 MAX1615
1 3 +RTC_PWR3_3V 1 3 +RTC_PWR5V
IN OUT 4 IN OUT 4
C645 5/3# C662 5/3#
C644 5 2 C646 C661 5 2 C654
SHDN GND SHDN GND
.1U_50V SOT23-5 +RTC_PWR3_3V
10U_10V .1U_50V SOT23-5 10U_10V
+RTC_PWR5V
1U_25V 1U_25V
Binchuan:
Binchuan:
ACAV_IN will be
ACAV_IN will be
generated after
ACAV_IN(P37)
generated after
+RTC_PWR5V.
+RTC_PWR5V.
+RTC_PWR5V
DC_IN+ (3) DC_IN+ +RTC_PWR5V
H
H
1
1
R459
R468 1K
75K/F
R465 10K 1
1 2 2 Q61
2
2
3 3906
R464 1M
1 2
ACAV_IN 22,36,41
1
2
U52
H
1
R471
12.7K/F
1 LM431SACMF ACAV_IN
R458
100K
2
3
2
Binchuan:
Binchuan:
ACAV_IN generate to notice SIO
ACAV_IN generate to notice SIO
about Adaptor(Present).
about Adaptor(Present).
Binchuan:
Binchuan:
MAX1999 use LDO to
+3VALW&+5VALW(P41)
MAX1999 use LDO to
output +5VALW&+3VALW
output +5VALW&+3VALW
while U50 pin 17(VCC)
while U50 pin 17(VCC)
has Power Source and
has Power Source and
Pin 66is at Logic H.
Pin is at Logic H. H
PWR_SRC
H VCC
SHDN
H
THERM_STP#
H
Binchuan:
Binchuan:
(6).As soon as +RTC_PWR3_3V on, then
(6).As soon as +RTC_PWR3_3V on, then
RTCRST# will be from Low ?High.
RTCRST# will be from Low ?High.
(Reset CMOS)
(Reset CMOS)
RTCRST#(P9)
VCCRTC
+RTC_PWR3_3V
H
H
Binchuan:
H
Binchuan:
RTCRST#
CLK_32KX1/X2 must
CLK_32KX1/X2 must
be generated, it's for
be generated, it's for
RTCCLK units(ICH4)
RTCCLK units(ICH4)
using to generate
using to generate
SLP_S3# &SLP_S5#.
SLP_S3# &SLP_S5#. ICH4
OSCILLATION
Binchuan:
Binchuan:
(A).POWER_SW# generate
(A).POWER_SW# generate
the POWER_SIO#, and IfIf
the POWER_SIO#, and
POWER_SW#(P41,P2
MACALLEN(SIO) is alive
MACALLEN(SIO) is alive
then it'll assert SUN_ON to
then it'll assert SUN_ON to
MAX1999 (3/5VSUS)
1) +RTC_PWR5V
+RTC_PWR5V +RTC_PWR5V
1
C658
MAX1999 (3/5VSUS)
H-L-H R391
10K
5
U36A
7WZ14
1
.1U
2
U41
5 7SH32
2
POWER_SW# 1 6 2
POWER_SW# 27,28 POWER_SW#
4
C650 1
.1U
D26
2 1
21 PWRSW_SIO#
+RTC_PWR5V
RB751V
C657
1 2
POWER_SIO# H-L-H R397
1
100K
2
5
.1U
U40
NC7ST32
2
22 LIVE_ON_BATT 4
1
22,36,37 ACAV_IN
MACALLEN(SIO)
H-L-H
H
SUS_ON
Binchuan:
Binchuan:
THERM_STP# is OD and will be
THERM_STP# is OD and will be
generated its function after +3VSUS.
generated its function after +3VSUS.
MAX1999(P41)
SHDN#
MAX1999
ON3
ON5
SUS_ON H
SUS_ON
H
H
Binchuan:
Binchuan:
With respect of MAX1999, the SHDN# pin need
Keep `H'
H With respect of MAX1999, the SHDN# pin need
to at Logic `H'and Enable ON3 & ON5 from
to at Logic `H'and Enable ON3 & ON5 from
SUS_ON signal to generate 3/5/12V.
SUS_ON signal to generate 3/5/12V.
Binchuan:
Binchuan:
SUS_ON turn on +3/5VSUS power.
SUS_ON turn on +3/5VSUS power.
While MAX1999 stable then itit
While MAX1999 stable then
3/5/12V(P41)
generate SUSPWROK_5V.
generate SUSPWROK_5V.
15V
+5VSUS
H H
H
+3VSUS
MAX1999
H
H SUSPWROK_5V
+12V
Binchuan:
Binchuan:
+3VSUS? THERM_STP# at Logic `H'.
+3VSUS? THERM_STP# at Logic `H'.
THERM_STP#(P28)
Guardian Thermal IC control currently
Guardian Thermal IC control currently
System Thermal 2status.
System Thermal status.
THERMDA ATF_INT# 21
2 THERMDC +5VSUS RT1 should be placed near DDR.
Thermal IC U4
R317
2.21K/F
R80 14,22,25 DAT_SMB DAT_SMB 1 +5VSUS
CLK_SMB 2 THDAT_SMB 9
+3VSUS 14,22,25 CLK_SMB THCLK_SMB ATF_INT#
1
RT1
49.9/F C104 R267 13 TH11-3H103FT
THERMDA 1K SMBADDRSEL
.1U C114 18 R309
REM_DIODE2_P
THERMDC 2200P
17
REM_DIODE2_N VCP
23 VCP
Q42
t 10Kohm C
@25 degree
10K
4
32
R92 11 +3VSUS C105
9,35 SUSPWROK VSUS_PWRGD
+RTC_PWR3_3V 1K 2
10 2200P 5V_CAL_SIO# 21
+RTC_PWR3V 16
C115 R265 5 RESSERVED RHU002N06
1
35 +3V_PWROK 1K +3V_PWROK#
.1U +3VSUS 21
27,41 POWER_SW# POWER_SW# Place under CPU
Notes: THERMTRIP1# 6 19
THERMTRIP1# REM_DIODE1_N 20
R86 7 REM_DIODE1_P Q17 1
Vset=(Tp-75)/16 C461 100K THERMTRIP2# +3VALW C110 2
Where Tp=75 to R268 R87 8
THERMTRIP3#
15
THERMTRIP_SIO 24
3
106 degree C .1U 100K 2200P
30.1K/F 22 THERM_STP# 3904
14 VSET R330
Set trip point=90 degree c 3 HW_LOCK# 12
VSS INTRUDER# Put 2200P close to Guardian.
Vset = (90-75)/16= 100K
0.9375 V R269
C852 R266
Guardian temp-tolerance= +/-3 degree C 12.1K/F 1K THERMTRIP_SIO22
2200P
THERM_STP#41
EMC6N300
+3VSUS
INTRUDER#9
R534
8.2K
THERMTRIP1#
VTT
R535 2.2K Q85 3
2
1
C853
Binchuan:
Binchuan:
3904 .1U
near Guardian IC. THERM_STP# to be
While THERM_STP# to be
C853 needs to be placed
2,9 THERMTRIP#
While
generated will cause MAX1999
generated will cause MAX1999
force POWER SHUT DOWN.
force POWER SHUT DOWN.
Binchuan:
Binchuan:
When +5VSUS supply SC1486 then it'll
When +5VSUS supply SC1486 then it'll 1.25V_PWRGD(P40)
generate +2_5VSUS,SMDDR_VTERM
generate +2_5VSUS,SMDDR_VTERM
and 1.25V_PWRGD & 2.5V_PWRGD. .
and 1.25V_PWRGD & 2.5V_PWRGD
+5VSUS
H 2.5V_PWRGD
+2_5VSUS
H
SMDDR_VTERM
H (1.25V)
H
SC1486
H
1.25V_PWRGD
Binchuan:
Binchuan:
(C). When +5VSUS supply
(C). When +5VSUS supply
MAX1715 then it'll generate
MAX1715 then it'll generate
+1.5VSUS,+2.5VSUS and
+1.5VSUS,+2.5VSUS and
1715PWROK(P42)
1715SUSOK.
1715SUSOK.
+5VSUS
VTT(1.05V) H
+VCC1_2_GMCH(1.2V)
H
H
MAX1715
H 1715PWROK
Binchuan:
Binchuan:
SUSPWROK_5V as +3/5VSUS
SUSPWROK_5V as +3/5VSUS
is ok. Then ititwill connect with
is ok. Then will connect with
AND-Gate with SUS_ON then
AND-Gate with SUS_ON then
AND with 2.5V_PWRGD to
SUSPWROK(P35)
AND with 2.5V_PWRGD to
produce SUSPWROK.
produce SUSPWROK.
+3VRUN +3VSUS +3V_PWROK 28
C595 +3VSUS
1
R346
Keep Away from high speed buses
100K .1U +3VSUS
5 U28A 5 U28B
C601
2
1 6 3 4
.1U
C602
7WZ14 7WZ14 14 U30A
.1U 1
3
+3VSUS 2
+3VSUS 39 1715_1.5V_PWRGOOD 74AHC08
U30B
5 4
5 2 6
RUNPWROK 22,38,41,42
40 1.25V_PWRGD 2 4 5
4 1
21,23,39,44 RUN_ON 1 74AHC08
U27
U32 7SH08
7SH08
SUSPWROK 9,28
+3VSUS
H
U30C
SUSPWROK_5V
C613
40 2.5V_PWRGD
9
8 SUSPWROK
.047U H 10
41 SUSPWROK_5V
H 5
2
74AHC08
21,40,41 SUS_ON 1
4
H
U31
7SH08
Binchuan:
Binchuan:
RTCRST# inactive to SUSCLK
RTCRST# inactive to SUSCLK
running,SLP_S3#,SLP_S5#
running,SLP_S3#,SLP_S5#
SLP_S3#,SLP_S5#(P09)
inactive.
inactive.
RSMRST#
SUSPWROK H
ICH4
SLP_S3#
Binchuan:
L?H SLP_S5# Binchuan:
RSMRST# used for
RSMRST# used for
resetting the resume
resetting the resume
power plane logic.
power plane logic.
ICH4 Binchuan:
Binchuan:
Inactive SLP_S3# signal
Inactive SLP_S3# signal
detected by MACALLEN(SIO).
detected by MACALLEN(SIO).
Logical Level L? H.
Logical Level L? H.
Binchuan:
Binchuan:
(D). SLP_S3# generate
(D). SLP_S3# generate
RUN_ON to turn on RUN
RUN_ON to turn on RUN
Power plane.
RUN_ON(P21)
Power plane.
P.S.: MACALLEN(SIO)
P.S.: MACALLEN(SIO)
ignore the SLP_S5# signal
ignore the SLP_S5# signal
SLP_S3# H
MACALLEN(SIO)
H RUN_ON(D)
MAX1715 1.8VRUN(P39)
+5VSUS
H
+1.8VRUN
+1.5VSUS H
RUN_ON
H
H
MAX1715
H 1715_1.5V_PWRGOOD
RUN POWER(P44)
+5VALW 12OUT
+5VSUS
Q2
SI3456DV +5VRUN +5VRUN
6
5 4
H
1
1
2
R472 R481 1
C31
RUN_ON_5V# 100K 100K
H 4.7U_10V
3
2
2
H
3
1
RUN_ON_5V# 2 R1
C826 470K_NC
4700PF
1
3
2
21,23,35,39 RUN_ON
2
Q69
Q74
RHU002N06 +3V_SRC
Q56
+3VRUN +3VRUN
1
RHU002N06 6
RUN_ON H
5 4
2
1
HC763
4.7U_10V
3
SI3456DV
Binchuan:
Binchuan: Q67
RUN_ON turn on all RUN POWER.
+1_5VSUS
SI3456DV +1_5VRUN
+1_5VRUN
RUN_ON turn on all RUN POWER. 6
5 4
RUN_ON enable as below:
RUN_ON enable as below:
2
1 HC819
1. +3VRUN, +5VRUN, +1_5VRUN,
3
4.7U_10V
1. +3VRUN, +5VRUN, +1_5VRUN,
+2_5VRUN(P44)
+2_5VRUN(P44)
2. +1_8VRUN (P39)
2. +1_8VRUN (P39)
+2_5VSUS Q73 +2_5VRUN
3 1
NDS351AN
H +2_5VRUN
C822
2
1U_10V
ID = 300mA(Max).
Rds= 1.0 Max @Vgs=10V.
Rds= 0.7 (Typ.)@Vgs=10V.
Binchuan:
Binchuan:
RUNPWROK turns on CPU
RUNPWROK turns on CPU
VCORE POWER.
VCORE POWER.
RUNPWROK(P35)
+3V_PWROK 28
+3VRUN +3VSUS
C595 +3VSUS
1
R346
Keep Away from high speed buses
100K .1U +3VSUS
5 U28A 5 U28B
H C601
2
1 6 3 4
.1U
C602
7WZ14 7WZ14 14 U30A
.1U