Text preview for : Compal_LA-7391P.pdf part of Compal Compal LA-7391P Compal Compal_LA-7391P.pdf



Back to : Compal_LA-7391P.pdf | Home

A B C D E




1 1




Compal Confidential
2 2




PBL22 MB Schematic Document
LA-7391P
3 3




Rev: 0.2
2011.04.07

4 4




Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/12/01 Deciphered Date 2011/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Sheet
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-7391P
Date: Thursday, April 07, 2011 Sheet 1 of 64
A B C D E
A B C D E




Compal Confidential CPU XDP
Project Code : PBL22 Chief River Conn. P.5
File Name : LA-7391P
PCH XDP
Fan Control
P.48 Conn. P.15
1 1



PEG x16 (DIS) Intel
GEN 1/2/3
N12P-GE Ivy Bridge Memory Bus 204pin DDRIII SO-DIMM x2
64*16 1GB Dual Channel BANK 0, 1, 2, 3 P.11, 12
SW eDP (UMA) Processor 1.5V DDR3 1866MHz
eDP Conn.
P.24-35 P.36
rPGA 989 Socket
Port 0
P.4~9
SATA HDD-1 Conn.
P.45
SATA 3.0
FDI x8 DMI x4
(UMA) 100MHz
LVDS Conn. HDMI Conn. CRT Conn. OPTIMUS/UMA 100MHz 5GB/s Port 2 SATA ODD Conn. Reserved USB2.0
P.38 P.44 P.37
2.7GT/s SATA 2.0 P.36
/ USB 3.0
Port 4 Port3 USB board
2 CRT Port 1
2

SATA
ESATA+ USB 2.0
DP Conn. HDMI IO board

IO board LVDS Port 8 USB 2.0 Conn.
on right side Audio board
DisplayPort Intel Port 9 USB 2.0 Conn./light peak
DisplayPort on right side light peak board
Cougar Point
Port 5-8 PCI-E x4 Port 0 USB 2.0 /USB 3.0 Conn. Port 0

PCI-E x1
Panther Point IO board

PCH USB2.0 Port 8
Light Peak Port 2 Port 3 Port 1 Camera P.38
P.52-53
Mini Card-1 LAN(GbE) Port 4 Mini Card-1 (WLAN& BTcombo)
Express Card WLAN (Half) P.51 RTL8111E-VB BGA 989 Balls ( Half ) P.51

IO board +Blue Tooth combo Port 2
3
CIO 3
P.54
Port 4 RJ45 USB 3.0 Port 2 USB 2.0/USB 3.0 Conn.
On Left Side P.46
P.42
7 in 1 card USB2.0 port 10
Reader P15~22
IO board HD Audio
Mini Card-1 USB2.0 port 5 SPI Int. Speaker Audio board
WWAN (full)
SATA Port1 LPC Bus
Reserved for Audio Jack x2
( HeadPhone, MIC) Audio board
m-SATA P.51 Audio Codec
Sub-board Realtek ALC269
ENE KB930/Co-lay KB9012 Audio board
Digital MIC Audio board
Function Board: LS-6002P P.49
IO board (LS-7391P)
P.50
SYS BIOS ROM
IO Board to Board :LS-7394P PWR Button Board:LS-6003P P.15
4
P.47 P.48 ENE 3810 Touch Pad Int.KBD EC ROM 4

P.47 P.50 P.50 P.50

Audio Board : LS-7392P USB Board : LS7395P
USB (Port,11) P.46 P.46
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/12/01 Deciphered Date 2011/12/31 Title
Light Peak Board : LS-7393P FPC Cable : LF7391P Chief River-Block Diagram
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P.46 P.46 Size Document Number Rev
USB (Port,10) AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-7391P
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, April 07, 2011 Sheet 2 of 64
A B C D E
A




Board ID Table for AD channel
Vcc 3.3V +/- 5% BOARD ID Table USB PORT# DESTINATION
Ra 100K +/- 5%
Board ID Rb V AD_BID min V AD_BID typ V AD_BID max Board ID PCB Revision 0 USB2/3 (Ext Right Side Up)
0 0 0 V 0 V 0 V 0 0.1
1 8.2K +/- 5% 0.168V 0.250 V 0.362 V 1 1 ESATA ( Ext Right Side Up)
2 18K +/- 5% 0.436 V 0.503 V 0.538 V 2
3 33K +/- 5% 0.712 V 0.819 V 0.875 V 3 2 USB2/3 (Ext Left Side Down)
4 56K +/- 5% 1.036 V 1.185 V 1.264 V 4
5 100K +/- 5% 1.453 V 1.650 V 1.759 V 5 3 USB2/3 (Ext FPC board)
6 200K +/- 5% 1.935 V 2.200 V 2.341 V 6
7 NC 2.500 V 3.300 V 3.300 V 7 4 JMINI1 (WLAN) Bluetooth

5 JMINI2 (WWAN)
SMBUS Control Table
DGPU 6 None
EXPRESS Internal JXDP1
JXDP2
SOURCE MIINI1 BATT MINI2 SODIMM Thermal
CARD
sensor PCH 7 None
CLKOUT DESTINATION
EC_SMB_CK1
EC_SMB_DA1
KB930 X V X X X X X 8 CAMERA
PCI0 PCH_LOOPBACK
EC_SMB_CK2
EC_SMB_DA2
KB930 X X X X X V X 9 JUSB3 ( Ext Right Side Down)
PCI1 EC
PCH_SMBCLK
PCH_SMBDATA PCH
V X V V V X V 10 EXPRESS CARD
PCI2 Debug Port
PCH_SMLCLK 11 JUSB4 ( Ext Right Side Down)
PCH_SMLDATA PCH
X X X X X V X PCI3 LPC Debug Port
12 None
PCI4 None
13 None
1
UMA: UMA@/XDP@/UO@ 1




OPTIMUS: XDP@/D@/UO@
DISCRETE:XDP@D@/DIS@

DIFFERENTIAL DESTINATION FLEX CLOCKS DESTINATION SATA DESTINATION PCI EXPRESS DESTINATION

CLKOUT_PCIE0 10/100/1G LAN CLKOUTFLEX0 None SATA0 HDD Lane 1 10/100/1G LAN

CLKOUT_PCIE1 MINI CARD-1 WLAN CLKOUTFLEX1 CLK_14M SATA1 m-SATA Lane 2 MINI CARD-1 WLAN

CLKOUT_PCIE2 EXPRESS CARD CLKOUTFLEX2 27M_CLK SATA2 ODD Lane 3 EXPRESS CARD

CLK CLKOUT_PCIE3 CARD READER CLKOUTFLEX3 27M_SSC SATA3 None Lane 4 CARD READER

CLKOUT_PCIE4 Light Peak SATA4 ESATA Lane 5 Light Peak

CLKOUT_PCIE5 None SATA5 None Lane 6 Light Peak

CLKOUT_PCIE6 None Lane 7 Light Peak

CLKOUT_PCIE7 None Lane 8 Light Peak

CLKOUT_PEG_B None



Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/12/01 Deciphered Date 2011/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-7391P
Date: Thursday, April 07, 2011 Sheet 3 of 64
A
5 4 3 2 1




+V1.05S_VCCP




1
JCPU1I
RC1 PEG_ICOMPI and RCOMPO signals should be shorted and routed
24.9_0402_1% with - max length = 500 mils - typical impedance = 43 mohms
PEG_ICOMPO signals should be routed with - max length = 500 mils
T35 F22




2
JCPU1A
- typical impedance = 14.5 mohms VSS161 VSS234
T34 F19
D PEG_COMP VSS162 VSS235 D
J22 T33 E30
PEG_ICOMPI VSS163 VSS236
J21 T32 E27
PEG_ICOMPO VSS164 VSS237
17 DMI_CRX_PTX_N0 B27 DMI_RX#[0] PEG_RCOMPO H22 T31 VSS165 VSS238 E24
17 DMI_CRX_PTX_N1 B25 DMI_RX#[1] T30 VSS166 VSS239 E21
17 DMI_CRX_PTX_N2 A25 PCIE_GTX_C_CRX_N[0..15] 24 T29 E18
DMI_RX#[2] PCIE_GTX_C_CRX_N15 VSS167 VSS240
17 DMI_CRX_PTX_N3 B24 DMI_RX#[3] PEG_RX#[0] K33 T28 VSS168 VSS241 E15
M35 PCIE_GTX_C_CRX_N14 T27 E13
PEG_RX#[1] PCIE_GTX_C_CRX_N13 VSS169 VSS242
17 DMI_CRX_PTX_P0 B28 L34 T26 E10
DMI_RX[0] PEG_RX#[2] PCIE_GTX_C_CRX_N12 VSS170 VSS243
17 DMI_CRX_PTX_P1 B26 J35 P9 E9
DMI_RX[1] PEG_RX#[3] PCIE_GTX_C_CRX_N11 VSS171 VSS244
17 DMI_CRX_PTX_P2 A24 J32 P8 E8




DMI
DMI_RX[2] PEG_RX#[4] PCIE_GTX_C_CRX_N10 VSS172 VSS245
17 DMI_CRX_PTX_P3 B23 H34 P6 E7
DMI_RX[3] PEG_RX#[5] PCIE_GTX_C_CRX_N9 VSS173 VSS246
PEG_RX#[6] H31 P5 VSS174 VSS247 E6
G21 G33 PCIE_GTX_C_CRX_N8 P3 E5
17 DMI_CTX_PRX_N0 DMI_TX#[0] PEG_RX#[7] VSS175 VSS248
E22 G30 PCIE_GTX_C_CRX_N7 P2 E4
17 DMI_CTX_PRX_N1 DMI_TX#[1] PEG_RX#[8] PCIE_GTX_C_CRX_N6 VSS176 VSS249
17 DMI_CTX_PRX_N2 F21 DMI_TX#[2] PEG_RX#[9] F35 N35 VSS177 VSS250 E3
D21 E34 PCIE_GTX_C_CRX_N5 N34 E2
17 DMI_CTX_PRX_N3 DMI_TX#[3] PEG_RX#[10] PCIE_GTX_C_CRX_N4 VSS178 VSS251
PEG_RX#[11] E32 N33 VSS179 VSS252 E1
G22 D33 PCIE_GTX_C_CRX_N3 N32 D35
17 DMI_CTX_PRX_P0 DMI_TX[0] PEG_RX#[12] VSS180 VSS253
D22 D31 PCIE_GTX_C_CRX_N2 N31 D32
17 DMI_CTX_PRX_P1 DMI_TX[1] PEG_RX#[13] PCIE_GTX_C_CRX_N1 VSS181 VSS254
17 DMI_CTX_PRX_P2 F20 DMI_TX[2] PEG_RX#[14] B33 N30 VSS182 VSS255 D29




PCI EXPRESS* - GRAPHICS
C21 C32 PCIE_GTX_C_CRX_N0 N29 D26
17 DMI_CTX_PRX_P3 DMI_TX[3] PEG_RX#[15] VSS183 VSS256
PCIE_GTX_C_CRX_P[0..15] 24 N28 VSS184 VSS257 D20
J33 PCIE_GTX_C_CRX_P15 N27 D17
PEG_RX[0] PCIE_GTX_C_CRX_P14 VSS185 VSS258
PEG_RX[1] L35 N26 VSS186 VSS259 C34
K34 PCIE_GTX_C_CRX_P13 M34 C31
FDI_CTX_PRX_N0 PEG_RX[2] PCIE_GTX_C_CRX_P12 PAY ATTENTION ON PCIE SWAP WHEN REVIEW VSS187 VSS260
17 FDI_CTX_PRX_N0 A21 FDI0_TX#[0] PEG_RX[3] H35 L33 VSS188 VSS261 C28
FDI_CTX_PRX_N1 H19 H32 PCIE_GTX_C_CRX_P11 L30 C27
17 FDI_CTX_PRX_N1 FDI_CTX_PRX_N2 FDI0_TX#[1] PEG_RX[4] PCIE_GTX_C_CRX_P10 VSS189 VSS262
17 FDI_CTX_PRX_N2 E19 G34 L27 C25
FDI_CTX_PRX_N3 FDI0_TX#[2] PEG_RX[5] PCIE_GTX_C_CRX_P9 VSS190 VSS263
17 FDI_CTX_PRX_N3 F18 G31 L9 C23
FDI0_TX#[3] PEG_RX[6] VSS191 VSS264
17 FDI_CTX_PRX_N4
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
B21
C20
FDI1_TX#[0] Intel(R) FDI PEG_RX[7] F33
F30
PCIE_GTX_C_CRX_P8
PCIE_GTX_C_CRX_P7
L8
L6
VSS192 VSS265 C10
C1
17 FDI_CTX_PRX_N5 FDI_CTX_PRX_N6 FDI1_TX#[1] PEG_RX[8] PCIE_GTX_C_CRX_P6 VSS193 VSS266
17 FDI_CTX_PRX_N6 D18 FDI1_TX#[2] PEG_RX[9] E35 L5 VSS194 VSS267 B22
C FDI_CTX_PRX_N7 PCIE_GTX_C_CRX_P5 C
E17 E33 L4 B19
17 FDI_CTX_PRX_N7 FDI1_TX#[3] PEG_RX[10]
PEG_RX[11]
PEG_RX[12]
F32
D34
PCIE_GTX_C_CRX_P4
PCIE_GTX_C_CRX_P3
L3
L2
VSS195
VSS196
VSS197
VSS VSS268
VSS269
VSS270
B17
B15
FDI_CTX_PRX_P0 A22 E31 PCIE_GTX_C_CRX_P2 L1 B13
17 FDI_CTX_PRX_P0 FDI_CTX_PRX_P1 FDI0_TX[0] PEG_RX[13] PCIE_GTX_C_CRX_P1 VSS198 VSS271
17 FDI_CTX_PRX_P1 G19 FDI0_TX[1] PEG_RX[14] C33 K35 VSS199 VSS272 B11
FDI_CTX_PRX_P2 E20 B32 PCIE_GTX_C_CRX_P0 K32 B9
17 FDI_CTX_PRX_P2 FDI0_TX[2] PEG_RX[15] VSS200 VSS273
FDI_CTX_PRX_P3 G18