Text preview for : Acer Aspire 4535_Compal_LA-4921P_KBLG0_NBLG0_Rev1.0.pdf part of acer Acer Aspire 4535 Compal LA-4921P KBLG0 NBLG0 Rev1.0 acer Acer Aspire 4535_Compal_LA-4921P_KBLG0_NBLG0_Rev1.0.pdf
Back to : Acer Aspire 4535_Compal_L | Home
A B C D E
1 1
Compal Confidential
2 2
KBLG0/NBLG0 Schematics Document
AMD Puma (JV40-PU) : Griffin Processor with RS780MN/SB700/M92-M2 XT
Tigris (JV40-TR) : Caspian Processor with RS880M/SB710/M92-M2 XT
3
2009-03-11 3
REV:1.0
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008/10/06 Deciphered Date 2009/10/06 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC A4921P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B
401679 C
Date: Thursday, March 26, 2009 Sheet 1 of 57
A B C D E
A B C D E
Tigris
Puma
Compal Confidential AMD S1G3 Processor
uPGA-638 Package
VRAM 512MB Caspian AMD S1G2 Processor
Model Name : KBLG0 Memory BUS(DDRII) 200pin DDRII-SO-DIMM X2
64M16 x 4 Fan Control uPGA-638 Package
page 19, 20 Dual Channel BANK 0, 1, 2, 3 page 8,9
PowerXpress (MUX) page 44
Griffin page 4,5,6,7 1.8V DDRII 667/800
1 LCD (LED BL) MUX DDR2 500MHz 1
Hyper Transport Link 5 in 1 socket
page 24 (1:2) ATI M92-M2 XT 16 x 16 page 33
ATI RS880M
uFCBGA-962 PCI-Express 16x uFCBGA-528
CRT MUX Page 14,15,16,17,18,21,22
Gen2 Thermal Sensor Clock Generator
page 26 (1:2) ATI RS780MN Card Reader
ADM1032 SLG8SP626VTR
page 6 page 23 RTS5159
HDMI Conn. uFCBGA-528 page 33
page 25
PCI-Express 1x option1
page 10,11,12,13 page 36,37 page 27 page 37 page 36 page 36
option2
USB CMOS Bluetooth Finger Mini
MINI Card x1 LAN(GbE) Card Reader A link Express2 conn printer card
ATI SB710 Camera Conn
WLAN Atheros AR8131 JMB385 uFCBGA-528 X2 AES1610 (WL)X1
page 36 page 34 page 33 USB port 0,6 USB port 3 USB port 12 USB port 13 USB port 8 USB port 4
port 2 port 3 port 4
2
ATI SB700 3.3V 48MHz USB
2
RJ45 5 in 1 socket 3.3V 24.576MHz/48Mhz HD Audio
page 33
page 35 uFCBGA-528
USB port 1
page 27,28,29,30,31 S-ATA
MDC 1.5 HDA Codec Digital MIC
Conn 41
page
ALC888 42
page page 42
LED LPC BUS SATA HDD CDROM ESATA
page 40
Conn. page 32 Conn. 32
page
Conn. 37
page
port 0 port 1 port 2 Audio AMP
page 43
RTC CKT.
page 26
ENE KB926
3 page 38 3
Phone Jack x3
page 43
LID SW / MEDIA/B
page 39 Touch Pad Int.KBD
page 39 page 39
Power On/Off CKT. EC I/O Buffer BIOS
page 41
page 38 page 39
DC/DC Interface CKT.
page 45
Power Circuit
4
page 46,47,48,49,50,51 4
52,53,54
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008/10/06 Deciphered Date 2009/10/06 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC A4921P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B
401679 C
Date: Thursday, March 26, 2009 Sheet 2 of 57
A B C D E
A B C D E
SIGNAL
STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
Voltage Rails Full ON HIGH HIGH HIGH HIGH ON ON ON ON
Power Plane Description S1 S3 S5 S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW
VIN Adapter power supply (19V) N/A N/A N/A S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF
B+ AC or battery power rail for power circuit. N/A N/A N/A
1
S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF 1
+CPU_CORE_0 Core voltage for CPU (0.7-1.2V) ON OFF OFF
+CPU_CORE_1 Core voltage for CPU (0.7-1.2V) ON OFF OFF S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF
+CPU_CORE_NB ON
Voltage for On-die Northbridge of CPU(0.8-1.1V) OFF OFF
+0.9V 0.9V switched power rail for DDR terminator ON ON OFF
+1.1VS 1.1V switched power rail for NB VDDC & VGA ON OFF OFF Board ID / SKU ID Table for AD channel
+1.2V_HT 1.2V switched power rail ON OFF OFF Vcc 3.3V +/- 5%
+VGA_CORE 0.95-1.2V switched power rail ON OFF OFF Ra/Rc/Re 100K +/- 5%
+1.5VS 1.5V power rail for PCIE Card ON OFF OFF Board ID Rb / Rd / Rf V AD_BID min V AD_BID typ V AD_BID max
+1.8V 1.8V power rail for CPU VDDIO and DDR ON ON OFF 0 0 0 V 0 V 0 V
+1.8VS 1.8V switched power rail ON OFF OFF 1 8.2K +/- 5% 0.216 V 0.250 V 0.289 V
+2.5VS 2.5V for CPU_VDDA ON OFF OFF 2 18K +/- 5% 0.436 V 0.503 V 0.538 V
+3VALW 3.3V always on power rail ON ON ON* 3 33K +/- 5% 0.712 V 0.819 V 0.875 V
+3V_LAN 3.3V power rail for LAN ON ON ON 4 56K +/- 5% 1.036 V 1.185 V 1.264 V
+3VS 3.3V switched power rail ON OFF OFF 5 100K +/- 5% 1.453 V 1.650 V 1.759 V
+5VALW 5V always on power rail ON ON ON* 6 200K +/- 5% 1.935 V 2.200 V 2.341 V
+5VS 5V switched power rail ON OFF OFF 7 NC 2.500 V 3.300 V 3.300 V
2 2
+VSB VSB always on power rail ON ON ON*
+RTCVCC RTC power ON ON ON
BOARD ID Table BTO Option Table
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
Board ID PCB Revision BTO Item BOM Structure
External PCI Devices 0 0.1 Discrete VGA@
Device IDSEL# REQ#/GNT# Interrupts 1 0.2 UMA UMA@
2 0.3 M92-M2 XT M92@
3 0.4 VRAM STRAP VRAM@
4 1.0 LAN 8121 8121@
5 LAN 8131 8131@
6 HDT debug HDT@
7 JMB385 CR JMB385@
RTS5159 CR RTS5159@
FOR PUMA PUMA@
EC SM Bus1 address EC SM Bus2 address FOR TIGRIS TIGRIS@
3 FOR TEST UB@ 3
Device Address HEX Device Address HEX
Smart Battery 0001 011X b 16H ADI ADM1032 (CPU) 1001 100X b 98H SB700 SB700 RS780MN DISPLAY OUTPUT
GMT G781-1 (GPU) 1001 101X b 9AH PX_GPIO0 PX_GPIO1 PX_GPIO2
SB-Temp Sensor 9CH Function Description dGPU_Reset dGPU_PWR_Enable PX Mode Switch
IGP only mode X X X
PowerXpress mode H : Enable H : Enable L : iGPU(DC) / H : dGPU(AC) LVDS / CRT
SB700 SB700
SM Bus 0 address SM Bus 1 address KB926
PX_GPIO1 PX_GPIO2 PX_+3VS PX_+1.8VS PX_+VGA_CORE PX_GPIO2_NB
Device Address HEX Device Address Function Description Enable +1.1VS_PX PX MODE SWITCH Enable +3VS_DELAY Enable +1.8VS_PX Enable +VGA_CORE Trigger from SB
New card IGP only mode X X X X X X
Clock Generator 1101 001Xb D2
(SILEGO SLG8SP626) PowerXpress mode H : Enable Reserved H : Enable H : Enable H : Enable Reserved
DDR DIMM1 1001 000Xb 90
KB926
DDR DIMM2 1001 010Xb 94
PX_GPIO1_SB
Mini card
Function Description Trigger from SB to Enable (PX_GPIO1/PX_+3VS/PX_+1.8VS/PX_+VGA_CORE)
4 4
IGP only mode X
PowerXpress mode H : Enable
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008/10/06 Deciphered Date 2009/10/06 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC A4921P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B
401679 C
Date: Thursday, March 26, 2009 Sheet 3 of 57
A B C D E
A B C D E
1 1
+1.2V_HT
VLDT CAP.
250 mil
1 1 1 1 1 1
C727 C666 C725 C726 C722 C668
H_CADIP[0..15] H_CADOP[0..15] 4.7U_0805_10V4Z 4.7U_0805_10V4Z 0.22U_0603_16V4Z 0.22U_0603_16V4Z 180P_0402_50V8J 180P_0402_50V8J
10 H_CADIP[0..15] H_CADOP[0..15] 10
H_CADIN[0..15] H_CADON[0..15] 2 2 2 2 2 2
10 H_CADIN[0..15] H_CADON[0..15] 10
PUMA@ PUMA@
Change as 10U Near CPU Socket
Change as 10U for Tigris
+1.2V_HT +1.2V_HT for Tigris
JCPU1A
PUMA@
2 2
D1 VLDT_A0 HT LINK VLDT_B0 AE2 1 2
D2 AE3 C664 4.7U_0805_10V4Z
VLDT=1.5A D3
VLDT_A1 VLDT_B1
AE4
VLDT_A2 VLDT_B2
D4 VLDT_A3 VLDT_B3 AE5
H_CADIP0 E3 AD1 H_CADOP0
H_CADIN0 L0_CADIN_H0 L0_CADOUT_H0 H_CADON0
E2 L0_CADIN_L0 L0_CADOUT_L0 AC1
H_CADIP1 E1 AC2 H_CADOP1
H_CADIN1 L0_CADIN_H1 L0_CADOUT_H1 H_CADON1
F1 L0_CADIN_L1 L0_CADOUT_L1 AC3
H_CADIP2 G3 AB1 H_CADOP2
H_CADIN2 L0_CADIN_H2 L0_CADOUT_H2 H_CADON2
G2 L0_CADIN_L2 L0_CADOUT_L2 AA1
H_CADIP3 G1 AA2 H_CADOP3
H_CADIN3 L0_CADIN_H3 L0_CADOUT_H3 H_CADON3
H1 L0_CADIN_L3 L0_CADOUT_L3 AA3
H_CADIP4 J1 W2 H_CADOP4
H_CADIN4 L0_CADIN_H4 L0_CADOUT_H4 H_CADON4
K1 L0_CADIN_L4 L0_CADOUT_L4 W3
H_CADIP5 L3 V1 H_CADOP5
H_CADIN5 L0_CADIN_H5 L0_CADOUT_H5 H_CADON5
L2 L0_CADIN_L5 L0_CADOUT_L5 U1
H_CADIP6 L1 U2 H_CADOP6
H_CADIN6 L0_CADIN_H6 L0_CADOUT_H6 H_CADON6
M1 L0_CADIN_L6 L0_CADOUT_L6 U3
H_CADIP7 N3 T1 H_CADOP7
H_CADIN7 L0_CADIN_H7 L0_CADOUT_H7 H_CADON7
N2 L0_CADIN_L7 L0_CADOUT_L7 R1
H_CADIP8 E5 AD4 H_CADOP8
H_CADIN8 L0_CADIN_H8 L0_CADOUT_H8 H_CADON8
F5 L0_CADIN_L8 L0_CADOUT_L8 AD3
H_CADIP9 F3 AD5 H_CADOP9
H_CADIN9 L0_CADIN_H9 L0_CADOUT_H9 H_CADON9
F4 L0_CADIN_L9 L0_CADOUT_L9 AC5
H_CADIP10 G5 AB4 H_CADOP10
H_CADIN10 L0_CADIN_H10 L0_CADOUT_H10 H_CADON10
H5 L0_CADIN_L10 L0_CADOUT_L10 AB3
H_CADIP11 H3 AB5 H_CADOP11
H_CADIN11 L0_CADIN_H11 L0_CADOUT_H11 H_CADON11
H4 L0_CADIN_L11 L0_CADOUT_L11 AA5
H_CADIP12 K3 Y5 H_CADOP12
H_CADIN12 L0_CADIN_H12 L0_CADOUT_H12 H_CADON12
K4 L0_CADIN_L12 L0_CADOUT_L12 W5
H_CADIP13 L5 V4 H_CADOP13
3 H_CADIN13 L0_CADIN_H13 L0_CADOUT_H13 H_CADON13 3
M5 L0_CADIN_L13 L0_CADOUT_L13 V3
H_CADIP14 M3 V5 H_CADOP14
H_CADIN14 L0_CADIN_H14 L0_CADOUT_H14 H_CADON14
M4 L0_CADIN_L14 L0_CADOUT_L14 U5
H_CADIP15 N5 T4 H_CADOP15
H_CADIN15 L0_CADIN_H15 L0_CADOUT_H15 H_CADON15
P5 L0_CADIN_L15 L0_CADOUT_L15 T3
10 H_CLKIP0 J3 L0_CLKIN_H0 L0_CLKOUT_H0 Y1 H_CLKOP0 10
10 H_CLKIN0 J2 L0_CLKIN_L0 L0_CLKOUT_L0 W1 H_CLKON0 10
10 H_CLKIP1 J5 L0_CLKIN_H1 L0_CLKOUT_H1 Y4 H_CLKOP1 10
10 H_CLKIN1 K5 L0_CLKIN_L1 L0_CLKOUT_L1 Y3 H_CLKON1 10
10 H_CTLIP0 N1 L0_CTLIN_H0 L0_CTLOUT_H0 R2 H_CTLOP0 10
10 H_CTLIN0 P1 L0_CTLIN_L0 L0_CTLOUT_L0 R3 H_CTLON0 10
10 H_CTLIP1 P3 L0_CTLIN_H1 L0_CTLOUT_H1 T5 H_CTLOP1 10
10 H_CTLIN1 P4 L0_CTLIN_L1 L0_CTLOUT_L1 R5 H_CTLON1 10
6090022100G_B conn@
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008/10/06 Deciphered Date 2009/10/06 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC A4921P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom
401679 C
Date: Thursday, March 26, 2009 Sheet 4 of 57
A B C D E
A B C D E
PLACE CLOSE TO PROCESSOR
Processor DDR2 Memory Interface
WITHIN 1.5 INCH
JCPU1C
9 DDRB_SDQ[63..0]
MEM:DATA
DDRA_SDQ[63..0] 8
DDRA_CLK0 DDRB_SDQ0 C11 G12 DDRA_SDQ0
1 +1.8V DDRB_SDQ1 MB_DATA0 MA_DATA0 DDRA_SDQ1 1
1 A11 MB_DATA1 MA_DATA1 F12
DDRB_SDQ2 A14 H14 DDRA_SDQ2
C379 DDRB_SDQ3 MB_DATA2 MA_DATA2 DDRA_SDQ3
B14 MB_DATA3 MA_DATA3 G14
2
1.5P_0402_50V9C DDRB_SDQ4 G11 H11 DDRA_SDQ4
R78 DDRA_CLK0# 2 DDRB_SDQ5 MB_DATA4 MA_DATA4 DDRA_SDQ5
E11 MB_DATA5 MA_DATA5 H12
1K_0402_1% DDRB_SDQ6 D12 C13 DDRA_SDQ6
DDRA_CLK1 DDRB_SDQ7 MB_DATA6 MA_DATA6 DDRA_SDQ7
A13 MB_DATA7 MA_DATA7 E13
1 DDRB_SDQ8 A15 H15 DDRA_SDQ8
MB_DATA8 MA_DATA8
1
+MCH_REF DDRB_SDQ9 A16 E15 DDRA_SDQ9
C111 DDRB_SDQ10 MB_DATA9 MA_DATA9 DDRA_SDQ10
1000P_0402_25V8J
0.1U_0402_16V4Z
A19 MB_DATA10 MA_DATA10 E17
2
1 1 1.5P_0402_50V9C DDRB_SDQ11 A20 H17 DDRA_SDQ11
R79 DDRA_CLK1# 2 DDRB_SDQ12 MB_DATA11 MA_DATA11 DDRA_SDQ12
C178
C177
C14 MB_DATA12 MA_DATA12 E14
1K_0402_1% DDRB_SDQ13 D14 F14 DDRA_SDQ13
DDRB_SDQ14 MB_DATA13 MA_DATA13 DDRA_SDQ14
C18 MB_DATA14 MA_DATA14 C17
2 2 DDRB_CLK0 DDRB_SDQ15 DDRA_SDQ15
D18 MB_DATA15 MA_DATA15 G17
1
1 DDRB_SDQ16 D20 G18 DDRA_SDQ16
DDRB_SDQ17 MB_DATA16 MA_DATA16 DDRA_SDQ17
A21 MB_DATA17 MA_DATA17 C19
C380 DDRB_SDQ18 D24 D22 DDRA_SDQ18
1.5P_0402_50V9C DDRB_SDQ19 MB_DATA18 MA_DATA18 DDRA_SDQ19
C25 MB_DATA19 MA_DATA19 E20
DDRB_CLK0# 2 DDRB_SDQ20 DDRA_SDQ20
B20 MB_DATA20 MA_DATA20 E18
DDRB_SDQ21 C20 F18 DDRA_SDQ21
DDRB_CLK1 DDRB_SDQ22 MB_DATA21 MA_DATA21 DDRA_SDQ22
B24 MB_DATA22 MA_DATA22 B22
1 DDRB_SDQ23 C24 C23 DDRA_SDQ23
DDRB_SDQ24 MB_DATA23 MA_DATA23 DDRA_SDQ24
E23 MB_DATA24 MA_DATA24 F20
C112 DDRB