Text preview for : MS-6561.pdf part of Microstar MS-6561 Microstar MS-6561.pdf
Back to : MS-6561.pdf | Home
5 4 3 2 1
MS-6561 VER:1.0
D CPU: AMD Socket-462 Processor CONTENT PAGE CONTENT PAGE D
Cover Page 1 Voltage Regulator 33,34
Chipset: SiS 745 Block Diagram 2 ATX Connector 35
LPC I/O: W83697HF
Clock Generator 3 Front Pannel 36
Clock Buffer 4 Decoupling Capacitors 37
AC'97 CODEC:Realtek ALC201A
AMD Socket A 5,6,7 MS-3 & D-LED 38
SiS 745 Host / AGP 8 1394 PHY 39
IEEE1394 : TI TSB41LV02(OPTION) SiS 745 Memory 9 CPU Thermal Portection 40
SiS 745 PCI / IDE 10 Manual Part 41
C
Expansion: SiS 745 Misc. Signal 11 GPIO SPEC. 42 C
1.AGP Slot * 1
SiS 745 Power 12
Hardware Strap 13
2.PCI Slot * 5 System Memory 14,15,16
3.CNR Slot * 1 PCI Connector 17,18,19
AGP Slot 20
IDE Connector 21
USB Connector 22
KB/MS Connector 23
B
AC'97 CODEC 24 B
Audio Connector 25
CNR Slot 26
LPC I/O W83697HF 27
Hardware Monitor 28
Parallel Port 29
Serial Port 30
Flash Memory 31
PWM ST-L6911D 32
A A
Micro Star Restricted Secret
Title Rev
Cover Sheet
Document Number 1.0
MS-6561
MICRO-STAR INT'L CO.,LTD. Last Revision Date:
Tuesday, February 19, 2002
No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan Sheet
http://www.msi.com.tw 1 of 42
5 4 3 2 1
5 4 3 2 1
D
VRM 9.0 K7 462-Pin Socket Processor Clock D
ADDR(In-Out)
PWR-MNG
DATA
INT & PWR-MNG
AGP 2X/4X
UltraDMA
IDE Primary 33/66/100 3 DDR
Modules
C C
IDE Secondary PC-266
PCI 2.2
USB Port 1 USB
USB Port 2 SIS745
PCI CNTRL
PCI Conn 1
PCI Conn 2
PCI Conn 3
PCI Conn 4
PCI Conn 5
USB Port 3
USB Port 4 PCI ADDR/DATA
IEEE 1394
1394 PHY
B TI-TSB41AB3 B
AC'97 Link
Onboard
AC'97 Codec
LPC
ISA Bus
Flash
CNR ROM
WINBOND
W83697HF
A
Floopy Parallel A
Serial Micro Star Restricted Secret
Title Rev
Block Diagram
Document Number 1.0
MS-6561
MICRO-STAR INT'L CO.,LTD. Last Revision Date:
Tuesday, February 19, 2002
No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan Sheet
http://www.msi.com.tw 2 of 42
5 4 3 2 1
5 4 3 2 1
CP16
X_COPPER
U7
D VCC3_3 L18 D
1 2 1 VDDREF
11 44 R126 10 CPUCLK 733CCLK C195 10P
VDDPCI CPUCLK0 CPUCLK 5
17 43 R127 10 CPUCLK#
VDDAGP CPUCLK#0 CPUCLK# 5
C259 X_80S_0805 C392 C209 C220 C245 C263 C208 C207 21 40 R128 22 733CCLK CPUCLK C192 10P
104P VDD48M CPUCLK1 733CCLK 8
4.7U_0805 104P 104P 104P 104P 104P 104P 36 VDDSDRAM CPUCLK# C193 10P
25 VDDCORE
47 R120 10 APICCLK0
APICCLK APICCLK0 5
R371 10 APICCLK1 733PCLK C249 10P
APICCLK1 11
32 35 R129 10 733DCLK
CPUSTP# SDRAMCLK 733DCLK 9
30 SDRAMSTOP#
29 APICCLK0 C394 X_10P
AGPSTOP# R169 22 733ACLK
33 PCISTP# AGPCLK0 18 733ACLK 8
31 19 R170 22 AGPCLK1 APICCLK1 C385 X_10P
PD# AGPCLK1 AGPCLK1 20
7 8 733PCLK
733PCLK 10
4 9 FS2 5 6 SIOPCLK PCICLK1 C384 X_10P
VSSREF FS2/PCICLK_F SIOPCLK 27
5 10 FS3 3 4 PCICLK1
VSSOSC FS3/PCICLK1 PCICLK1 17
8 12 1 2 SIOPCLK C383 X_10P
VSSPCI PCICLK2
14 VSSPCI PCICLK3 13
CP2 RN56 8P4R-22 CN19
20 VSSAGP PCICLK4 15
24 16 PCICLK2 7 8
VSS48M PCICLK5 PCICLK2 PCICLK3
34 VSSSDRAM 7 8 PCICLK2 18 5 6
X_COPPER 26 5 6 PCICLK3 PCICLK4 3 4
VSSCORE PCICLK3 18
2 FS0 3 4 PCICLK4 PCICLK5 1 2
FS0/REF0 PCICLK4 19
VCC2_5 L17 3 FS1 1 2 PCICLK5
FS1/REF1 PCICLK5 19
X_8P4C-10P
C 1 2 45 RN57 8P4R-22 C
VDDCPU OSCI C264 10P
41 22
1
VDDCPU 48MHZ AGPSEL R175 33 OSCI
48 VDDAPIC AGPSEL/24_48MHZ 23 OSCI 11
+ EC71 C211 X_80S_0805 C204 C205 C206 C391 R176 33 OSCI1
OSCI1 38
UCLK48M C252 10P
10U/16VS 104P 104P 104P 104P 4.7U_0805 R537 X_33 AU_XIN
AU_XIN 24
42 SIO48M C260 10P
VSSCPU
2
39 VSSCPU SCLK 27
46 28 R171 22 733DCLK C197 22P
VSSAPIC SDATA UCLK48M 11
R177 22
C244 SIO48M 27
AGPCLK1 C251 10P
R131 100
SCLK 4,11,14,15,26,33,38
6 37 R130 100 733ACLK C250 10P
XIN RSVD SDATA 4,11,14,15,26,33,38
10P 38
Y2 RSVD OSCI1 C265 10P
C203 14.318MHz AU_XIN C477 X_10P
7 XOUT
10P
ICS9248-199
VCC3_3
B B
RN59
FS3 1 2
FS2 3 4
FS1 5 6
FS0 7 8
8P4R-10K
AGPSEL R172 10K
SIS745 CLOCK AGPCLK
(MHz)
(FS3) (FS2) (FS1) (FS0) CPU SDRAM PCI AGPSEL=0 AGPSEL=1
(MHz) (MHz) (MHz)
0 0 0 0 66.6 66.6 33.3 66.6 50
0 0 0 1 100 100 33.3 66.6 50
0 0 1 0 166 166 33.3 66.6 55.6
0 0 1 1 133 133 33.3 66.6 50
0 1 0 0 66.6 100 33.3 66.6 50
0 1 0 1 100 66.6 33.3 66.6 50
0 1 1 0 100 133 33.3 66.6 50
A A
0 1 1 1 133 100 33.3 66.6 50
1 0 0 0 112 112 33.6 67.2 56
1 0 0 1 124 124 31 62 46.5
1
1
0
0
1
1
0
1
138
150
138
150
34.5
30
69
60
51.8
50
Micro Star Restricted Secret
1 1 0 0 66.6 133 33.3 62.5 49.84 Title Rev
1 1 0 1 133 166 33.3 66.6 55.3 Clock Generator
1 1 1 0 150 100 30 60 50 Document Number 1.0
1 1 1 1 160 120 30 60 48 MS-6561
NOTE: MICRO-STAR INT'L CO.,LTD. Last Revision Date:
PCICLK<34.5MHz Tuesday, February 19, 2002
No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan Sheet
http://www.msi.com.tw 3 of 42
5 4 3 2 1
5 4 3 2 1
D Clock Buffer (DDR) D
CP3
DDRCLK[0..8]
DDRCLK[0..8] 14,15
X_COPPER
DDRCLK-[0..8]
DDRCLK-[0..8] 14,15
L50
1 2 CBVDDR2 SCLK
VCC2_5 SCLK 3,11,14,15,26,33,38
SDATA
SDATA 3,11,14,15,26,33,38
X_80_0805
BC40 FWDCLK_DDR
FWDCLK_DDR 9
1
1
1
1
1
1
1
C427 BC37 BC39 BC41 BC42 BC43 BC44 BC38
0.1u 0.1u 0.1u 0.1u 0.1u 0.1u 0.1u
4.7U_0805
2
2
2
2
2
2
2
47U/10VS
V_CORE
By-Pass Capacitors
Place near to the Clock Buffer
U24 DDRCLK3 C428 1 2 10p-0603
C C
RN112 1 48 DDRCLK-5 C429 1 2 10p-0603
DDRCLK-3 GND GND RN113
1 2 2 CLKC0 CLKC5 47
DDRCLK3 3 4 3 46 1 2 DDRCLK-1 DDRCLK0 C430 1 2 10p-0603
DDRCLK5 CLKT0 CLKT5 DDRCLK1
5 6 4 VDD VDD 45 3 4
DDRCLK-5 7 8 5 44 5 6 DDRCLK4 DDRCLK-2 C431 1 2 10p-0603
CLKT1 CLKT6 DDRCLK-4
6 CLKC1 CLKC6 43 7 8
0-0603 7 42 DDRCLK-1 C432 1 2 10p-0603
GND GND 0-0603
8 GND GND 41
DDRCLK-0 R460
1 2 0_0603 9 40 DDRCLK-8 C433 1 2 10p-0603
DDRCLK0 R461 CLKC2 CLKC7
1 2 0_0603 10 CLKT2 CLKT7 39
11 38 DDRCLK4 C434 1 2 10p-0603
CB1SCLK VDD VDD CB1SDATA
12 SCLK SDATA 37
X_80_0805 FWDCLK_DDR 13 36 DDRCLK7 C435 1 2 10p-0603
L51 1 CLK_INT FB_INC FB_DDR
2 14 CLK_INC FB_INT 35
VCC2_5 15 34 DDRCLK6 C436 1 2 10p-0603
1
1
BC45 BC46 VDD VDD R462
16 AVDD FB_OUTT 33 1 2 0_0603 FB_DDR
CP15 47U/10VS C437 0.01u 0.1u 17 AGND FB_OUTC 32
18 31 RN114
GND GND
2
2
19 30 1 2 DDRCLK-6 DDRCLK-3 C438 1 2 10p-0603
DDRCLK-2 CLKC3 CLKC8 DDRCLK6
1 2 20 CLKT3 CLKT8 29 3 4
X_COPPER DDRCLK2 3 4 21 28 5 6 DDRCLK7 DDRCLK5 C439 1 2 10p-0603
DDRCLK8 VDD VDD DDRCLK-7
5 6 22 CLKT4 CLKT9 27 7 8
DDRCLK-8 7 8 23 26 DDRCLK-0 C440 1 2 10p-0603
CLKC4 CLKC9 0-0603
24 GND GND 25
RN115 0-0603 DDRCLK2 C441 1 2 10p-0603
ICS-ICS93705CF DDRCLK1 C442 1 2 10p-0603
B DDRCLK8 C443 1 B
2 10p-0603
DDRCLK-4 C444 1 2 10p-0603
SCLK R465
1 2 0_0603 CB1SCLK DDRCLK-7 C445 1 2 10p-0603
SDATA R466
1 2 0_0603 CB1SDATA
DDRCLK-6 C446 1 2 10p-0603
FB_DDR C447 1 2 10p-0603
A A
Micro Star Restricted Secret
Title Rev
Clock Buffer
Document Number 1.0
MS-6561
MICRO-STAR INT'L CO.,LTD. Last Revision Date:
Tuesday, February 19, 2002
No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan Sheet
http://www.msi.com.tw 4 of 42
5 4 3 2 1
5 4 3 2 1
CPU FERR BLOCK
AMD 462PGA Socket - Signals SADDINCLK#
SADDINCLK# 8
VCC3_3
CPU1A
SDATA#0 AA35 AE1 A20M# SDATAINCLK#0
8 SDATA#[0..63] SDATA0 A20M A20M# 7,11 SDATAINCLK#[0..3] 8
SDATA#1 W37 AG1 FERR SDATAINCLK#1
SDATA#2 SDATA1 FERR INIT#_39491 SDATAINCLK#2 V_CORE R27
W35 SDATA2 INIT AJ3 INIT# 7,11
SDATA#3 Y35 AL1 INTR SDATAINCLK#3 4.7K
SDATA3 INTR INTR 7,11
SDATA#4 U35 AJ1 IGNNE#
SDATA4 IGNNE IGNNE# 7,11
SDATA#5 U33 AN3 NMI
SDATA5 NMI NMI 7,11
SDATA#6 S37 AG3 CPURST# R22
SDATA6 RESET CPURST# 7,8 4.7K FERR# 11
D SDATA#7 S33 AN5 SMI# D
SDATA7 SMI SMI# 7,11
SDATA#8 AA33 AC1 STPCLK#
C
SDATA8 STPCLK STPCLK# 7,11
SDATA#9 AE37
SDATA#10 SDATA9 CPU_PWOK FERR Q8
AC33 SDATA10 PWROK AE3 CPU_PWOK 33 B
SDATA#11 L37 L40 2N3904
AC37 SDATA11
SDATA#12 Y37 SDINCLK# SADDINCLK#
SDATA12
E
SDATA#13 AA37 N1 APICCLK0 10n 10n
SDATA13 PICCLK APICCLK0 3
SDATA#14 AC35 N3 APICD0 C347
SDATA14 PICD0/BYPASSCLK APICD0 7,11
SDATA#15 S35 N5 APICD1 5P
SDATA15 PICD1/BYPASSCLK APICD1 7,11
SDATA#16 Q37
SDATA#17 SDATA16 COREFB-
Q35 SDATA17 COREFB- AG13 COREFB- 7
SDATA#18 COREFB+
SDATA#19
N37
J33
SDATA18 COREFB+ AG11 COREFB+ 7 CPU SYSCLK BLOCK
SDATA#20 SDATA19 SYSCLK
G33 SDATA20 CLKIN AN17
SDATA#21 SYSCLK# L35 L38
G37 SDATA21 CLKIN AL17
SDATA#22 E37 SDINCLK#0 SDATAINCLK#0 V_CORE
SDATA22