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5 4 3 2 1
D D
PEG_ICOMPI and RCOMPO signals should
be shorted and routed
with - max length = 500 mils - typical
+1.05VS_VCCP impedance = 43 mohms
PEG_ICOMPO signals should be routed with -
1
max length = 500 mils
R419
24.9_0402_1%
- typical impedance = 14.5 mohms
JCPU1A
2
J22 PEG_COMP
PEG_ICOMPI
J21
PEG_ICOMPO
<16> DMI_CRX_PTX_N0 B27 H22
DMI_RX#[0] PEG_RCOMPO
<16> DMI_CRX_PTX_N1 B25 DMI_RX#[1]
<16> DMI_CRX_PTX_N2 A25
DMI_RX#[2] PEG_GTX_C_HRX_N15
<16> DMI_CRX_PTX_N3 B24 DMI_RX#[3] PEG_RX#[0] K33
M35 PEG_GTX_C_HRX_N14
PEG_RX#[1] PEG_GTX_C_HRX_N13
<16> DMI_CRX_PTX_P0 B28 L34
DMI_RX[0] PEG_RX#[2] PEG_GTX_C_HRX_N12
<16> DMI_CRX_PTX_P1 B26 J35
DMI_RX[1] PEG_RX#[3] PEG_GTX_C_HRX_N11
<16> DMI_CRX_PTX_P2 A24 J32
DMI
DMI_RX[2] PEG_RX#[4] PEG_GTX_C_HRX_N10
<16> DMI_CRX_PTX_P3 B23 DMI_RX[3] PEG_RX#[5] H34
H31 PEG_GTX_C_HRX_N9
PEG_RX#[6] PEG_GTX_C_HRX_N8
<16> DMI_CTX_PRX_N0 G21 DMI_TX#[0] PEG_RX#[7] G33
E22 G30 PEG_GTX_C_HRX_N7
<16> DMI_CTX_PRX_N1 DMI_TX#[1] PEG_RX#[8] PEG_GTX_C_HRX_N6
<16> DMI_CTX_PRX_N2 F21 F35
DMI_TX#[2] PEG_RX#[9] PEG_GTX_C_HRX_N5
<16> DMI_CTX_PRX_N3 D21 DMI_TX#[3] PEG_RX#[10] E34 PEG_GTX_C_HRX_N[0..15] <23>
E32 PEG_GTX_C_HRX_N4
PEG_RX#[11] PEG_GTX_C_HRX_N3 PEG_GTX_C_HRX_P[0..15] <23>
<16> DMI_CTX_PRX_P0 G22 D33
DMI_TX[0] PEG_RX#[12] PEG_GTX_C_HRX_N2
<16> DMI_CTX_PRX_P1 D22 D31 PEG_HTX_C_GRX_N[0..15] <23>
C DMI_TX[1] PEG_RX#[13] PEG_GTX_C_HRX_N1 C
<16> DMI_CTX_PRX_P2 F20 DMI_TX[2] PEG_RX#[14] B33 PEG_HTX_C_GRX_P[0..15] <23>
PCI EXPRESS* - GRAPHICS
C21 C32 PEG_GTX_C_HRX_N0
<16> DMI_CTX_PRX_P3 DMI_TX[3] PEG_RX#[15]
J33 PEG_GTX_C_HRX_P15
PEG_RX[0] PEG_GTX_C_HRX_P14
PEG_RX[1] L35
K34 PEG_GTX_C_HRX_P13
PEG_RX[2] PEG_GTX_C_HRX_P12
<16> FDI_CTX_PRX_N0 A21 FDI0_TX#[0] PEG_RX[3] H35
H19 H32 PEG_GTX_C_HRX_P11
<16> FDI_CTX_PRX_N1 FDI0_TX#[1] PEG_RX[4] PEG_GTX_C_HRX_P10
<16> FDI_CTX_PRX_N2 E19 FDI0_TX#[2] PEG_RX[5] G34
F18 G31 PEG_GTX_C_HRX_P9
<16> FDI_CTX_PRX_N3 FDI0_TX#[3] PEG_RX[6]
Intel(R) FDI
B21 F33 PEG_GTX_C_HRX_P8
<16> FDI_CTX_PRX_N4 FDI1_TX#[0] PEG_RX[7]
C20 F30 PEG_GTX_C_HRX_P7
<16> FDI_CTX_PRX_N5 FDI1_TX#[1] PEG_RX[8]
D18 E35 PEG_GTX_C_HRX_P6
<16> FDI_CTX_PRX_N6 FDI1_TX#[2] PEG_RX[9] PEG_GTX_C_HRX_P5
<16> FDI_CTX_PRX_N7 E17 E33
FDI1_TX#[3] PEG_RX[10] PEG_GTX_C_HRX_P4
F32
PEG_RX[11] PEG_GTX_C_HRX_P3
D34
PEG_RX[12] PEG_GTX_C_HRX_P2
<16> FDI_CTX_PRX_P0 A22 E31
FDI0_TX[0] PEG_RX[13] PEG_GTX_C_HRX_P1
<16> FDI_CTX_PRX_P1 G19 C33
FDI0_TX[1] PEG_RX[14] PEG_GTX_C_HRX_P0
<16> FDI_CTX_PRX_P2 E20 B32
FDI0_TX[2] PEG_RX[15]
<16> FDI_CTX_PRX_P3 G18 FDI0_TX[3]
B20 M29 PEG_HTX_GRX_N15 C547 1 2 OPT@ 0.1U_0402_10V7K PEG_HTX_C_GRX_N15
<16> FDI_CTX_PRX_P4 FDI1_TX[0] PEG_TX#[0]
C19 M32 PEG_HTX_GRX_N14 C545 1 2 OPT@ 0.1U_0402_10V7K PEG_HTX_C_GRX_N14
<16> FDI_CTX_PRX_P5 FDI1_TX[1] PEG_TX#[1] PEG_HTX_GRX_N13 PEG_HTX_C_GRX_N13
D19 M31 C543 1 2 OPT@ 0.1U_0402_10V7K
<16> FDI_CTX_PRX_P6 FDI1_TX[2] PEG_TX#[2]
F17 L32 PEG_HTX_GRX_N12 C541 1 2 OPT@ 0.1U_0402_10V7K PEG_HTX_C_GRX_N12
<16> FDI_CTX_PRX_P7 FDI1_TX[3] PEG_TX#[3] PEG_HTX_GRX_N11 PEG_HTX_C_GRX_N11
L29 C555 1 2 OPT@ 0.1U_0402_10V7K
+1.05VS_VCCP PEG_TX#[4] PEG_HTX_GRX_N10 C553 OPT@ 0.1U_0402_10V7K PEG_HTX_C_GRX_N10
<16> FDI_FSYNC0 J18 K31 1 2
FDI0_FSYNC PEG_TX#[5] PEG_HTX_GRX_N9 C556 OPT@ 0.1U_0402_10V7K PEG_HTX_C_GRX_N9
<16> FDI_FSYNC1 J17 FDI1_FSYNC PEG_TX#[6] K28 1 2
J30 PEG_HTX_GRX_N8 C561 1 2 OPT@ 0.1U_0402_10V7K PEG_HTX_C_GRX_N8
PEG_TX#[7] PEG_HTX_GRX_N7 C563 OPT@ 0.1U_0402_10V7K PEG_HTX_C_GRX_N7
<16> FDI_INT H20 J28 1 2
FDI_INT PEG_TX#[8] PEG_HTX_GRX_N6 PEG_HTX_C_GRX_N6
eDP_COMPIO and ICOMPO signals PEG_TX#[9]
H29 C569 1 2 OPT@ 0.1U_0402_10V7K
1
J19 G27 PEG_HTX_GRX_N5 C571 1 2 OPT@ 0.1U_0402_10V7K PEG_HTX_C_GRX_N5
should be shorted near balls R106
<16> FDI_LSYNC0
H17
FDI0_LSYNC PEG_TX#[10]
E29 PEG_HTX_GRX_N4 C574 1 2 OPT@ 0.1U_0402_10V7K PEG_HTX_C_GRX_N4
<16> FDI_LSYNC1 FDI1_LSYNC PEG_TX#[11]
B and routed with typical 24.9_0402_1% F27 PEG_HTX_GRX_N3 C576 1 2 OPT@ 0.1U_0402_10V7K PEG_HTX_C_GRX_N3 B
PEG_TX#[12] PEG_HTX_GRX_N2 C579 OPT@ 0.1U_0402_10V7K PEG_HTX_C_GRX_N2
impedance <25 mohms PEG_TX#[13] D28 1 2
F26 PEG_HTX_GRX_N1 C582 1 2 OPT@ 0.1U_0402_10V7K PEG_HTX_C_GRX_N1
2
PEG_TX#[14] PEG_HTX_GRX_N0 C587 OPT@ 0.1U_0402_10V7K PEG_HTX_C_GRX_N0
PEG_TX#[15] E25 1 2
EDP_COMP A18
eDP_COMPIO PEG_HTX_GRX_P15 C546 OPT@ 0.1U_0402_10V7K PEG_HTX_C_GRX_P15
A17 M28 1 2
eDP_ICOMPO PEG_TX[0] PEG_HTX_GRX_P14 C544 OPT@ 0.1U_0402_10V7K PEG_HTX_C_GRX_P14
B16 M33 1 2
eDP_HPD PEG_TX[1] PEG_HTX_GRX_P13 C542 OPT@ 0.1U_0402_10V7K PEG_HTX_C_GRX_P13
M30 1 2
PEG_TX[2] PEG_HTX_GRX_P12 C540 OPT@ 0.1U_0402_10V7K PEG_HTX_C_GRX_P12
L31 1 2
PEG_TX[3] PEG_HTX_GRX_P11 C554 OPT@ 0.1U_0402_10V7K PEG_HTX_C_GRX_P11
C15 eDP_AUX PEG_TX[4] L28 1 2
D15 K30 PEG_HTX_GRX_P10 C552 1 2 OPT@ 0.1U_0402_10V7K PEG_HTX_C_GRX_P10
eDP_AUX# PEG_TX[5] PEG_HTX_GRX_P9 C557 OPT@ 0.1U_0402_10V7K PEG_HTX_C_GRX_P9
K27 1 2
eDP
PEG_TX[6] PEG_HTX_GRX_P8 C562 OPT@ 0.1U_0402_10V7K PEG_HTX_C_GRX_P8
PEG_TX[7] J29 1 2
C17 J27 PEG_HTX_GRX_P7 C565 1 2 OPT@ 0.1U_0402_10V7K PEG_HTX_C_GRX_P7
eDP_TX[0] PEG_TX[8] PEG_HTX_GRX_P6 C570 OPT@ 0.1U_0402_10V7K PEG_HTX_C_GRX_P6
F16 eDP_TX[1] PEG_TX[9] H28 1 2
C16 G28 PEG_HTX_GRX_P5 C572 1 2 OPT@ 0.1U_0402_10V7K PEG_HTX_C_GRX_P5
eDP_TX[2] PEG_TX[10] PEG_HTX_GRX_P4 C575 OPT@ 0.1U_0402_10V7K PEG_HTX_C_GRX_P4
G15 E28 1 2
eDP_TX[3] PEG_TX[11] PEG_HTX_GRX_P3 C577 OPT@ 0.1U_0402_10V7K PEG_HTX_C_GRX_P3
F28 1 2
PEG_TX[12] PEG_HTX_GRX_P2 C581 OPT@ 0.1U_0402_10V7K PEG_HTX_C_GRX_P2
C18 D27 1 2
eDP_TX#[0] PEG_TX[13] PEG_HTX_GRX_P1 C585 OPT@ 0.1U_0402_10V7K PEG_HTX_C_GRX_P1
E16 E26 1 2
eDP_TX#[1] PEG_TX[14] PEG_HTX_GRX_P0 C588 OPT@ 0.1U_0402_10V7K PEG_HTX_C_GRX_P0
D16 D25 1 2
eDP_TX#[2] PEG_TX[15]
F15 eDP_TX#[3]
SUYIN_100361HK988_SANDY BRIDGE
CONN@
A A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/09/28 Deciphered Date 2011/09/28 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PROCESSOR(1/7) DMI,FDI,PEG
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
P4LS0 M/B LA-7241P Schematic
Date: Thursday, December 23, 2010 Sheet 4 of 55
5 4 3 2 1
5 4 3 2 1
D D
+3VS
XDP_DBRESET# R407 2 1 1K_0402_5%
For eDP
CLK_CPU_DPLL_R R410 1 @ 2 0_0402_5% CLK_CPU_DPLL <15>
CLK_CPU_DPLL#_R R413 1 @ 2 0_0402_5% CLK_CPU_DPLL# <15>
JCPU1B
C C
A28 CLK_CPU_DMI
BCLK CLK_CPU_DMI# CLK_CPU_DMI <15>
C26 A27
MISC
CLOCKS
<18> H_SNB_IVB# PROC_SELECT# BCLK# CLK_CPU_DMI# <15>
AN34
+1.05VS_VCCP SKTOCC# CLK_CPU_DPLL_R
Processor Pullups DPLL_REF_CLK A16 R409 1 2 1K_0402_5%
A15 CLK_CPU_DPLL#_R R414 1 2 1K_0402_5%
DPLL_REF_CLK# +1.05VS_VCCP
R67 2 1 62_0402_5% H_PROCHOT#
T9 PAD H_CATERR# AL33 CATERR#
DDR3 compensation Signals
THERMAL
AN33 R8 H_DRAMRST# SM_RCOMP0 R151 2 1 140_0402_1%
<19,39> H_PECI PECI SM_DRAMRST# H_DRAMRST# <6>
R70 2 1 10K_0402_5% H_CPUPWRGD R72 SM_RCOMP1 R436 2 1 25.5_0402_1%
DDR3
MISC
56_0402_5%
1 2 H_PROCHOT#_R AL32 AK1 SM_RCOMP0 SM_RCOMP2 R437 2 1 200_0402_1%
<39,50> H_PROCHOT# PROCHOT# SM_RCOMP[0]
A5 SM_RCOMP1
SM_RCOMP[1] SM_RCOMP2
A4
SM_RCOMP[2]
<19> H_THRMTRIP# AN32
THERMTRIP#
PU/PD for JTAG signals
+3VS
Buffered reset to CPU
AP29
PRDY#
AP27
PREQ#
+1.05VS_VCCP AR26 PAD T7
TCK
1
C74 AR27 PAD T27
PWR MANAGEMENT
TMS
JTAG & BPM
B 0.1U_0402_16V4Z PAD T25 B
<16> H_PM_SYNC AM34 PM_SYNC TRST# AP30
1
2
R84 AR28 PAD T26 Del resister and add test point
75_0402_5% TDI PAD T6
TDO AP26
<19> H_CPUPWRGD H_CPUPWRGD AP33
UNCOREPWRGOOD
5
U8 R85
2
1 43_0402_1% R150
P
NC BUFO_CPU_RST#
4 1 2 BUF_CPU_RST# 130_0402_5% AL35 DBRESET#_R 1 R402 2 0_0402_5% XDP_DBRESET#
XDP_DBRESET# <16>
PLT_RST# 2 Y PM_SYS_PWRGD_BUF 1 DBR#
2 PM_DRAM_PWRGD_R V8
A SM_DRAMPWROK
G
1
SN74LVC1G07DCKR_SC70-5
@ AT28
3
R86 BPM#[0]
AR29
0_0402_5% BPM#[1]
BPM#[2] AR30
BUF_CPU_RST# AR33 AT30
PLT_RST# <18,35,38,39,44>
2
RESET# BPM#[3]
BPM#[4] AP32
AR31
BPM#[5]
AT31
BPM#[6]
AR32
BPM#[7]
+3VALW
Follow DG 0.71
SUYIN_100361HK988_SANDY BRIDGE
+1.5V_CPU_VDDQ CONN@
1
+3VS C280
0.1U_0402_16V4Z
1
2
R149
U11 200_0402_5%
R440 74AHC1G09GW_TSSOP5
5
10K_0402_5%
2
1 2 1
P
A B PM_SYS_PWRGD_BUF A
4
O
<16> PM_DRAM_PWRGD 2 A
G
1
3
@
R153
39_0402_5%
Security Classification Compal Secret Data Compal Electronics, Inc.
1 2
D @ Issued Date 2010/09/28 Deciphered Date 2011/09/28 Title
SUSP 2 Q19
<46,53> SUSP
G 2N7002E_SOT23-3
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PROCESSOR(2/7) PM,XDP,CLK
S Size Document Number Rev
3
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
P4LS0 M/B LA-7241P Schematic
Date: Thursday, December 23, 2010 Sheet 5 of 55
5 4 3 2 1
5