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A B C D E
1 1
Compal Confidential
2 2
Cougar
LA-6851P Schematics Document
Intel Pine View Processor/ Tiger point
3
2010-10-10 3
REV: 1.0
Toshiba Satellite NB500 NB505
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/06/27 Deciphered Date 2011/6/27 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC MB A6851
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401986
Date: Friday, September 02, 2011 Sheet 1 of 36
A B C D E
A B C D E
Compal Confidential
Model Name : PBU00
File Name : LA-6851P
1
Thermal Sensor Low Power Clock Generator 1
Fan Control EMC1402 ICS9LVRS387AKLFT MLF
page 24
page 7 page 9
CRT Conn.
page 15
Memory BUS(DDRIII) 204pin DDRIII-SO-DIMM
Intel Pineview-M page 10
LED Conn. LVDS
page 16 ONE CHANNEL (22x22mm) page 6,7,8 1.5V DDRIII 667
2
DMI x 2 2
PCIeMini Card
WWAN USB Conn X3 Int. Camera
(FULL)
USB port 6 USB USB USB port 0,1,4 USB port 7
page 16
5V 480MHz 5V 480MHz page 18,21 page 16
PCIeMini Card
PCIe 1x [2]
WLAN +BT COMBO (HALF) 1.5V 2.5GHz(250MB/s)
Tiger Pointer
PCIe port 2 USB
page 16 Card Reader Card Reader Conn.
RTL5137 page 23
PCIe 1x USB port 3 page 23
(17x17mm)
RJ45 RTL8105E 1.5V 2.5GHz(250MB/s) SATA port 0 SATA HDD
page 22
10/100 LAN 5V 1.5GHz(150MB/s)
page 19
PCIe port 3 page 22
page 11,12,13,14
3 3
RTC CKT.
page 13 HD Audio 3.3V 24.576MHz/48Mhz
3.3V 33 MHz
LPC BUS
DC/DC Interface CKT. HDA Codec
ALC269
page 26 page 20
ENE KB926 E0
page 24
Power Circuit DC/DC
Int.
page 27~35 MIC CONN MIC CONN HP CONN SPK CONN
page 20 page 21 page 21 page 21
Touch Pad Int.KBD SPI ROM (10A 1X) (10B 2X)
page 26 page 25 page 25
4
Power/B 4
page 26
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/06/27 Deciphered Date 2011/6/27 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC MB A6851
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401986
Date: Friday, September 02, 2011 Sheet 2 of 36
A B C D E
A B C D E
Voltage Rails
1 SIGNAL 1
STATE SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
Power Plane Description S1 S3 S5 G3
Full ON HIGH HIGH HIGH ON ON ON ON
VIN Adapter power supply (19V) ON ON ON OFF
B+ AC or battery power rail for power circuit. ON ON ON ON S1(Power On Suspend) HIGH HIGH HIGH ON ON ON LOW
+CPU_CORE Core voltage for CPU ON OFF OFF OFF
S3 (Suspend to RAM) LOW HIGH HIGH ON ON OFF OFF
+0.89VS 0.89VS GFX support voltage ON OFF OFF OFF
+0.75VS 0.75V switched power rail for DDR terminator ON OFF OFF OFF S4 (Suspend to Disk) LOW LOW HIGH ON OFF OFF OFF
+1.05VS VCCP switched power rail ON OFF OFF OFF
S5 (Soft OFF) LOW LOW LOW ON OFF OFF OFF
+1.5VS 1.5V switched power rail ON OFF OFF OFF
+1.5V 1.5V power rail for DDR ON ON OFF OFF
+1.8VS 1.8VS switched power rail ON OFF OFF OFF
+3VALW 3.3V always on power rail ON ON ON OFF
+3V_LAN 3.3V power rail for LAN ON ON OFF OFF
BTO Option Table
+3V_WLAN 3.3V power rail for LAN ON ON OFF OFF
2 +3VS 3.3V switched power rail ON ON OFF OFF 2
+5VALW 5V always on power rail ON OFF ON OFF Function Mini PCI-E SLOT CAMERA & MIC BLUE TOOTH Clock gen
+5VS 5V switched power rail ON OFF OFF OFF
+VSB VSB always on power rail ON ON ON OFF
description
+RTCVCC RTC power ON ON ON ON explain Wi-Fi WiMax 3GGPS 3G CAMERA MIC BLUE TOOTH Tpye
BTO WLAN@ WIMAX@ 3GGPS@ 3G@ CAM@ MIC@ BT@ low@ normal@
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
Function
description
explain
BTO
3 3
EC SM Bus1 address EC SM Bus2 address
Device Address Device Address
Smart Battery 0001 011X b EMC1402 1001 010X b
ICH7M SM Bus address
Device Address
Clock Generator 1101 001Xb
(SLG8SP556VTR)
DDR DIMMA 1010 000Xb
WWAN/WLAN
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/06/27 Deciphered Date 2011/6/27 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC MB A6851
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401986
Date: Friday, September 02, 2011 Sheet 3 of 36
A B C D E
5 4 3 2 1
D D
C C
B B
A
Security Classification Compal Secret Data Compal Electronics, Inc. A
Issued Date 2010/06/27 Deciphered Date 2011/6/27 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC MB A6851
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401986
Date: Friday, September 02, 2011 Sheet 4 of 36
5 4 3 2 1
5 4 3 2 1
B+ DESIGN CURRENT 250mA Cougar Power Map
Ipeak=6.97A, Imax=4.88A
DESIGN CURRENT 522mA
+3VALWP +-5%
** The SW just is reserved.
The power passes by jump or
UP6182CQAG 0-ohm resistor. WOL_EN#
D ** P-CHANNEL +3V_LAN D
AO3413 DESIGN CURRENT 300mA
Ipeak=3.98A, Imax=2.8A +5VALWP +-5%
DESIGN CURRENT 3010mA
SUSP
N-CHANNEL +5VS
DESIGN CURRENT 2286mA
SI4800BDY
SUSP
N-CHANNEL DESIGN CURRENT 5586mA
+3VS
C C
SI4800BDY ENVDD
P-CHANNEL +LCD_VDD
AO3413 DESIGN CURRENT 2000mA
SUSP#
DESIGN CURRENT 2640mA
+0.89VSP
SY8033BDBC
SUSP#
SY8033BDBC Ipeak=1.308A, Imax=4A +1.05VSP +-5%
DESIGN CURRENT 3489mA
VR_ON
B Imax=3.5A DESIGN CURRENT 6000mA +CPU_CORE B
ADP3211AMNR2G
SYSON
Ipeak=19.6A, Imax=13.72A +1.5VP +-5%
DESIGN CURRENT 2000mA
G5603RU1U
SUSP#
DESIGN CURRENT 2112mA +1.5VSP
IRF8113PBF
SUSP
DESIGN CURRENT 500mA
+0.75VSP
UP7711U8
A A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/06/27 Deciphered Date 2011/6/27 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC MB A6851
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401986 D
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, September 02, 2011 Sheet 5 of 36
5 4 3 2 1
5 4 3 2 1
<10> DDR_A_DQS#[0..7]
PINEVIEW_M
N455@ N475@
U1 U1 <10> DDR_A_D[0..63]
U80610006237AA SLBX9 A0 1.66G AU80610006240AA SLBX5 U1B
REV = 1.1
<10> DDR_A_DM[0..7]
PINEVIEW_M DDR_A_MA0 AH19 AD3 DDR_A_DQS0
U1A <10> DDR_A_DQS[0..7] DDR_A_MA1 DDR_A_MA_0 DDR_A_DQS_0 DDR_A_DQS#0
AJ18 DDR_A_MA_1 DDR_A_DQS#_0 AD2
DDR_A_MA2 AK18 AD4 DDR_A_DM0
<10> DDR_A_MA[0..14] DDR_A_MA3 DDR_A_MA_2 DDR_A_DM_0
REV = 1.1 AK16 DDR_A_MA_3
DMI_RXP0_C F3 G2 DMI_TXP0 <12> DDR_A_MA4 AJ14 AC4 DDR_A_D0
DMI_RXN0_C DMI_RXP_0 DMI_TXP_0 DDR_A_MA5 DDR_A_MA_4 DDR_A_DQ_0 DDR_A_D1
F2 DMI_RXN_0 DMI_TXN_0 G1 DMI_TXN0 <12> AH14 DDR_A_MA_5 DDR_A_DQ_1 AC1
DMI_RXP1_C H4 H3 DMI_TXP1 <12> DDR_A_MA6 AK14 AF4 DDR_A_D2
DMI_RXN1_C DMI_RXP_1 DMI_TXP_1 DDR_A_MA7 DDR_A_MA_6 DDR_A_DQ_2 DDR_A_D3
G3 DMI_RXN_1 DMI_TXN_1 J2 DMI_TXN1 <12> AJ12 DDR_A_MA_7 DDR_A_DQ_3 AG2
DDR_A_MA8 AH13 AB2 DDR_A_D4
D DMI DDR_A_MA9 DDR_A_MA_8 DDR_A_DQ_4 DDR_A_D5 D
AK12 DDR_A_MA_9 DDR_A_DQ_5 AB3
DDR_A_MA10 AK20 AE2 DDR_A_D6
DDR_A_MA11 DDR_A_MA_10 DDR_A_DQ_6 DDR_A_D7
AH12 DDR_A_MA_11 DDR_A_DQ_7 AE3
DDR_A_MA12 AJ11
DDR_A_MA13 DDR_A_MA_12 DDR_A_DQS1
<9> CLK_CPU_EXP# N7 EXP_CLKINN EXP_RCOMPO L10 AJ24 DDR_A_MA_13 DDR_A_DQS_1 AB8
<9> CLK_CPU_EXP N6 L9 DMI_IRCOMP R492 DDR_A_MA14 AJ10 AD7 DDR_A_DQS#1
EXP_CLKINP EXP_ICOMPI R493 49.9_0402_1% DDR_A_MA_14 DDR_A_DQS#_1 DDR_A_DM1
EXP_RBIAS L8 DDR_A_DM_1 AA9
R10 750_0402_1%
EXP_TCLKINN DDR_A_WE# DDR_A_D8
R9 EXP_TCLKINP RSVD_TP N11 T1 <10> DDR_A_WE# AK22 DDR_A_WE# DDR_A_DQ_8 AB6
N10 P11 Pull-down must be placed DDR_A_CAS# AJ22 AB7 DDR_A_D9
RSVD RSVD_TP T2 <10> DDR_A_CAS# DDR_A_CAS# DDR_A_DQ_9
N9 DDR_A_RAS# AK21 AE5 DDR_A_D10
RSVD within 500 mils from Pineview-M <10> DDR_A_RAS# DDR_A_RAS# DDR_A_DQ_10
AG5 DDR_A_D11
DDR_A_BS0 DDR_A_DQ_11 DDR_A_D12
<10> DDR_A_BS0 AJ20 DDR_A_BS_0 DDR_A_DQ_12 AA5
DDR_A_BS1 AH20 AB5 DDR_A_D13
<10> DDR_A_BS1 DDR_A_BS_1 DDR_A_DQ_13
K2 K3 DDR_A_BS2 AK11 AB9 DDR_A_D14
RSVD RSVD <10> DDR_A_BS2 DDR_A_BS_2 DDR_A_DQ_14
J1 L2 AD6 DDR_A_D15
RSVD RSVD DDR_A_DQ_15
M4 RSVD RSVD M2
L3 N2 AD8 DDR_A_DQS2
RSVD RSVD DDR_CS0# DDR_A_DQS_2 DDR_A_DQS#2
<10> DDR_CS0# AH22 DDR_A_CS#_0 DDR_A_DQS#_2 AD10
DDR_CS1# AK25 AE8 DDR_A_DM2
1 OF 6 <10> DDR_CS1# DDR_A_CS#_1 DDR_A_DM_2
AJ21
PINEVIEW-M_FCBGA8559 AJ25
DDR_A_CS#_2
AG8 DDR_A_D16
DDR_A_CS#_3 DDR_A_DQ_16 DDR_A_D17
DDR_A_DQ_17 AG7
N550@ DDR_CKE0 AH10 AF10 DDR_A_D18
<10> DDR_CKE0 DDR_A_CKE_0 DDR_A_DQ_18
DDR_CKE1 AH9 AG11 DDR_A_D19
<10> DDR_CKE1 DDR_A_CKE_1 DDR_A_DQ_19
SMPWROK AK10 AF7 DDR_A_D20
DDR_A_CKE_2 DDR_A_DQ_20
0.1U_0402_16V4Z
AJ8 AF8 DDR_A_D21
DDR_A_CKE_3 DDR_A_DQ_21 DDR_A_D22
DDR_A_DQ_22 AD11
10K_0402_5%
M_ODT0 AK24 AE10 DDR_A_D23
<10> M_ODT0 DDR_A_ODT_0 DDR_A_DQ_23
<12> DMI_RXP0 C948
1 2 DMI_RXP0_C M_ODT1 AH26
<10> M_ODT1 DDR_A_ODT_1
2
0.1U_0402_10V6K 1 AH24 AK5 DDR_A_DQS3
DDR_A_ODT_2 DDR_A_DQS_3
1
D DDR_A_DQS#3
AK27 DDR_A_ODT_3 DDR_A_DQS#_3 AK3
C C949 DMI_RXN0_C SYSON# Q37