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5 4 3 2 1
8S661FXMTIU-IU Schematics Revision : 1.0
SHEET TITLE SHEET TITLE
D D
1 COVER SHEET 32 RTL8100C 10/100 LAN
2 BOM & PCB MODIFY HISTORY 33 VGA CONNECTOR
3 BLOCK DIAGRAM
4,5,6 INTEL CPU_WMT_478
7-10 SIS661FX (NORTH BRIDGE) HOST; DDR; AGP,HYPER ZIP
11-14 SIS964L (SOUTH BIRDGE)
15 CLOCK GENERATOR (ICS952018AF), BUFFER(ICS93722)
C C
16,17 DDR SDRAM DIMMS 1,2
18 AGP SLOT
19 PCI SLOT 1,2,3
20 IDE,FRONT USB,PCIRST#
21 LPCIO_IT8705
22 BIOS
23 COM,PRT,FDD,KB/MS,IR
B B
24 AC 97 ALC655
25 AUDIO JACK,SPDIF
26 FAN, IR
27 PANEL,STR LED,FANS ,CPU GN
28 VCORE PWM FAN5019 + FAN5009
29 VDDQ,VCC18,VTT_GMCH DC POWER PCB Size: 244*230 mm
COMPONENT SIDE
(1 oz. Copper)
30 ATX CONN, GPIO LIST VCC LAYER
(1 oz. Copper)
GND LAYER
A (1 oz. Copper) A
31 DDR POWER SOLDER SIDE
(1 oz. Copper)
GIGABYTE
Title
COVER SHEET
Size Document Number Rev
Custom 1.0
8S661FXMTIU-IU
Date: Thursday, June 16, 2005 Sheet 1 of 33
5 4 3 2 1
5 4 3 2 1
Model Name: 8S661FXMTIU-IU Circuit or PCB layout change
for next version
Version: 1.0 Date Change Item Reason
D D
Component value change history
Date Change Item Reason
2005/05/04
0.1 First Release
2005/06/15
1.0 PVT BOM
C C
B B
A A
GIGABYTE
Title
BOM & PCB MODIFY HISTORY
Size Document Number Rev
Custom 1.0
8S661FXMTIU-IU
Date: Thursday, June 16, 2005 Sheet 2 of 33
5 4 3 2 1
5 4 3 2 1
VCORE
+
+
+
SEC1 SEC2 SEC3
100U/2V/SPCAP/X 100U/2V/SPCAP/X
D VCORE 100U/2V/SPCAP/X D
BC663 BC664 BC665 BC666
10U/12/X/6.3V/X 10U/12/X/6.3V/X 10U/12/X/6.3V/X 10U/12/X/6.3V
LGA775A
HA[3..16]
7 HA[3..16]
HA3 L5 D2 -ADS
A03# ADS# -ADS 7
HA4 P6 C2 -BNR
A04# BNR# -BNR 7
HA5 M5 D4 -HIT
A05# HIT# -HIT 7
HA6 L4 H4
HA7 A06# RSP# -BPRI
M4 A07# BPRI# G8 -BPRI 7
HA8 R4 B2 -DBSY
A08# DBSY# -DBSY 7
HA9 T5 C1 -DRDY
A09# DRDY# -DRDY 7
HA10 U6 E4 -HITM
A10# HITM# -HITM 7
HA11 T4 AB2 -IERR
HA12 A11# IERR# -CPUINIT
U5 A12# INIT# P3 -CPUINIT 5,12
HA13 U4 C3 -HLOCK
A13# LOCK# -HLOCK 7
HA14 V5 E3 -HTRDY C1086
A14# TRDY# -HTRDY 7
HA15 V4 AD3 33P/4/N/50V
HA16 A15# BINIT# -DEFER
W5 A16# DEFER# G7 -DEFER 7 Closed to
C N4 F2 -EDRDY C
P5
RSVD EDRDY#
AB3 Pin-H1
-HREQ0 RSVD MCERR# R1537
7 -HREQ0 K4 REQ0#
-HREQ1 J5 U2 CPU_TP1 100/6/1 GTLREF
7 -HREQ1 REQ1# AP0# VTT_OR
-HREQ2 M6 U3 CPU_TP2
7 -HREQ2 REQ2# AP1#
-HREQ3 K6
7 -HREQ3 REQ3#
-HREQ4 J6 F3 -BREQ0 BC667 R1538 C1087
7 -HREQ4 REQ4# BR0# -BREQ0 7
-HA_STB0 R6 G3 TESTHI8 0.01U/6/X/50V 169/6/1 1U/6/Y/10V
7 -HA_STB0 ADSTB0# TESTHI08 TESTHI8 5
-HPCREQ G5 G4 TESTHI9
HA[17..31] PCREQ# TESTHI09 TESTHI9 5
H5 TESTHI10
7 HA[17..31] TESTHI10 TESTHI10 5
HA17 AB6
HA18 A17#
W6 A18# DP0# J16 CPU_TP3
HA19 C1088
Y6 A19# DP1# H15 CPU_TP4
HA20 Y4 H16 CPU_TP5 220P/4/N/50V
HA21 A20# DP2#
AA4 A21# DP3# J17 CPU_TP6
HA22 AD6 A22#
SP-CAP X 4PCS HA23
HA24
AA5
AB5
A23# GTLREF H1 GTLREF
HA25 A24# -CPURST R1539 62/6 -IERR
AC5 A25# RESET# G23 -CPURST 7 VTT_OL
HA26 AB4
VCORE HA27 A26# -RS0
AF5 A27# RS0# B3 -RS0 7
HA28 AF4 F5 -RS1 C1089 R1540 62/6 -BREQ0
A28# RS1# -RS1 7 VTT_OL
HA29 AG6 A3 -RS2 22P/4/N/50V
A29# RS2# -RS2 7
HA30 AG4
HA31 A30# R1541 62/6 -CPURST
AG5 VTT_OL
+
+
+
+
EC98 EC99 EC100 EC101 A31#
AH4 A32#
AH5 A33#
AJ5 R1542 62/6/X -EDRDY
A34# VTT_OL
AJ6 A35#
AC4 R1652 62/6/X
100U/2V/SPCAP/X 100U/2V/SPCAP/X 100U/2V/SPCAP/X RSVD
AE4 RSVD
B -HA_STB1 B
7 -HA_STB1 AD5 ADSTB1#
100U/2V/SPCAP/X
R1543 62/6/X -HPCREQ
VTT_OL
LGA775
VCORE
BC668 BC669 BC670 BC671 BC672
10U/12/X/6.3V/X 10U/12/X/6.3V/X 10U/12/X/6.3V/X 10U/12/X/6.3V/X 10U/12/X/6.3V/X
VCORE
BC673 BC674 BC675
10U/12/X/6.3V 10U/12/X/6.3V 10U/12/X/6.3V
A A
GIGABYTE
Title
P4_LGA775-A
Size Document Number Rev
Custom 8S661FXMTIU-IU 1.0
Date: Thursday, June 16, 2005 Sheet 3 of 33
5 4 3 2 1
5 4 3 2 1
D D
LGA775B
HD[0..15]
7 HD[0..15] HD[32..47] 7
HD0 B4 G16 HD32
HD1 D00# D32# HD33
C5 D01# D33# E15
HD2 A4 E16 HD34
HD3 D02# D34# HD35
C6 D03# D35# G18
HD4 A5 G17 HD36
HD5 D04# D36# HD37
B6 D05# D37# F17
HD6 B7 F18 HD38
HD7 D06# D38# HD39
A7 D07# D39# E18
HD8 A10 E19 HD40
HD9 D08# D40# HD41
A11 D09# D41# F20
C HD10 B10 E21 HD42 C
HD11 D10# D42# HD43
C11 D11# D43# F21
HD12 D8 G21 HD44
HD13 D12# D44# HD45
B12 D13# D45# E22
HD14 C12 D22 HD46
HD15 D14# D46# HD47
D11 D15# D47# G22
-DBI0 A8 D19 -DBI2
7 -DBI0 DBI0# DBI2# -DBI2 7
-HD_STBN0 C8 G20 -HD_STBN2
7 -HD_STBN0 DSTBN0# DSTBN2# -HD_STBN2 7
-HD_STBP0 B9 G19 -HD_STBP2
7 -HD_STBP0
HD[16..31] DSTBP0 DSTBP2 -HD_STBP2 7
7 HD[16..31] HD[48..63] 7
HD16 G9 D20 HD48
HD17 D16# D48# HD49
F8 D17# D49# D17
HD18 F9 A14 HD50
HD19 D18# D50# HD51
E9 D19# D51# C15
HD20 D7 C14 HD52
HD21 D20# D52# HD53
E10 D21# D53# B15
HD22 D10 C18 HD54
HD23 D22# D54# HD55
F11 D23# D55# B16
HD24 F12 A17 HD56
HD25 D24# D56# HD57
D13 D25# D57# B18
HD26 E13 C21 HD58
HD27 D26# D58# HD59
G13 D27# D59# B21
HD28 F14 B19 HD60
HD29 D28# D60# HD61
G14 D29# D61# A19
HD30 F15 A22 HD62
HD31 D30# D62# HD63
G15 D31# D63# B22
-DBI1 G11 C20 -DBI3
7 -DBI1 DBI1# DBI3# -DBI3 7
-HD_STBN1 G12 A16 -HD_STBN3
7 -HD_STBN1 DSTBN1# DSTBN3# -HD_STBN3 7
-HD_STBP1 E12 C17 -HD_STBP3
7 -HD_STBP1 DSTBP1 DSTBP3 -HD_STBP3 7
B B
LGA775
A A
GIGABYTE
Title
P4_LGA775-C
Size Document Number Rev
Custom 1.0
8S661FXMTIU-IU
Date: Thursday, June 16, 2005 Sheet 4 of 33
5 4 3 2 1
5 4 3 2 1
Place outside of CPU socket
R1545 100/6/1 COMP2
VTT_OL
R1547 100/6/1 COMP3
Note: C1091 R1548 60.4/6/1 COMP0
VCCA & VCOREPLL R1544 110/6/1 TESTHI0 0.1U/6/Y/25V R1549 60.4/6/1 COMP1
VCC3
R1659 49.9/6/1/X GTLREF1
define doesn't same as VTT_OR
R1546 C1090
VTT_GMCH old P4 design kit 61.9/6/1 0.1U/6/Y/25V
L20 R1660 C1135 R1661 60.4/6/1/X COMP2
VCCA 100/6/1/X 1U/6/Y/10V/X R1662 60.4/6/1/X COMP3
10UH/8/100mA/S
D C1092 BC676 R1550 R1551 249/6/1 D
VCC3
3
1U/6/Y/10V 4.7U/8/Y/10V 0/SHT/X RN192
Q148 470/8P4R
VSSA D FS_A
Trace width doesn't 2N7002/SOT23 VTT_GMCH 7 8
5 6 FS_C
less than 12 Mil G S
3 4 FS_B
C1093 BC677 SOT23 TESTHI0 1 2
2
1
L21 1U/6/Y/10V 4.7U/8/Y/10V 6,7 GTL_DET
VCOREPLL R31 62/6
-CPUINIT 3,12
10UH/8/100mA/S LGA775C
As close as possible to R1552 62/6 TESTHI2_7
CPU socket -SMI P2 F26 TESTHI0 R1553 62/6/X -THERMTRIP
12 -SMI SMI# TESTHI00
-A20M K3 W3 TESTHI1
12 -A20M A20M# TESTHI01
-FERR R3 P1 TESTHI11 R1670 62/6/X -FERR
12 -FERR FERR#/PBE# TESTHI11
INTR K1 W2 TESTHI12
12 INTR LINT0 TESTHI12
NMI L1 F25 R1555 62/6/X RSVD_G6
12 NMI LINT1 TESTHI02 VTT_OL
-IGNNE N2 G25
12 -IGNNE IGNNE# TESTHI03
-STPCLK M3 G27 R1556 62/6 TESTHI12
12 -STPCLK STPCLK# TESTHI04
TESTHI05 G26
VCCA A23 G24 R1557 62/6 TESTHI1
VSSA VCCA TESTHII06 TESTHI2_7
B23 VSSA TESTHI07 F24
D23 AK6 -FORCEPR
RSVD FORCEPR# -FORCEPR 26
VCOREPLL C23 G6 RSVD_G6
VCCIOPLL RSVD RN193 7 TESTHI11
8
VTT_GMCH VID0 AM2 L2 -CPUSLP 5 6 TESTHI10
VID[0..5] VID0 SLP# -CPUSLP 12 TESTHI10 3
VID1 AL5 AH2 3 4 TESTHI9
28 VID[0..5] VID1 RSVD TESTHI9 3
RN11 2 62/8P4R INTR VID2 AM3 N1 CPUPWOK_CPU 1 2 TESTHI8
VID2 PWRGOOD TESTHI8 3
3 4 -IGNNE VID3 AL6 AL2 -PROCHOT 62/8P4R
VID3 PROCHOT# -PROCHOT 12,26
5 6 -SMI VID4 AK4 M2 -THERMTRIP
VID4 THERMTRIP# -THERMTRIP 12
7 8 NMI VID5 AL4
C VID5 COMP0 C
1 2 AM5 RSVD COMP0 A13
3 4 -A20M T1 COMP1
-STPCLK CPU_CLK COMP1 COMP2
5 6 15 CPU_CLK F28 BCLK0 COMP2 G2
7 8 -CPUSLP -CPU_CLK G28 R1 COMP3
15 -CPU_CLK BCLK1 COMP3 VTT_OL
RN2 62/8P4R
AE8 N5 VTT_OL VTT_OL
SKTOCC# RSVD
RSVD AE6
21 TMPIN2