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AMD~
AMD-KSTM
PROCESSOR
Software
Development
Guide
Publication # 20007 Rev: D AmendmenVO
Issue D September 1996
ate:
This document contains information on a product under development at Advanced Micro
Devices (AMD). The information is intended to help you evaluate this product. AMD reo
serves the right to change or discontinue work on this proposed product without notice.
e> 1996 Advanced Micro Devices, Inc. All rights reserved.
Advanced Micro Devices reserves the right to make changes in its products
without notice in order to improve design or performance characteristics.
This publication neither states nor implies any representations or warranties
of any kind, including but not limited to any implied warranty of merchant-
ability or fitness for a particular purpose.
AMD makes no representations or warranties with respect to the accuracy or
completeness of the contents of this publication or the information contained
herein, and reserves the right to make changes at any time, without notice.
AMD disclaims responsibility for any consequences resulting from the use of
the information included herein.
Trademarks
AMD, the AMD logo, and combinations thereof are trademarks of Advanced Micro Devices, Inc.
Am486 is a registered trademark, and AMD-K5 is a trademark of Advanced Micro Devices, Inc.
Other product names used in this publication are for identification purposes only and may be trademarks of their
respective companies.
AMD~
20007D/O-Sep1996 AMD-K5 Processor Software Development Guide
Contents
AMD-KSTM Processor x86 Architedure Extensions
Additions to the EFLAGS Register. . . . . . . . . . . . . . . . . . . . . . . . . . .. 2
Control Register 4 (CR4) Extensions .......................... 2
Machine-Check Exceptions .................................. 4
4-Mbyte Pages ............................................. 4
Global Pages .............................................. 8
Virtual-8086 Mode Extensions (VME) ........................ 12
Protected Virtual Interrupt (PVI) Extensions .................. 24
Model-Specific Registers (MSRs) ............................ 25
Machine-Check Address Register (MCAR) ................... : 25
Machine-Check Type Register (MCTR) ....................... 26
Time Stamp Counter (TSC) ................................. 27
Array Access Register (AAR) ............................... 27
Hardware Configuration Register (HWCR) .................... 28
New Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
CPUID .................................................. 29
CMPXCHG8B ............................................. 31
MOV to and from CR4 ..................................... 32
RDTSC .................................................. 33
RDMSR and WRMSR ...................................... 34
RSM .................................................... 36
Illegal Instruction (Reserved Opcode) ........................ 37
Code Optimization for the AMD-K5 Processor
Code Optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
General Superscalar Techniques ............................. 39
Techniques Specific to the AMD-K5 Processor ................. 41
Dispatch and Execution Timing ... . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Notation ................................................. 43
Integer Instructions ....................................... 46
Integer Dot Product Example ............................... 55
Floating-Point Instructions ................................. 57
Contents iii
AMD~
AMD-K5 Processor Software Development Guide 20007D/O-Sep 1996
AMD-KS Processor Initialization
General Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 65
Segment Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
EIP and EFLAGS .......................................... 66
Control and Debug Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Model-Specific Registers ................................... 67
Caches and TLB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Floating-Point Unit ........................................ 67
AMD-KS Processor Test and Debug
Hardware Configuration Register (HWCR) . . . . . . . . . . . . . . . . . . . . 71
Built-In Self-Test (BIST) .................................... 73
Normal BIST ............................................. 73
Test Access Port (TAP) BIST ................................ 74
Output-Float Test ......................................... 75
Cache and TLB Testing ..................................... 75
Array Access Register (AAR) ............................... 76
Array Pointer ............................................. 77
Array Test Data ........................................... 78
Debug Registers .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Standard Debug Functions .................................. 84
110 Breakpoint Extension ................................... 84
Debug Compatibility with Pentium Processor .................. 85
Branch Tracing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Functional-Redundancy Checking ........................... 86
Boundary Scan Architecture Support ......................... 87
Boundary Scan Test Functional Description ................... 88
Boundary Scan Architecture ................................ 89
Registers ................................................ 90
JTAG Register Organization ................................ 91
Public Instructions ........................................ 92
Hardware Debug Tool (HDT) ............................... 112
iv Contents
AMD~
20007DjO-$ep1996 AMD-K5 Processor Software Development Guide
Appendix A Cache
Array Pointer Formats .................................... A-l
AMD-K5 Model 0 Array Data Formats ....................... A-3
AMD-K5 Modell Array Data Formats ....................... A-5
Contents v
AMDl1
20007D/O-Sep1996 AMD-K5 Processor Software Development Guide
List of Tables
Table l-lA. Control Register 4 (CR4) Fields .................... 3
Table 1-2A. Page-Directory Entry (PDE) Fields ................. 8
Table 1-3A. Page-Table Entry (PTE) Fields ................... 11
Table 1-4A. Virtual-Interrupt Additions to EFLAGS Register .... 15
Table 1-5A. Instructions that Modify the IF or
VIF Flags-Real Mode .......................... 16
Table 1-5B. Instructions that Modify the IF or
VIP Flags-Protected Mode ...................... 17
Table 1-5C. Instructions that Modify the IF or
VIF Flags-Virtual-8086 Mode . . . . . . . . . . . . . . . . . . . 18
Table 1-5D. Instructions that Modify the IF or
VIF Flags-Virtual-8086 Mode
Interrupt Extensions (VME) ...................... 19
Table 1-5E. Instructions that Modify the IF or
VIF Flags-Protected Mode Virtual
Interrupt Extensions (PVI). . . . . . . . . . . . . . . . . . . . . . . 20
Table 1-6A. Interrupt Behavior and Interrupt-Table Access ...... 23
Table 1-7A. Machine-Check Type Register (MCTR) Fields ....... 27
Table 1-8A. CPU Clock Frequencies, Bus Frequencies,
and P-Rating Strings ............................ 29
Table 2-1. Integer Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 2-2. Integer Dot Product Internal Operations Timing .... 56
Table 2-3. Floating-Point Instructions ....................... 57
Table 3-1. Segment Register Attribute Fields Initial Values. . . . 66
Table 4-l. Hardware Configuration Register (HWCR) Fields ... 72
Table 4-2. BIST Error Bit Definition in EAX Register ......... 74
Table 4-3. Array IDs in Array Pointers ...................... 77
Table 4-4. Branch-Trace Message Special Bus Cycle Fields ..... 86
Table 4-5. Test Access Port (TAP) ID Code .................. 92
Table 4-6. Public TAP Instructions ......................... 93
Table 4-7. Control Bit Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Table 4-8. Boundary Scan Register Bit Definitions (Model 0) ... 96
Table 4-9. Boundary Scan Register Bit Definitions (Modell) .. 104
Table A-l. Cache Array Pointer Formats ................... A-2
Table A-2. Cache Array Identification Values ............... A-2
Table A-3. AMD-K5 Model 0 ICACHE Physical Tags .......... A-3
Table A-4. AMD-K5 Model 0 DCACHE Physical Tags ......... A-3
List of Tables vii
AMD~
AMD-K5 Processor Software Development Guide 20007D/O-Sep 1996
Table A-5. AMD-K5 Model 0 DCACHE Data ................. A-3
Table A-6. AMD-K5 Model 0 DCACHE Linear Tag ........... A-3
Table A-7. AMD-K5 Model 0 ICACHE Instructions ........... A-4
Table A-B. AMD-K5 Model 0 ICACHE Linear Tag ............ A-4
Table A-9. AMD-K5 Model 0 ICACHE Valid Bits ............. A-4
Table A-lO. AMD-K5 Model 0 ICACHE Branch Prediction ...... A-4
Table A-ll. AMD-K5 Model 0 TLB 4-Kbyte Linear Tag ......... A-4
Table A-l2. AMD-K5 Model 0 TLB 4-Kbyte Physical Page Frame A-5
Table A-l3. AMD-K5 Model 0 TLB 4-Mbyte Virtual Tag ........ A-5
Table A-l4. AMD-K5 Model 0 TLB 4-Mbyte Physical Page Frame A-5
Table A-l5. AMD-K5 Modell ICACHE Physical Tags .......... A-5
Table A-l6. AMD-K5 Modell DCACHE Physical Tags ......... A-5
Table A-l7. AMD-K5 Modell DCACHE Data ................. A-5
Table A-lB. AMD-K5 Modell DCACHE Linear Tag ........... A-6
Table A-l9.AMD-K5 Modell ICACHE Instructions ........... A-6
Table A-20. AMD-K5 Modell ICACHE Linear Tag ............ A-6
Table A-21. AMD-K5 Modell ICACHE Valid Bits ............. A-6
Table A-22. AMD-K5 Modell ICACHE Branch Prediction ...... A-6
Table A-23. AMD-K5 Modell TLB 4-Kbyte Linear Tag ......... A-7
Table A-24. AMD-K5 Modell TLB 4-Kbyte Physical Page Frame A-7
Table A-25. AMD-K5 Modell TLB 4-Mbyte Virtual Tag ........ A-7
Table A-26. AMD-K5 Model 1 TLB 4-Mbyte Physical Page Frame A-7
viii List of Tables
AMD~
20007D/O-Sep1996 AMD-K5 Processor Software Development Guide
List of Figures
Figure 1-1. Control Register 4 (CR4) ......................... 2
Figure 1-2. 4-Kbyte Paging Mechanism ....................... 5
Figure 1-3. 4-Mbyte Paging Mechanism ....................... 6
Figure 1-4. Page-Directory Entry (PDE) ....................... 7
Figure 1-5. Page-Table Entry (PTE) ......................... 10
Figure 1-6. EFLAGS Register .............................. 15
Figure 1-7. Task State Segment (TSS) ....................... 22
Figure 1-8. Machine-Check Address Register (MCAR) ......... 25
Figure 1-9. Machine-Check Type Register (MCTR) ............ 26
Figure 4-1. Hardware Configuration Register (HWCR) ......... 71
Figure 4-2. Array Access Register (AAR). . . . . . . . . . . . . . . . . . . . . 76
Figure 4-3. Test Formats: Data-Cache Tags. . . . . . . . . . . . . . . . . .. 78
Figure 4-4. Test Formats: Data-Cache Data ................... 79
Figure 4-5. Test Formats: Instruction-Cache Tags .............. 80
Figure 4-6. Test Formats: Instruction-Cache Instructions ....... 81
Figure 4-7. Test Formats: 4-Kbyte TLB ....................... 82
Figure 4-8. Test Formats: 4-Mbyte TLB ...................... 83
List of Figures ix
AMD~
20007D/O-Sep1996 AMD-K5 Processor Software Development Guide
1
AMD-KSTM Processor
x86 Architecture Extensions
The AMD-K5TM processor is compatible with the instruction
set, programming model, memory management mechanisms,
and other software infrastructure supported by the 486 and
Pentium (735\90, 815\100) processors. Operating system and
application software that runs on the Pentium processor can be
executed on the AMD-K5 processor without modification.
Because the Al\ID-K5 processor takes a significantly different
approach to implementing the x86 architecture, some subtle
differences from the Pentium processor may be visible to sys-
tem and code developers. These differences are described in
Appendix A of the AMD-K5 Processor Technical Reference Man-
ual, order# 18524.
Call AMD at 1-800-222-9232 to order AMD-K5 processor sup-
port documents.
Before implementing the AMD-K5 processor model-specific
features, check CPUID for supported feature flags. See
"CPUID" on page 29 for more information.
AMD-KSTM Processor x86 Architecture Extensions ,
AMD~
AMD-K5 Processor Software Development Guide 20007D/O-$ep1996
Additions to the EFLAGS Register
The EFLAGS register on the Al\ID-K5 proce'ssor defines new
bits in the upper 16 bits of the register to support extensions to
the operating modes. See "Virtual-8086 Mode Extensions
(VME)" on page 12 and "CPUID" on page 29 for additional
information.
Control Register 4 (CR4) Extensions
Control Register 4 (CR4) was added on the Al\ID-K5 processor.
The bits in this register control the various architectural exten-
sions. The majority of the bits are reserved. The default state
of CR4 is all zeros. Figure 1-1 shows the register and describes
the bits. The architectural extensions are described in Table
1-1.
31 B 7 6 543 2 1 0
Ii I-+- Reserved
Global Page Extension
Machine Check Enable
Page Size Extension
Debugging Extensions
Time Stamp Disable
GPE
MCE
PSE
DE
TSD
PVI
7
6
4
2
-----'1111
Protected Virtual Interrupts
Virtual-BOB6 Mode Extensions VME
Figure 1-1. Control Register 4 (CR4)
2 AMD-KSTM Processor x86 Architecture Extensions
AMD~
20007D/0-Sep 1996 AMD-K5 Processor Software Development Guide
Table l-lA. Control Register 4 (CR4) Fields
Bit Mnemonic Description Function
Enables retention of designated entries in the 4-Kbyte TlB or
Global Page 4-Mbyte TlB during invalidations.
7 GPE
Extension 1 =enabled, 0 =disabled.
See "Global Pages" on page Bfor details.
Enables machine-check exceptions.
6 MCE Machine-Check Enable 1 =enabled, 0 =disabled.
See "Machine-Check Exceptions" on page 4 for details.
Enables 4-Mbyte pages.
Page Size
4 PSE 1 =enabled, 0 =disabled.
Extension
See "4-Mbyte Pages" on page 4 for details.
Enables I/O breakpoints in the DR7-DRO registers.
Debugging
3 DE 1 =enabled, 0 =disabled.
Extensions
See "Debug Registers" on page 84 for details.
Selects privileged (CPl=O) or non-privileged (CPl>O) use of
the RDTSC instruction, which reads the Time Stamp Counter
2 TSD
Time Stamp (Tsq.
Disable
1 =CPl must be 0, 0 =any CPl.
See "Time Stamp Counter (Tsq" on page 27 for details.
Enables hardware support for interrupt virtualization in Pro-
tected mode.
Protected Virtual
1 PVI 1 =enabled, 0 =disabled.
Interrupts
See "Protected Virtual Interrupt (PVI) Extensions" on page 24
for details.
Enables hardware support for interrupt virtualization in Vir-
tual-BOB6 mode.
Virtual-BOB6
0 VME 1 =enabled, 0 =disabled.
Mode Extensions
See ''Virtual-BOB6 Mode Extensions (VME)" on page 12 for
details.
Control Register 4 (CR4) Extensions
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AMD-K5 Processor Software Development Guide 20007D/0-Sep 1996
Machine-Check Exceptions
Bit 6 in CR4, the machine-check enable (MCE) bit, controls
generation of machine-check exceptions (12h). If enabled by
the MCE bit, these exceptions are generated when either of
the following occurs: