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5 4 3 2 1
ZB1 SYSTEM BLOCK DIAGRAM
PCI-Express X 2
Yonah/Merom 479 Docking
DVI / 7307 CPU Connector TV out / CRT
X'TAL uFCPGA U44 Thermal Sensor Switch
Chrontel P41 14.318MHZ P3,P4 U64 P5 with PCIE1~2 , Lan TV in
D ,Ser & Par Port , D
PS2 , VGA, DVI , SPDIF
Clock Generator FSB DVI
TVOUT SM BUS
MAX4892
ICS954310BGLF P2
P25 Audio
DDR II 2N7002
Dual Channel DDR2 P42 10/100/1G
SVIO SODIMM0 MAX4892
TFT LCD Panel TVout CN36 Switch
CALISTOGA
WXGA LVDS 945GM/PM 533/667 Mhz DDR II
WSXGA+ VGA 1466 SODIMM1
WUXGA P25 FCBGA U43 CN37 P12,P13
SPIF3811 SATA0 PCI-Express 16X Lan
P6,P7,P8,P9,P10,P11 USB7 USB8
U51 P37
LVDS
CRT HOT SWAP X4 DMI interface VGA/TV out ATI
C
P26 BAY M52/54 MiniCard / C
HDD Master WLAN New Card
PATA VRAM X 4 U34
CN41 P35
U30,33,6,10 P23 P18,P19,P20,P21, P29 P33
P22,P24
SATA1
ICH7M PCI-Express
ODD Slave PATA
82801
CN24 P35 652 BGA
U49 PCI Bus interface X'TAL
USB 2.0
25M
X'TAL24.576MHZ
P14,P15,P16,P17
DDR2
Bluetooth X'TAL 16M X 16 Broadcom
USB4 P29 32.768KHZ
32M X 16 5789/87/88
PCMCIA+1394 MINI-PCI /
USB Port x 4 +Cardreader
USB0~3 P29
Int MIC TV Card 4401E 10/100
P29
B
P36 Controller 5705E GLAN B
P27
CCD TI PCI7412
USB7 P29 LPC
X'TAL OSC
Azalia Audio 32.768K 48MHZ P30,P31
EEPROM Transformer
Controller Azalia
Audio Amplifier KBC NS P27 P27
P37 ALC883 P36
PC97541V
P39
RJ45
IEEE 1394 6 in 1 Cardreader PCMCIA Slot
Port Fan Header
P30 Socket P32 P31 P5,P40
MIC Jack Line in
BIOS
P39 TPM Primary Battery
2nd 8/6 Cell
A Connector A
Speaker Phone Jack MDC 1.5 Super I/O FIR
P37 P36 Touch Pad SMSC CIR PROJECT : ZB1
(Dual-Point) SIO1000 Connector
P40 P38 Quanta Computer Inc.
Size Document Number Rev
BLOCK DIAGRAM C
Date: Tuesday, February 07, 2006 Sheet 1 of 50
5 4 3 2 1
A B C D E
4 Close to IC <500mils VDD_A 4
C277 27P-50V_4 CG_XIN
Place these termination to close CK410M.
45
46
2
U15
L38 25 mils Y6 58 60 14M_REF R222 33_4
VDDA
GNDA
X1 REF0 14M_ICH <16>
ACB2012L-120-T_8 14.318MHZ RP58
+3V VDD_SRC_CPU C257 27P-50V_4 CG_XOUT 57 52 RHCLK_CPU 1 2 33_4P2R_S
X2 CPUCLKT0 CLK_CPU_BCLK <3>
RHCLK_CPU# C309
1
CPUCLKC0 51 3 4 CLK_CPU_BCLK# <3>
120 ohms@100Mhz C772 C771 C300 C786 C279 +3V R196 *10K_4 CK-410M RP57 *10P-50V_4
.1U-10V_4 10U-10V_8
<16,43> VR_PWRGD_CK410# 10 49 RHCLK_MCH 1 2 33_4P2R_S
Vtt_PwrGd#/PD CPUCLKT1 CLK_MCH_BCLK <6>
.1U-10V_4 .1U-10V_4 .1U-10V_4 <16> PM_STPCPU# PM_STPCPU# 62 48 RHCLK_MCH# 3 4
CPU_STOP# CPUCLKC1 CLK_MCH_BCLK# <6>
<16> PM_STPPCI# PM_STPPCI# 63 RP56
R234 2.2_6 VDD_A PCI/PCIE_STOP# CLK_PCIE_MINI1_
CPUCLKT2/PCIET8 44 1 2 33_4P2R_S CLK_PCIE_MINI1 <29>
CGCLK_SMB 54 43 CLK_PCIE_MINI1_# 3 4
<13> CGCLK_SMB SCLK CPUCLKC2/PCIEC8 RP55 CLK_PCIE_MINI1# <29>
C298 C314 CGDAT_SMB 55
<13> CGDAT_SMB SDATA
.1U-10V_4 10U-10V_8 R195 33_4 41 1 2 RP62
<16> CLKUSB_48 REQ1#/PCIET7 CLK_PCIE_EZ2 <42>
CLK_BSEL0 R502 4.7K_4 12 40 3 4 CLK_CPU_BCLK 1 249.9_4P2R_S
FSA/USB_48MHz REQ2#/PCIEC7 CLK_PCIE_EZ2# <42>
CLK_BSEL1 16 RP54 CLK_CPU_BCLK# 3 4
CLK_BSEL2 R224 4.7K_4 FSB/TEST_MODE RSRC_MCH
61 REF1/FSLC/TEST_SEL PCIET6 39 1 2 33_4P2R_S CLK_PCIE_3GPLL <8>
RP61
R223 33_4 38 RSRC_MCH# 3 EZ@33_4P2R_S
4 CLK_MCH_BCLK 1 249.9_4P2R_S
<38> SIO_14M PCIEC6 RP53 CLK_PCIE_3GPLL# <8>
VDD_REF 56 CLK_MCH_BCLK# 3 4
VDD_SRC_CPU VDD_REF RP10
50 VDDCPU PCIET5 36 1 2 CLK_PCIE_EZ1 <42>
C310 35 3 4 CLK_PCIE_MINI1 1 249.9_4P2R_S
PCIEC5 CLK_PCIE_EZ1# <42>
*10P-50V_4 VDD_PCI 1 RP46 CLK_PCIE_MINI1# 3 4
VDD_PCI_1 CLK_PCIE_NEW
7 VDD_PCI_2 PCIET4 30 3 4 EX@33_4P2R_S CLK_PCIE_NEW_C <33>
RP120
25 mils 31 CLK_PCIE_NEW# 1 EZ@33_4P2R_S
2 CLK_PCIE_LAN [email protected]_4P2R_S
3 4
PCIEC4 CLK_PCIE_NEW_C# <33>
VDD_SRC_CPU 21 RP47 CLK_PCIE_LAN# 1 2
3 L74 VDD_PCI VDD_PCIE RSRC_SATA 33_4P2R_S RP59 3
+3V 28 VDDPCIE SATA_CKT 26 3 4 CLK_PCIE_SATA <14>
ACB2012L-120-T_8 42 27 RSRC_SATA# 1 2 CLK_PCIE_3GPLL 1 249.9_4P2R_S
VDD_PCIE SATA_CKC CLK_PCIE_SATA# <14>
C768 C767 C760 RP48 CLK_PCIE_3GPLL# 3 4
.1U-10V_4 .1U-10V_4 10U-10V_8 VDD_48 11 24 RSRC_ICH 3 4 33_4P2R_S RP122
VDD_48 PCIET3 CLK_PCIE_ICH <15>
25 RSRC_ICH# 1 2 CLK_PCIE_SATA 3 449.9_4P2R_S
PCIEC3 CLK_PCIE_ICH# <15>
CLKGN_REQ3_PCIE 32 RP49 CLK_PCIE_SATA# 1 2
R191 2.2_6 VDD_48 CLKGN_REQ4_PCIE REQ3(PCIE)
33 REQ4(PCIE) PCIET2 22 3 4 G7_G9@33_4P2R_S CLK_PCIE_LAN <27>
PCIEC2 23 1 2 CLK_PCIE_LAN# <27>
C769 C770 Iref=5mA, R510 475/F_6 IREF 47
.1U-10V_4 10U-10V_8 IREF RP121
Ioh=4*Iref
PCIET1 19
20 CLK_PCIE_ICH
3 449.9_4P2R_S
PCIEC1 RP51 CLK_PCIE_ICH#
RP52 1 2
DREFCLK 1 2 R_DOT96 14 17 R_DREFSSCLK 3 4 IV@33_4P2R_S RP123 [email protected]_4P2R_S
<8> DREFCLK DOT96MHz 27Mfix/LCD_SSCGT/PCIE0T DREFSSCLK <8>
R233 1_6 VDD_REF DREFCLK# 3 4 R_DOT96# 15 18 R_DREFSSCLK# 1 2 CLK_PCIE_NEW_C 3 4
<8> DREFCLK# DOT96MHz# 27SS/LCD_SSCGC/PCIE0C DREFSSCLK# <8>
CLK_PCIE_NEW_C# 1 2
C297 C308 33_4P2R_S R_PCLK_SIO R199 33_4 RP45
selPCIEX0_LCD#/PCI5 5 PCI_CLK_SIO <38>
.1U-10V_4 10U-10V_8 T38 34 4 R_PCLK_7411 R201 33_4 DREFSSCLK 3 4
GND_PCI_1
GND_PCI_2
PWRSAVE# PCI4 PCI_CLK_7412 <30>
GND_SRC
3 R_PCLK_LAN R202 NL_G5@33_4 DREFSSCLK# 1 2
PCI3 PCLK_LAN <27> RP117
GND_48
INTERNAL PULL HIGH 64 PCLK_MINI_LPC R225 33_4
PCICLK2/REQ_SEL PCLK_MINI <29>
9 R_PCLK_ICH R500 33_4 DREFCLK 3 4
GND
GND
GND
PCIF1/selLCD_27# PCLK_ICH <15>
8 R_PCLK_591 R499 33_4 DREFCLK# 1 [email protected]_4P2R_S
2
PCIF0/ITP_EN PCLK_591 <39>
RP60
ICS954310BGLF CLK_PCIE_EZ2 1 [email protected]_4P2R_S
53
13
59
29
37
+3V C757 C236 C234 CLK_PCIE_EZ2# 3 49.9_4P2R_S
2
6
4
R220 *10K_4 RP4
+3V
*10P-50V_4 *10P-50V_4 CLK_PCIE_EZ1 1 [email protected]_4P2R_S
CLKGN_REQ3_PCIE R206 10K_4 R197 10K_4 C756 C302 C235 CLK_PCIE_EZ1# 3 4
<33> NEW_CLKREQ# RP116
CLKGN_REQ4_PCIE R217 10K_4
<42> EZ_CLKREQ#
R198 10K_4 NL_G5@10P-50V_4 CLK_PCIE_M56 1 2
2 *10P-50V_4 *10P-50V_4 *10P-50V_4 CLK_PCIE_M56# 2
3 4
BSEL strappings need to be set for 533MHz Moby Dick (Intel?915GM - Calistoga Interposer)
(if Calistoga is designed for 667MHz board).
EV@: Stuff when external VGA used [email protected]_4P2R_S
IV@: Stuff when internal VGA used
RP118 EV@33_4P2R_S
R_DREFSSCLK 1 2 CLK_PCIE_M56 <18>
R_DREFSSCLK# 3 4 CLK_PCIE_M56# <18>
CLK_BSEL0 R493 1K_4 MCH_BSEL0 <8>
<3> CPU_BSEL0
+3V
CLK_BSEL1 R192 1K_4 MCH_BSEL1 <8> R689 EV@10K_4
<3> CPU_BSEL1
CLK_BSEL2 R235 1K_4 R_PCLK_SIO R200 IV@10K_4
<3> CPU_BSEL2 MCH_BSEL2 <8>
+3V
Q15 R218 R216
2
RHU002N06 10K_4 10K_4 FSC FSB FSA CPU SRC PCI
3 1 CGDAT_SMB 1 0 1 100 100 33
<16,27,29,33,42> PDAT_SMB
1 0 0 1 133 100 33 1
+3V
0 1 1 166 100 33
Q14
0 1 0 200 100 33
PROJECT : ZB1
2
RHU002N06 0 0 0 266 100 33
3 1 CGCLK_SMB 1 0 0 333 100 33
<16,27,29,33,42> PCLK_SMB Quanta Computer Inc.
1 1 0 400 100 33 Size Document Number Rev
1 1 1 200 100 33 CLOCK GENERATOR C
Date: Wednesday, March 01, 2006 Sheet 2 of 50
A B C D E
5 4 3 2 1
T17
U44A
<6> H_A#[31:3] +1.05V
H_A#3 J4 H1
A[3]# ADS# H_ADS# <6>
H_A#4 L4 E2
A[4]# BNR# H_BNR# <6>
H_A#5 M3 G5 +1.05V +1.05V <4,6,9,10,14,17,46>
A[5]# BPRI# H_BPRI# <6>
H_A#6 K5
H_A#7 M1 A[6]#
A[7]# DEFER# H5 H_DEFER# <6>
ADDR GROUP 0
H_A#8 N2 F21
A[8]# DRDY# H_DRDY# <6>
H_A#9 J1 E1 R230 Near to MCH <500mils
A[9]# DBSY# H_DBSY# <6>
H_A#10 N3 56.2/F_4
CONTROL
H_A#11 P5 A[10]#
A[11]# BR0# F1 H_BREQ#0 <6>
D H_A#12 P2 D
H_A#13 L1 A[12]#
A[13]# IERR# D20 <6> H_D#[63:0] H_D#[63:0] <6>
H_A#14 P4 B3
A[14]# INIT# H_INIT# <14>
H_A#15 P1 T98 U44B
H_A#16 R1 A[15]# H_D#0 E22
A[16]# LOCK# H4 H_LOCK# <6> D[0]# D[32]# AA23 H_D#32
L2 H_D#1 F24 AB24 H_D#33
<6> H_ADSTB0# ADSTB[0]# H_CPURST# <6> D[1]# D[33]#
B1 H_D#2 E26 V24 H_D#34
<6> H_REQ#[4:0] RESET# D[2]# D[34]#
H_REQ#0 K3 F3 H_RS#0 H_D#3 H22 V26 H_D#35
REQ[0]# RS[0]# D[3]# D[35]#
DATA GRP 0
H_REQ#1 H_RS#1 H_D#4 F23 W25 H_D#36
DATA GRP 2
H2 REQ[1]# RS[1]# F4