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Compal Confidential 2
QAU20 M/B Schematics Document
Date : 2011/11/08
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4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/08/03 Deciphered Date Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Page
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-8441P
Date: Monday, November 14, 2011 Sheet 1 of 46
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A B C D E
Compal Confidential Memory BUS(DDRIII)
1.5V DDRIII 1066/1333/1600 for CR
1.5V DDRIII 1066/1333 for HR
Channel A (256MX16) X4 chips
2GB/4GB chips
1
Page 11 1
Page 4~10
FDI x8 DMI x4
LVDS USB3.0
Page 26
Page 23
HDMI
Page 20
USB Page 23
SMBus USB
2 2
USB
PCIE2 Page 25
Page 22
SATA
Port 0 Page 24
SATA
USB
HDA
3
USB 3
Page 29
SPI
Page 12
LPC
Page 25
4 4
Page 27
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/08/01 Deciphered Date 2011/10/18 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Block Diagrams
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-8441P
Date: Monday, November 14, 2011 Sheet 2 of 46
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A B C D E
QAZ50 (LA-8101P Ver:0.1)
Voltage Rails 2011/08/19 Modify SIGNAL
Power Plane Description S1 S3 S5 STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
VIN Adapter power supply (19V) N/A N/A N/A
Full ON HIGH HIGH HIGH HIGH ON ON ON ON
BATT+ Battery power supply (7.2V) N/A N/A N/A
B+ AC or battery power rail for power circuit. N/A N/A N/A S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW
1 +CPU_CORE Core voltage for CPU ON OFF OFF 1
S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF
+VCCSA Voltage for CPU SA RALL ON OFF OFF
+VGFX_CORE Core voltage for UMA graphic ON OFF OFF S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF
+0.75VS +0.75VP to +0.75VS switched power rail for DDR terminator ON OFF OFF
S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF
+CHGRTC BATT+ or Vin to +CHGRTC always on power rail for sequence control ON ON ON*
+RTCVCC RTC power ON ON ON
+VCCP +VCCP (1.05V ) power for PCH ON OFF OFF
+1.5V +1.5VP to +1.5V power rail for DDRIII (1.35V OR 1.5V) ON ON OFF
+1.5VS +1.5VS switched power rail ON OFF OFF
+LG_OUT Voltage for LCD Panel Backlight LED Power ON OFF OFF
+1.8VS (+5VALW ) to 1.8V switched power rail to PCH & GPU ON OFF OFF
+3VALW +3VALW always on power rail ON ON ON*
+3VALW_EC +3VALW always to KBC ON ON ON*
+LAN_IO +3VALW to +LAN_IO power rail for LAN ON ON ON*
+3V_PCH +3VALW to +3V_PCH power rail for PCH (Short Jumper) ON ON ON*
EC SM Bus1 address
+3VS +3VALW to +3VS power rail ON OFF OFF
+5VALW +5VALWP to +5VALW power rail ON ON ON* Device Address
+5V_PCH +5VALW to +5V_PCH power rail for PCH (Short resister) ON ON ON* Smart Battery 0001 011X b
+5VS +5VALW to +5VS switched power rail ON OFF OFF
2 EC SM Bus2 address 2
Device Address
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
PCH (Reserve) 1010 0110b
SMBUS Control Table 2011/07/28 Modify
MINI1 MINI2 EC_SMB_CK2 PCH_SMBCLK
BATT (mSATA) (WLan1) CLKOUT DESTINATION
SOURCE EC_SMB_DA2 PCH_SMBDATA
PCI0 PCH_LPBACK
EC_SMB_CK1
EC_SMB_DA1
KB9012 V X X X X
PCI1 PCI_LPC
EC_SMB_CK2
EC_SMB_DA2
KB9012 X X X O V USB Port Table 2011/07/12 Check
PCI2 None
PCH_SMBCLK 2 External
PCH_SMBDATA PCH X V V V O PCI3 None
USB 2.0 USB 1.1 Port USB Port
3
SATA DESTINATION 0 3
PCH_SMLCLK PCH UHCI0
PCH_SMLDATA X X X X X PCI4 None
SATA0 m-SATA,JSSD1
1 USB/B ( External)
2 USB/B ( External)
UHCI1
3
SATA1 None EHCI1
4 Mini Card(WLAN)
UHCI2
5 Camera
SATA2 None 6
UHCI3
DIFFERENTIAL DESTINATION FLEX CLOCKS DESTINATION 7
SATA3 None 8
UHCI4
CLKOUT_PCIE0 10/100/1G LAN CLKOUTFLEX0 None 9 Test Point (RH274,RH310)
SATA4 None 10
EHCI2 UHCI5
CLKOUT_PCIE1 MINI CARD WLAN CLKOUTFLEX1 None 11
SATA5 None 12
UHCI6
CLKOUT_PCIE2 None CLKOUTFLEX2 None 13
CLK CLKOUT_PCIE3 CARD READER CLKOUTFLEX3 None 2011/08/19 Modify USB 3.0 Port
2 External
USB Port
Option @ CONN@ 1
CLKOUT_PCIE4 None
: etoN lobmyS CR UMA X X 2 USB/B ( External)
4
CLKOUT_PCIE5 None dnuorG latigiD snaem : 3 USB/B ( External) 4
4
CLKOUT_PCIE6 None
dnuorG golanA snaem : USB/B ( External)
CLKOUT_PCIE7 None
Security Classification Compal Secret Data Compal Electronics, Inc.
2009/08/01 2011/10/18 Title
CLKOUT_PEG_B None Issued Date Deciphered Date
Notes List
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C LA-8441P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, November 14, 2011 Sheet 3 of 46
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5 4 3 2 1
PEG_ICOMPI and RCOMPO signals should be
shorted and routed
with - max length = 500 mils - typical
+VCCP impedance = 43 mohms
D PEG_ICOMPO signals should be routed with - D
1
max length = 500 mils
RC1
24.9_0402_1% - typical impedance = 14.5 mohms
UCPU1A
2
G3 PEG_COMP
PEG_ICOMPI
PEG_ICOMPO G1
{14} DMI_CRX_PTX_N0 M2 G4
DMI_RX#[0] PEG_RCOMPO
{14} DMI_CRX_PTX_N1 P6 DMI_RX#[1]
{14} DMI_CRX_PTX_N2 P1
DMI_RX#[2]
{14} DMI_CRX_PTX_N3 P10 H22
DMI_RX#[3] PEG_RX#[0]
J21
PEG_RX#[1]
{14} DMI_CRX_PTX_P0 N3 DMI_RX[0] PEG_RX#[2] B22
{14} DMI_CRX_PTX_P1 P7 DMI_RX[1] PEG_RX#[3] D21
DMI
DMI
{14} DMI_CRX_PTX_P2 P3 DMI_RX[2] PEG_RX#[4] A19
{14} DMI_CRX_PTX_P3 P11 DMI_RX[3] PEG_RX#[5] D17
B14
PEG_RX#[6]
{14} DMI_CTX_PRX_N0 K1 D13
DMI_TX#[0] PEG_RX#[7]
{14} DMI_CTX_PRX_N1 M8 DMI_TX#[1] PEG_RX#[8] A11
{14} DMI_CTX_PRX_N2 N4 DMI_TX#[2] PEG_RX#[9] B10
{14} DMI_CTX_PRX_N3 R2 DMI_TX#[3] PEG_RX#[10] G8
PEG_RX#[11] A8
{14} DMI_CTX_PRX_P0 K3 B6
DMI_TX[0] PEG_RX#[12]
{14} DMI_CTX_PRX_P1 M7 DMI_TX[1] PEG_RX#[13] H8
{14} DMI_CTX_PRX_P2 P4 DMI_TX[2] PEG_RX#[14] E5
{14} DMI_CTX_PRX_P3 T3 DMI_TX[3] PEG_RX#[15] K7
K22
PEG_RX[0]
K19
PEG_RX[1]
PEG_RX[2] C21
{14} FDI_CTX_PRX_N0 U7 FDI0_TX#[0] PEG_RX[3] D19
C C
{14} FDI_CTX_PRX_N1 W11 FDI0_TX#[1] PEG_RX[4] C19
{14} FDI_CTX_PRX_N2 W1 FDI0_TX#[2] PEG_RX[5] D16
{14} FDI_CTX_PRX_N3 AA6 C13
FDI0_TX#[3] PEG_RX[6]
{14} FDI_CTX_PRX_N4 W6 FDI1_TX#[0] PEG_RX[7] D12
PCI EXPRESS -- GRAPHICS
{14} FDI_CTX_PRX_N5 V4 FDI1_TX#[1] PEG_RX[8] C11
{14} FDI_CTX_PRX_N6 Y2 FDI1_TX#[2] PEG_RX[9] C9
{14} FDI_CTX_PRX_N7 AC9 FDI1_TX#[3] PEG_RX[10] F8
Intel(R) FDI
Intel(R) FDI
C8
PEG_RX[11]
C5
PEG_RX[12]
{14} FDI_CTX_PRX_P0 U6 FDI0_TX[0] PEG_RX[13] H6
{14} FDI_CTX_PRX_P1 W10 F6
FDI0_TX[1] PEG_RX[14]
{14} FDI_CTX_PRX_P2 W3 K6
FDI0_TX[2] PEG_RX[15]
{14} FDI_CTX_PRX_P3 AA7
FDI0_TX[3]
{14} FDI_CTX_PRX_P4 W7 G22
FDI1_TX[0] PEG_TX#[0]
{14} FDI_CTX_PRX_P5 T4 FDI1_TX[1] PEG_TX#[1] C23
{14} FDI_CTX_PRX_P6 AA3 D23
FDI1_TX[2] PEG_TX#[2]
{14} FDI_CTX_PRX_P7 AC8 F21
FDI1_TX[3] PEG_TX#[3]
PEG_TX#[4] H19
+VCCP AA11 C17
{14} FDI_FSYNC0 FDI0_FSYNC PEG_TX#[5]
{14} FDI_FSYNC1 AC12 FDI1_FSYNC PEG_TX#[6] K15
F17
PEG_TX#[7]
{14} FDI_INT U11 F14
FDI_INT PEG_TX#[8]
A15
PEG_TX#[9]
1
{14} FDI_LSYNC0 AA10 J14
RC2 FDI0_LSYNC PEG_TX#[10]
{14} FDI_LSYNC1 AG8 H13
FDI1_LSYNC PEG_TX#[11]
24.9_0402_1% M10
PEG_TX#[12]
PEG_TX#[13] F10
D9
2
PEG_TX#[14]
eDP_COMPIO and ICOMPO signals PEG_TX#[15]
J4
EDP_COMP AF3
should be shorted near balls AD2
eDP_COMPIO
F22
eDP_ICOMPO PEG_TX[0]
B
and routed with typical +VCCP RC86 1 @ 2 10K_0402_5% AG11 eDP_HPD# PEG_TX[1] A23
B
impedance <25 mohms PEG_TX[2] D24
E21
PEG_TX[3]
AG4 G19
eDP_AUX# PEG_TX[4]
AF4 B18
eDP_AUX PEG_TX[5]
PEG_TX[6] K17
eDP
eDP
PEG_TX[7] G17
AC3 E14
eDP_TX#[0] PEG_TX[8]
AC4 C15
eDP_TX#[1] PEG_TX[9]
AE11 K13
eDP_TX#[2] PEG_TX[10]
AE7 G13
eDP_TX#[3] PEG_TX[11]
K10
PEG_TX[12]
AC1 G10
eDP_TX[0] PEG_TX[13]
AA4 eDP_TX[1] PEG_TX[14] D8
AE10 eDP_TX[2] PEG_TX[15] K4
AE6
eDP_TX[3]
IVY-BRIDGE_BGA1023
SA00004SX00
A A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/04/26 Deciphered Date 2011/10/18 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PROCESSOR(1/7) DMI,FDI,PEG
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-8101P
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, November 14, 2011 Sheet 4 of 46
5 4 3 2 1
5 4 3 2 1
+3VS
Buffered reset to CPU
+VCCP
1
CC1
0.1U_0402_16V4Z
1
2 RC3
75_0402_5%
+3VS
5
D UC1 RC4 D
2
1 43_0402_1% XDP_DBRESET# RC5 2 1 1K_040