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Keysight Technologies
An Innovative Simulation Workflow
for Debugging High-Speed Digital
Designs Using Jitter Separation

White Paper

Abstract
This paper presents a new simulation workflow for jitter separation analysis. Jitter
separation is a very promising tool that quickly identifies the sources of signal integrity
degradation and thus enables easy optimization of a design to meet the low jitter
requirements of multi-gigabit high speed digital SERDES devices.
1.0 Introduction As data rates in high-speed products increase, identifying and solving signal
integrity problems becomes critical. Timing margins are becoming increasingly
tight. Several distinct effects influence the integrity of signals.

The deviation of a signal transition from its ideal time is defined as jitter.
Jitter becomes a problem when out-of-place edges start to corrupt the zero/
one decision that should occur in the slicer circuit in the receiver. Breaking
jitter into its various components is required to diagnose the most severe jitter
problems. Several factors affect jitter. Power supply noise is a big contributor
to the total jitter in the system. A power delivery network has a substantial
impedance which causes a voltage ripple on the IC`s supply lines. This supply
noise translates into jitter on the clock and data edges. The amount of jitter is
modulated by channel dispersion as signals propagate in the system. Channel
loss, reflections and distortions from impedance discontinuities in the signal or
return path, lead to attenuated and smeared data edges which can then cause
inter-symbol interference (ISI). It is observed in both measurements and simula-
tions that jitter can be amplified by a lossy channel even when the channel is
linear, passive and noiseless [1].

1
C. Chastang, 2 A. Amedeo 1
V. Poisson, 1 P. Grison, 2 F. Demuynck C. Gautier, F. Costa
Thales Communications & Security Keysight