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A B C D E
SYSTEM DC/DC
Garda-D Block Diagram
TPS51120 40
Project code: 91.4A901.001 INPUTS OUTPUTS
PCB P/N : 55.4A901.XXX
(Discrete) REVISION : 05217-2 5V_S5
DCBATOUT
Mobile CPU
-2-0209
3D3V_S5
4 CLK GEN. (Hannstar, ACCL) 4
IDT CV125PA
G792
(ICS 954206) 3
Yonah 478 19
PCB STACKUP SYSTEM DC/DC
TPS51124 41
1.83G/2G/2.16G
4, 5 TOP INPUTS OUTPUTS
TVO
14 GND 1D05V_S0
HOST BUS 400/533/667MHz DCBATOUT
LVDS 14"WSXGA+ 1D8V_S3
DDR2 533/667MHz LCD 13
S
TPS51100 43
533 MHz RGB CRT
S
11,12 PCI Express x16 CRT VCC 1D8V_S3 DDR_VREF_S0
ATI
Calistoga M56 Ver.: B24 M54P / M52P
14
S
DDR2 533/667MHz
Ver.:A3 :71.945PM.A0U / QK58
KI.94501.006 / SL8Z4
M52 Ver.: A12
M54 Ver.: A12
45,46,47,48,49
GND
APL5332KAC 43
533 MHz 6,7,8,9,10
VRAM x4
3D3V_S0 2D5V_S0
11,12 BOTTOM
3 128/256M
50,51 3
DMI I/F 100MHz APL5912-U 43
Line In PCMCIA I/F PCMCIA
1D8V_S3 1D5V_S0
29
Codec TI SLOT
AZALIA PCI 7412 PWR SW Support
29 ALC883 TSP2220A TypeII MAXIM CHARGER
28 27
27 MAX8725 42
MIC In CARDBUS
PCI BUS 1394 INPUTS OUTPUTS
CardReader 1394
26 MS/MS Pro/xD/ CHG_PWR
CONN 18V 4.0A
INT.MIC 24,25 MMC/SD/SDIO DCBATOUT
6 in 1 UP+5V
Mini-PCI 26
Line Out
(SPDIF)
ICH7M 802.11A/B/G 30
5V 100mA
Ver. : B0, 71.ICH7M.A0U / QK65
29 OP AMP KI.80101.017 / SL8YB LAN CPU DC/DC
G1421B 29 TXFM ISL6262
10/100 RJ45 BCM5787MKFBG-A1 38,39
2 23 23 BCM5789KFBG-C1 2
BCM4401-E 22 BCM4401EKFBG-B0 INPUTS OUTPUTS
29 PCIEx1 Mini Card*1
802.11A/B/G 26 VCC_CORE_S0
DCBATOUT
Giga LAN 0~1.3V
INT.SPKR BCM5789/5787M 35 44A
SPI I/F BIOS
SST25LF080A
MODEM 34 ATI M54 DC/DC
15,16,17,18
LPC BUS 52
RJ11 MDC Card FAN5234
21
INPUTS OUTPUTS
SATA
PATA
PCI Express
SIO KBC
Renesas
LPC DCBATOUT VGA_CORE_S0
New card30 USB NS87381 RE144B DEBUG
3 PORT 32 31 34
CONN. APL5331KAC 43
21
1D8V_S0 1D2V_S0
21
1 PWR SW MINI USB FIR 32 Touch INT.
1
TPS223130 HDD 20 CDROM Blue-tooth Pad 33 KB 33
18 Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
BLOCK DIAGRAM
Size Document Number Rev
A3
AG1 -2
Date: Thursday, February 09, 2006 Sheet 1 of 53
A B C D E
ICH7M Integrated Pull-up 954305D 27Mhz/LCDCLK Spread Calistoga Strapping Signals and
and Pull-down Resistors ICH7-M EDS 17837 1.5V1
and Frequency Selection Table Configuration EDS 17050 0.71
page 7
SS3 SS2 SS1 SS0
Byte9 bit6 bit5 bit4 Spread Amount% page 3 Pin Name Strap Description Configuration
EE_DIN, EE_DOUT, GNT[3:0], GPIO[25], bit 7 CFG[2:0] FSB Frequency Select
GNT[4]#/GPIO48, GNT[5]#/GPO17, PME#, 0 0 0 0 -0.50 Down 001 = FSB533
ICH7 internal 20K pull-ups 011 = FSB667
LAD[3:0]#/FHW[3:0]#, LAN_RXD[2:0] 0 0 0 1 -1.00 Down others = Reserved
4 LDRQ[0], LDRQ[1]/GPIO[41], 0 0 1 0 -1.50 Down CFG[4:3] Reserved 4
PWRBTN#, TP[3] 0 0 1 1 -2.00 Down CFG5 DMI x2 Select 0 = DMI x2
1 = DMI x4 (Default)
0 1 0 0 -0.75 Down CFG6 Reserved
DD[7], DDREQ ICH7 internal 11.5K pull-downs
0 1 0 1 -1.25 Down CFG7 0 = Reserved
CPU Strap 1 =Mobile CPU(Default)
ACZ_BIT_CLK, ACZ_RST#, ACZ_SDIN[2:0], ICH7 internal 20K pull-downs 0 1 1 0 -1.75 Down
Reserved
ACZ_SDOUT, ACZ_SYNC, DPRSLPVR/GPIO16, 0 1 1 1 -2.25 Down CFG8
EE_CS,SPI_ARB, SPI_CLK, SPKR, 1 0 0 0 +-0.25 Center 0 = Reverse Lanes,15->0,14->1 ect..
CFG9 PCI Express Graphics 1= Normal operation(Default):Lane
1 0 0 1 +-0.5 Center Lane Reversal Numbered in order
USB[7:0][P,N] ICH7 internal 15K pull-downs
1 0 1 0 +-0.75 Center
CFG[11:10] Reserved
SATALED# ICH7 internal 15K pull-up 1 0 1 1 +-1.0 Center
XOR/ALL Z test 00 = Reserved
1 1 0 0 +-0.25 Center CFG[13:12] straps 01 = XOR mode enabled
LAN_CLK ICH7 internal 100K pull-down 10 = All Z mode enabled
1 1 0 1 +-0.5 Center 11 = Normal Operation
(Default)
1 1 1 0 +-0.75 Center
CFG[15:14] Reserved Reserved
ICH7M IDE Integrated Series 1 1 1 1 +-1.0 Center
CFG16 FSB Dynamic ODT 0 = Dynamic ODT Disabled
3 Termination Resistors Global R-comp Disable
1 = Dynamic ODT Enabled (Default)
0 = All R-comp Disable 3
CFG17 (All R-comps) 1 = Normal Operation (Default)
DD[15:0], DIOW#, DIOR#, DREQ,
approximately 33 ohm
PCI Routing page 16
CFG18 VCC Select 0 = 1.05V (Default)
DDACK#, IORDY, DA[2:0], DCS1#, 1 = 1.5V
DCS3#, IDEIRQ
IDSEL INT -> PIRQ REQ/GNT CFG19 DMI Lane Reversal 0 = Normal operation (Default):lane
A->G, B->B, Numbered in order
1 =Reverse Lane,4->0,3->1 ect...
7412 22 C->F, D->G 0
A/C -> E 0 = Only SDVO or PCIE x1 is
ICH7M Functional Strap Definitions page 16
MiniPCI 21 B/D -> E 1 CFG20 SDVO/PCIE
Concurrent
operational (Default)
1 =SDVO and PCIE x1 are operating
simultaneously via the PEG port
Signal Usage/When Sampled Comment LAN 23 A -> H 2 SDVOCRTL SDVO Present 0 = No SDVO Card present
ACZ_SDOUT XOR Chain Entrance/ Allows entrance to XOR Chain testing when TP3 _DATA (Default)
PCIE Port Config bit1, pulled low.When TP3 not pulled low at rising edge 1= SDVO Card present
Rising Edge of PWROK of PWROK,sets bit1 of RPC.PC(Config Registers:
offset 224h) NOTE: All strap signals are sampled with respect to the leading
edge of the Calistoga GMCH PWORK in signal.
ACZ_SYNC PCIE bit0, Sets bit0 of RPC.PC(Config Registers:Offset 224h)
Rising Edge of PWROK.
EE_CS Reserved This signal should not be pull high. History
EE_DOUT Reserved This signal should not be pull low.
2 GNT2# Reserved This signal should not be pull low. 2
Top-Block Sampled low:Top-Block Swap mode(inverts A16 for
GNT3# Swap Override. all cycles targeting FWH BIOS space).
Rising Edge of PWROK. Note: Software will not be able to clear the
Top-Swap bit until the system is rebooted
without GNT3# being pulled down.
GNT5#/ Boot BIOS Destination Controllable via Boot BIOS Destination bit
GPIO17#, Selection. (Config Registers:Offset 3410h:bit 11:10).
GNT4#/ Rising Edge of PWROK. GNT5# is MSB, 01-SPI, 10-PCI, 11-LPC.
GPIO48
DPRSLPVR Reserved This signal should not be pull high.
GPIO25 Reserved.
Rising Edge of RSMRST#. This signal should not be pull low.
INTVRMEN Integrated VccSus1_05 Enables integrated VccSus1_05 VRM when
VRM Enable/Disable. sampled high
Always sampled.
LINKALERT# Reserved Requires an external pull-up resistor.
REQ[4:1]# XOR Chain Selection.
Rising Edge of PWROK. TBD, Chapter 8.
1 1
SATALED# Reserved This signal should not be pull low.
Wistron Corporation
SPKR No Reboot. If sampled high, the system is strapped to the 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Rising Edge of PWROK. "No Reboot" mode(ICH7 will disable the TCO Timer Taipei Hsien 221, Taiwan, R.O.C.
system reboot feature). The status is readable
Title
via the NO REBOOT bit.
Reference
TP3 XOR Chain Entrance. This signal should not be pull low unless using Size Document Number Rev
A3
Rising Edge of PWROK. XOR Chain testing. AG1 SD
Date: Wednesday, February 08, 2006 Sheet 2 of 53
A B C D E
3D3V_S0
3D3V_S0 3D3V_S0
2 R158 1 3D3V_CLKPLL_S0 2 R213 1 3D3V_48MPWR_S0 3D3V_CLKGEN_S0 2 R155 1
0R0603-PAD 0R0603-PAD 0R0603-PAD
1
1
1
1
1
1
1
1
1
1
1
4 4
C228 C229 C301 C226 C257 C254 C230 C255 C303 C258 C508
SCD1U16V2ZY-2GP SC1U6D3V2ZY-GP SC1U6D3V2ZY-GP SC4D7U10V5ZY-3GP SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP
2
2
2
2
2
2
2
2
2
2
2
3D3V_S0
U24
1
RN35 1 4 SRN33J-5-GP-U CLK_MCH_3GPLL 7
R598 2 3 CLK_MCH_3GPLL# 7
10KR2J-3-GP R173 1 2 33R2J-2-GP PCLKCLK0 56 17
31 PCLK_KBC PCI0 LVDS
22 PCLK_LAN R176 1 2 33R2J-2-GP PCLKCLK1 3 18 RN21 1 4 SRN33J-5-GP-U CLK_PCIE_ICH 16
R179 22R2J-2-GP PCLKCLK2 PCI1 LVDS#
25 PCLK_PCM 2 1 4 2 3 CLK_PCIE_ICH# 16
2
R209 33R2J-2-GP PCLKCLK3 PCI2 CLK_MCH_3GPLL_1
32 PCLK_SIO 1 2 5 PCI3 SRC1 19
SS_SEL 34 PCLK_FWH R214 2 1 22R2J-2-GP 20 CLK_MCH_3GPLL_1# RN40 2 3 SRN33J-5-GP-U CLK_PCIE_LAN 35
R210 33R2J-2-GP SS_SEL SRC1# CLK_PCIE_ICH_1
H/L: 100/96MHz 30 PCLK_MINI 1 MINI 2 9 PCIF1/SEL100/96# SRC2 22 1 GIGA 4 CLK_PCIE_LAN# 35
1
16 CLK_ICHPCI R211 1 2 33R2J-2-GP ITP_EN 8 23 CLK_PCIE_ICH_1#
R597 PCIF0/ITP_EN SRC2# CLK_PCIE_LAN_1 RN25 SRN33J-5-GP-U
1 2 24 2 3 CLK_PCIE_SATA 15
10KR2J-3-GP
16 PM_STPPCI# R174 10KR2J-3-GP 55
SRC3
25 CLK_PCIE_LAN_1# 1 SATA 4 CLK_PCIE_SATA# 15
PCI_STOP# SRC3# CLK_PCIE_SATA_1
DY H/L : CPU_ITP/SRC7 SRC4 26
27 CLK_PCIE_SATA_1# RN29 1 4 SRN33J-5-GP-U CLK_PCIE_NEW 30
2
SRC4# CLK_PCIE_NEW_1
PCLK_FWH & PCLK_PCM 11,18 SMBC_ICH 46 SCL SRC5 31 2 NEW 3 CLK_PCIE_NEW# 30
3 47 30 CLK_PCIE_NEW_1# 3
need equal length 11,18 SMBD_ICH SDA SRC5#
33 CLK_PCIE_MINI1_1 RN27 1 4 SRN33J-5-GP-U CLK_PCIE_MINI1 26
SRC6 CLK_PCIE_MINI1_1#
SRC6# 32 2 MINIC 3 CLK_PCIE_MINI1# 26
14
15
DOT96
36 CLK_PCIE_PEG_1 RN28 1
Dummy when use UMA
4 SRN33J-5-GP-U
DOT96# CPU2_ITP/SRC7 CLK_PCIE_PEG 45
35 CLK_PCIE_PEG_1# 2 VGA 3 CLK_PCIE_PEG# 45
C256 CPU2_ITP#/SRC7#
1 2 GEN_XTAL_IN 50 44 CLK_CPU_BCLK_1 RN17 3 2 SRN33J-5-GP-U CLK_CPU_BCLK 4
GEN_XTAL_OUT_R GEN_XTAL_OUT 49 XTAL_IN CPU0 CLK_CPU_BCLK_1#
1 2 XTAL_OUT CPU0# 43 4 1 CLK_CPU_BCLK# 4
1
SC27P50V2JN-2-GP X2 R154 470R2J-2-GP 41
R177 1 CPU1
32 CLK14_SIO 2 22R2J-2-GP CPU1# 40 CLK_MCH_BCLK_1 RN19 3 2 SRN33J-5-GP-U CLK_MCH_BCLK 6
X-14D31818M-31GP 16 CLK_ICH14 R181 1 2 22R2J-2-GP GEN_REF 52 CLK_MCH_BCLK_1# 4 1 CLK_MCH_BCLK# 6
C225 82.30005.831 475R2F-L1-GP 2 R157 1GEN_IREF 39 REF
54 PM_STPCPU# 16
2
IREF CPU_STOP# CPU_SEL2
1 2 FSC/TEST_SEL 53 CPU_SEL2 4,7
16 CPU_SEL1 CPU_SEL1 4,7
SC27P50V2JN-2-GP 3D3V_S0 FSB/TEST_MODE CLK48 22R2J-2-GP 1 R601
10 VTT_PWRGD#/PD USB48/FSA 12 2 CLK48_ICH 16
22R2J-2-GP 1 R600 2 CLK48_CARDBUS 25
1 R602 2 CPU_SEL0 4,7
1
2 34 3D3V_CLKGEN_S0 2K2R2J-2-GP
VSS_PCI VDD_SRC
-2 modify 6 VSS_PCI VDD_SRC 21
R212 DY
10KR2J-3-GP 51 7
VSS_REF VDD_PCI
45 1
2
VSS_CPU VDD_PCI
38 CLK_EN# 38 VSSA
13 VSS48 VDD_REF 48
29 VSS_SRC VDD_CPU 42
37 3D3V_CLKPLL_S0
VDDA 3D3V_48MPWR_S0
VDD48 11
VDD_SRC 28
2 2
IDTCV125PAG-GP 71.00125.A0W
EMI capacitor
CLK_PCIE_MINI1 1 2 DY
EC20 SC22P50V2JN-4GP
CLK_PCIE_MINI1# 1 2 DY
EC18 SC22P50V2JN-4GP
PCLK_MINI 1 2 DY
EC19 SC22P50V2JN-4GP
RN34
CLK_PCIE_MINI1 1 4
CLK_PCIE_MINI1# 2 MINIC 3
SRN49D9F-GP CLK_ICH14 1 2 DY
RN42 RN18 EC17 SC22P50V2JN-4GP
CLK_PCIE_LAN 2 3 CLK_CPU_BCLK 1 4 CLK_ICHPCI 1 2 DY
CLK_PCIE_LAN# 1 GIGA 4 CLK_CPU_BCLK# 2 3 EC21 SC22P50V2JN-4GP
SRN49D9F-GP SRN49D9F-GP CLK48_ICH 1 2 DY