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A B C D E
1 1
PWWHA
2 TaiDi1 Plus 2
LA-7203P REV 0.1 Schematic
3
Intel Processor(Sandy Bridge) / PCH(Cougar Point) 3
2010-12-27 Rev 0.1
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/09/03 Deciphered Date 2012/12/31 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS, MB A7203
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019CT
Date: Monday, January 10, 2011 Sheet 1 of 43
A B C D E
A B C D E
Intel CPU
Sandy Bridge
1
rPGA-989 Memory BUS(DDRIII) 200pin DDRIII-SO-DIMM X2 1
37.5mm*37.5mm Dual Channel BANK 0, 1, 2, 3 page 11,12
page 5,6,7,8,9,10 1.5V DDRIII 1066/1333/1600 MT/s
CRT FDI X8 DMI X4
page 14
2.7GT/s 5GT/s
USB/B Left 2IN1 RTS5137 Int. Camera
USB port 0,1 USB port 10 USB port 11
USB page 24 page 27 page 13
5V 480MHz
LVDS Conn.
page 13
PCIeMini Card
2
USB WiMax USB port 9 2
5V 480MHz page 25
PCIe 1x PCIeMini Card
1.5V 5GT/s
WLAN PCIe port 2
Intel PCH page 25
Cougar Point - M
RTL8105E 10/100M SATA port 0 SATA HDD
RJ45 PCIe 1x 5V 6GHz(600MB/s) SATA port 1
page 26 RTL8111E 1G PCIe port 1 1.5V 5GT/s page 24
page 26
FCBGA-989
25mm*25mm SATA port 2 SATA ODD
5V 3GHz(300MB/s) SATA port 4
page 24
page 15,16,17,18,19,20,21,22,23
3 3
LPC BUS HD Audio 3.3V 24MHz
3.3V 33 MHz
HDA Codec
ALC259
SPI ROM Debug Port ENE KB9012 page 28
page 31 page 30
(4MB) 15
page
RTC CKT.
page 16
Touch Pad Int.KBD EC ROM Int. SPK Conn HP & MIC
page 32 page 32 MIC Conn
DC/DC Interface CKT. (128KB) 31
page
page 29 page 29 page 29
page 33
4 4
Power Circuit DC/DC
page 34,35,36,37,38,39
,40,41
Security Classification Compal Secret Data Compal Electronics, Inc.
2010/09/03 2012/12/31 Title
Power/B Issued Date Deciphered Date
SCHEMATICS, MB A7203
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DA40000XR10 page 32
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019CT
Date: Monday, January 10, 2011 Sheet 2 of 43
A B C D E
5 4 3 2 1
DESIGN CURRENT 0.1A +3VL
B+
Ipeak=5A, Imax=3.5A, Iocp min=7.9A DESIGN CURRENT 5A +5VALW
SUSP#
DESIGN CURRENT 2A +1.8VS
SY8033BDBC
SUSP
D D
N-CHANNEL DESIGN CURRENT 4A +5VS
SI4800
ODD_EN#
P-CHANNEL DESIGN CURRENT 1.8A +5VS_ODD
AO-3413
TPS51125ARGER
Ipeak=5A, Imax=3.5A, Iocp min=7.7A DESIGN CURRENT 5A +3VALW
WOL_EN#
P-CHANNEL DESIGN CURRENT 330mA +3V_LAN
AO-3413
C C
SUSP
N-CHANNEL DESIGN CURRENT 4A +3VS
SI4800 LCD_ENVDD
P-CHANNEL DESIGN CURRENT 1.5A +LCD_VDD
AO-3413
VR_ON
Ipeak=94A, Imax=52A, Iocp min=122A DESIGN CURRENT 94A +CPU_CORE
ISL95831HRTZ-T Ipeak=33A, Imax=21.5A, Iocp min=40A DESIGN CURRENT 33A +GFX_CORE
SUSP#
Ipeak=17A, Imax=11.9A, Iocp min=19.23A DESIGN CURRENT 15A +1.05VS_VCCP
TPS51117RGYR
B B
VCCPPWRGD
Ipeak=6A, Imax=4.2A, Iocp min=7A DESIGN CURRENT 6A +VCCSA
TPS51117RGYR
SYSON
Ipeak=9A, Imax=6.3A, Iocp min=9.92A DESIGN CURRENT 10A +1.5V
TPS51117RGYR SUSP
N-CHANNEL DESIGN CURRENT 2A +1.5V_CPU
FDS6676AS
SUSP
N-CHANNEL DESIGN CURRENT 2A +1.5VS
SI4800
+3V
DESIGN CURRENT 1A +1.05V
APL5930KAI-TRG
0.75VR_EN#
A A
DESIGN CURRENT 1.5A +0.75VS
UP7711U8
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/09/03 Deciphered Date 2012/12/31 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS, MB A7203
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019CT
Date: Monday, January 10, 2011 Sheet 3 of 43
5 4 3 2 1
A B C D E
( O MEANS ON X MEANS OFF )
Voltage Rails
+5VS
+RTCVCC B+ +3VL +5VALW +1.5V
+3VS
+3VALW
+1.8VS
+VSB
power +1.5VS
1 plane +1.05VS
1
+0.75VS
+CPU_CORE
+GFX_CORE
State
BTO Option Table
Function MINI PCI-E SLOT LAN Camera & Mic
S0 description SLOT1 LAN Camera & Mic
O O O O O O
explain WIMAX 10/100M Giga Camera & Mic
S1
O O O O O O
BTO WIMAX@ 8105E@ 8111E@ CAM@
2 2
S3
O O O O O X
S5 S4/AC
O O O O X X
S5 S4/ Battery only
O O O X X X
S5 S4/AC & Battery
don't exist
O X X X X X
PCH SM Bus Address
Power Device HEX Address
+3VS DDR SO-DIMM 0 A0 H 1010 0000 b
3
+3VS DDR SO-DIMM 1 A4 H 1010 0100 b 3
+3VS Clock Generator D2 H 1101 0010 b
+3VS WLAN/WIMAX
SIGNAL
STATE SLP_S3# SLP_S4# SLP_S5#
EC SM Bus1 Address EC SM Bus2 Address
Full ON HIGH HIGH HIGH
Power Device HEX Address Power Device HEX Address S1(Power On Suspend) HIGH HIGH HIGH
+3VL Smart Battery 16 H 0001 0110 b +3VS PCH 96 H 1001 0110 b S3 (Suspend to RAM) LOW HIGH HIGH
S4 (Suspend to Disk) LOW LOW HIGH
S5 (Soft OFF) LOW LOW LOW
4 4
G3 LOW LOW LOW
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/09/03 Deciphered Date 2012/12/31 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS, MB A7203
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
Custom A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019CT
Date: Monday, January 10, 2011 Sheet 4 of 43
A B C D E
5 4 3 2 1
JCPUB
100 MHz
@ PROC_SELECT# A28 CLK_CPU_DMI Stuff R41 and R42 if do not support eDP
CLK_CPU_DMI <16>
MISC
BCLK
CLOCKS
1000P_0402_50V7K 2 1 C487 PM_DRAM_PWRGD_R H_SNB_IVB# C26 A27 CLK_CPU_DMI#
<19> H_SNB_IVB# SNB_IVB# BCLK# CLK_CPU_DMI# <16>
@ +1.05VS_VCCP
120 MHz
1000P_0402_50V7K 2 1 C488 H_PWRGOOD T1 PAD TP_SKTOCC# AN34 SKTOCC# CLK_CPU_DPLL
DPLL_REF_SSCLK A16
A15 CLK_CPU_DPLL# CLK_CPU_DPLL# R42 1 2 1K_0402_5%
DPLL_REF_SSCLK#
D CLK_CPU_DPLL R41 1 D
2 1K_0402_5%
T2 PAD H_CATERR# AL33 CATERR#
THERMAL
H_PECI AN33 R8 H_DRAMRST#
<30> H_PECI PECI SM_DRAMRST# H_DRAMRST# <7>
DDR3
MISC
+1.05VS_VCCP R450
<30,35> H_PROCHOT# 1 2 H_PROCHOT#_R AL32 PROCHOT# SM_RCOMP[0] AK1 SM_RCOMP_0 R1437 2 1 140_0402_1% DDR3 Compensation Signals
56_0402_5% A5 SM_RCOMP_1 R1438 2 1 25.5_0402_1% Layout Note:Place these
R47 SM_RCOMP[1]
2 1 62_0402_5% H_PROCHOT#
SM_RCOMP[2] A4 SM_RCOMP_2 R1439 2 1 200_0402_1% resistors near Processor
H_THERMTRIP# AN32
<20> H_THERMTRIP# THERMTRIP#
R51 2 1 10K_0402_5% H_PWRGOOD
Remove R14(o ohm) for HW Review demand AP29 XDP_PRDY#_R R1 1 @ 2 0_0402_5% XDP_PRDY#
PRDY# XDP_PREQ#_R R2 1 @
PREQ# AP27 2 0_0402_5% XDP_PREQ#
AR26 XDP_TCK_R R4 1 @ 2 0_0402_5% XDP_TCK
TCK
PWR MANAGEMENT
XDP_TMS_R R6 1 @ 2 0_0402_5% XDP_TMS
JTAG & BPM
TMS AR27
<17> H_PM_SYNC H_PM_SYNC AM34 AP30 XDP_TRST#_R R7 1 @ 2 0_0402_5% XDP_TRST# Routed as a single daisy chain
PM_SYNC TRST#
AR28 XDP_TDI_R R8 1 @ 2 0_0402_5% XDP_TDI
TDI XDP_TDO_R R10 1 @
TDO AP26 2 0_0402_5% XDP_TDO
<20> H_PWRGOOD H_PWRGOOD AP33 R36
UNCOREPWRGOOD
1 2 +3VS
1K_0402_5%
AL35 XDP_DBRESET#_R R11 1 @ 2 0_0402_5% XDP_DBRESET#
DBR# XDP_DBRESET# <17>
PM_SYS_PWRGD_BUF 1 2 PM_DRAM_PWRGD_R V8
C R454 130_0402_5% SM_DRAMPWROK C
AT28 XDP_BPM#0_R R12 1 @ 2 0_0402_5% XDP_BPM#0
BPM#[0] XDP_BPM#1_R R13 1 @ 0_0402_5% XDP_BPM#1
BPM#[1] AR29 2
AR30 XDP_BPM#2_R R15 1 @ 2 0_0402_5% XDP_BPM#2
BUF_CPU_RST# BPM#[2] XDP_BPM#3_R R18 1 @ 0_0402_5% XDP_BPM#3
AR33 RESET# BPM#[3] AT30 2 PU/PD for JTAG signals +1.05VS_VCCP
BPM#[4] AP32
BPM#[5] AR31 Close to CPU side
AT31 XDP_TMS_R R28 2 1 51_0402_5%
+3VALW BPM#[6]
BPM#[7] AR32
XDP_TDI_R R29 2 1 51_0402_5%
+1.5V_CPU XDP_TDO R30 2 1 51_0402_5%
1
C93
0.1U_0402_16V4Z Sandy Bridge_rPGA_Rev0p61 @ XDP_TCK_R R31 2 1 51_0402_5%
1
PS3@
2 XDP_TRST#_R R32 2 1 51_0402_5%
U10 R339
R312 74AHC1G09GW_TSSOP5 200_0402_5%
5
0_0402_5% PS3@
2
1 2 1
P
<17,30> PM_PWROK
<17> DRAMPWROK
PS3@
2
B
O 4 PM_SYS_PWRGD_BUF FAN Control Circuit (RPM and PWM)
A
G
+5VS
1
1A
3
R340
39_0402_5% 2 JFAN2 @
@ C12 +FAN2 1
R384 1 1
2 0_0402_5% 10U_0805_10V6K 2
1 2
WPS3@ 2
D 2 3 3
Q5 U1 1 C14
<9,25,33> SUSP SUSP 2 2N7002_SOT23 1 8 1000P_0402_50V7K 4
G @ EN GND @ GND
2 VIN GND 7 5 GND
B S +FAN2 1 B
3 6
3
VOUT GND
<30> EN_DFAN1 4 VSET GND 5 ACES_85204-0300N
10mil 1
APL5607KI-TRG_SO8 R14 10K_0402_5% @
C15 2 1 +3VS
JXDP @ 10U_0805_10V6K
XDP Connector XDP_PREQ# 1
2
1
FAN_SPEED1
XDP_PRDY# 2 C13