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VER : F3B
VM9M Block Diagram Intel UMA
A A
FAN & THERMAL POWER
Penryn EMC1423-1-AIZL-TR
PG 31 REGULATOR CPU VR
POWER (478 Micro-FCPGA) +1.5V_RUN/+1.05V_VCCP PG 37 PG 39
CLOCK REGULATOR REGULATOR
SLG8SP513V +1.8V_SUS /+0.9V_DDR_VTT +3.3V_ALW/+5V_SUS/+15V_ALW
BATT (QFN-64)
PG 3,4
AC/BATT CHARGER PG 36 PG 17 PG 38 PG 40
CONNECTOR 800/1066 MHz
RUN POWER SW
PG 42 +3.3V_SUS/+5V_SUS
+5V/+3.3V/+1.8V PG 41 LVDS Panel Connector
Cantiga (WXGA) PG 17
B
VGA B
CRT CONN.
DDR2-SODIMM*2 667/800 MHZ DDR II 1299 uFCBGA PG 19
PG 15,16
PG 5,6,7,8,9,10 RTL8111DL RJ45/Magnetics
GLAN PG 34
PG 34
DMI interface
SATA-ODD SATA PCIE
PG 28 PCIE MINI-CARD
WLAN
PG 26
SATA-HDD SATA PCIE
PG 28 ICH9-M
PCIE
Bluetooth USB 2.0 676 BGA
C USB2.0 EXPRESS-CARD34 C
PG 26 PG 21
USB2.0
IHDA USB conn x 2 PG 27
PG 11,12,13,14
USB conn x 2
Board to board PG 33
LPC
USB2.0
AUDIO/AMP Panel Connector
MODEM (AMOM) (To CCD) PG 18
CX20583-10z
CX20548-11Z
PCIE 3-in-1 Card Reader Card Reader CONN.
PG 32 Board to board KBC
ITE8502 R5U230(1394a+Media)
18X8 1394a CONN
Keyboard
Audio PG 23 Board to board PG 33
Audio SPK RJ-11conn PG 29
D
Jacks x2 D
conn 2Wx1 SPI PS/2
PG 32 PG 33
PG 32 USER QUANTA
FLASH
2M bytes
Touchpad INTERFACE COMPUTER
PG 30 Title
Schematic Block Diagram
PG 24 PG 29 Size Document Number Rev
VM9M 1A
Date: Monday, June 08, 2009 Sheet 1 of 46
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
Table of Contents Power States
CONTROL
PAGE DESCRIPTION POWER PLANE VOLTAGE PAGE DESCRIPTION SIGNAL ACTIVE IN
1 Schematic Block Diagram
2 Front Page +PWR_SRC 10V~+19V 4,18,24,36,37,3,8,39,40,44 MAIN POWER S0~S5
3-4 Penryn
+RTC_CELL +3.0V~+3.3V 11,14,23,24 RTC S0~S5
5-10 Cantiga
A 11-14 ICH9M +3.3V_ALW +3.3V 3,23,24,30,35,36,38,40,41,42,45 8051 POWER ALWON S0~S5 A
15-16 DDRII SO-DIMM(200P)
+5V_ALW2 +5V 37,38,40,41,42 LCD/CHARGE POWER ALWON S0~S5
17 Clock Generator
18 LCD Conn. +15V_ALW +15V 11,18,40,41 LARGE POWER +5V_ALW S0~S5
19 CRT Conn
+3.3V_LAN +3.3V 34 LAN POWER
21 Express card
23 SIO (ITE8512) +5V_SUS +5V 14,27,30,39,40,41,44 SLP_S5# CTRLD POWER SUS_ON
24 FLASH/RTC
+3.3V_SUS +3.3V 3,11,12,13,14,18,25,30,37,39,41,45 SLP_S5# CTRLD POWER 3.3V_SUS_ON
25 BLANK PAGE
26 Mini Card / BT +1.8V_SUS +1.8V 6,8,9,15,37,38,41 SODIMM POWER DDR_ON
27 USB
+0.9V_DDR_VTT +0.9V 16,38,41 SODIMM POWER 0.9V_DDR_VTT_ON
28 SATA Conn
29 TP / KEYBOARD +5V_RUN +5V 14,18,19,21,25,28,29,30,31,32,41,44 SLP_S3# CTRLD POWER RUN_ON
30 SWITCH /LED 3,6,8,9,11,12,13,14,15,17,30,31,32,34,18,19,
+3.3V_RUN +3.3V 20,21,23,25,26,28,41,44,45 SLP_S3# CTRLD POWER 3.3V_RUN_ON
31 FAN & Thermal
B 32 Audio CODEC/Phone Jack +1.5V_RUN +1.5V 4,9,14,26,37,41,44 CALISTOGA/ICH8 POWER 1.5V_RUN_ON B
33 Board To Board
+1.05V_VCCP +1.05V 3,4,6,8,9,11,14,37,44 CPU/CALISTOGA/ICH8 POWER 1.05V_RUN_ON
34 LAN / TRANSFORM
35 BLANK PAGE +VCC_CORE +0.7V~+1.77V 4,39 CPU CORE POWER IMVP_VR_ON
36 Battery Selector & Charger LCDVCC_TST_EN
+LCDVCC +3.3V 18 LCD Power & ENVDD
37 1.05VCCP / 1.5VRUJN
38 DDR2_1.8VSUS, 0.9V +5V_MOD +5V 28 Module Power
39 CPU_MAX17410(2phase)
+5V_HDD +5V 28 HDD Power
40 MAX17020 (+5.5V,+3,3V)
41 RUN Power Switch +PBATT +10V~+17V 42 MAIN BATTERY CHG_PBATT
42 DCIN,Batt
43 PAD& SCREW
44 EMI CAP
45 SMBUS BLOCK
46 Power Block Dianram
C C
GND PLANE PAGE DESCRIPTION
GND ALL
D D
QUANTA
Title
COMPUTER
Index & Power Status
Size Document Number Rev
VM9M 1A
Date: Wednesday, June 03, 2009 Sheet 2 of 46
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
H_A#[3..16] U16A H_D#[0..63] U16B H_D#[0..63]
[5] H_A#[3..16] [5] H_D#[0..63] H_D#[0..63] [5]
H_A#3 J4 H1 H_D#0 E22 Y22 H_D#32
A[3]# ADS# H_ADS# [5] D[0]# D[32]#
H_A#4 L5 E2 H_D#1 F24 AB24 H_D#33
A[4]# BNR# H_BNR# [5] D[1]# D[33]#
H_A#5 H_D#2 H_D#34
ADDR GROUP 0
ADDR GROUP 0
L4 G5 H_BPRI# [5] E26 V24
H_A#6 A[5]# BPRI# H_D#3 D[2]# D[34]# H_D#35
K5 G22 V26
H_A#7 A[6]# H_D#4 D[3]# D[35]# H_D#36
M3 H5 H_DEFER# [5] F23 V23
H_A#8 N2 A[7]# DEFER# F21 H_D#5 G25 D[4]# D[36]# T22 H_D#37
A[8]# DRDY# H_DRDY# [5] D[5]# D[37]#
H_A#9 J1 E1 H_D#6 E25 U25 H_D#38
A[9]# DBSY# H_DBSY# [5] D[6]# D[38]#
H_A#10 H_D#7 H_D#39
DATA GRP 0
DATA GRP 0
DATA GRP 2
N3 H_BR0# [5] E23 U23
H_A#11 A[10]# H_D#8 D[7]# D[39]# H_D#40
P5 F1 K24 Y25
H_A#12 P2 A[11]# BR0# R26 56 H_D#9 G24 D[8]# D[40]# W22 H_D#41
H_A#13 A[12]# H_IERR# H_D#10 D[9]# D[41]# H_D#42
CONTROL
CONTROL
L2 D20 1 2 +1.05V_VCCP J24 Y23
A
H_A#14 A[13]# IERR# H_D#11 D[10]# D[42]# H_D#43 A
P4 B3 H_INIT# [11] J23 W24
H_A#15 A[14]# INIT# H_D#12 D[11]# D[43]# H_D#44
P1 H22 W25
H_A#16 R1 A[15]# H4 H_D#13 F26 D[12]# D[44]# AA23 H_D#45
A[16]# LOCK# H_LOCK# [5] D[13]# D[45]#
M1 H_D#14 K22 AA24 H_D#46
[5] H_ADSTB#0 H_REQ#[0..4] ADSTB[0]# D[14]# D[46]#
C1 Reserve from EMI R90 1 2 0 603 H_D#15 H23 AB25 H_D#47
[5] H_REQ#[0..4] RESET# H_RESET# [5] D[15]# D[47]#
H_REQ#0 K3 F3 J26 Y26
REQ[0]# RS[0]# H_RS#0 [5] [5] H_DSTBN#0 DSTBN[0]# DSTBN[2]# H_DSTBN#2 [5]
H_REQ#1 H2 F4 H26 AA26
REQ[1]# RS[1]# H_RS#1 [5] [5] H_DSTBP#0 DSTBP[0]# DSTBP[2]# H_DSTBP#2 [5]
H_REQ#2 K2 G3 H25 U22
REQ[2]# RS[2]# H_RS#2 [5] [5] H_DINV#0 DINV[0]# DINV[2]# H_DINV#2 [5]
H_REQ#3 J3 G2
REQ[3]# TRDY# H_TRDY# [5]
H_REQ#4 L1 H_D#[0..63] H_D#[0..63]
H_A#[17..35] REQ[4]# [5] H_D#[0..63] H_D#[0..63] [5]
G6 H_D#16 N22 AE24 H_D#48
[5] H_A#[17..35] HIT# H_HIT# [5] D[16]# D[48]#
H_A#17 Y2 E4 H_D#17 K25 AD24 H_D#49
A[17]# HITM# H_HITM# [5] D[17]# D[49]#
H_A#18 U5 H_D#18 P26 AA21 H_D#50
H_A#19 A[18]# ITP_BPM#0 H_D#19 D[18]# D[50]# H_D#51
ADDR GROUP 1
ADDR GROUP 1
R3 AD4 PAD T30 R23 AB22
H_A#20 A[19]# BPM[0]# ITP_BPM#1 H_D#20 D[19]# D[51]# H_D#52
W6
A[20]# BPM[1]#
AD3 PAD T34 Layout Note: L23
D[20]# D[52]#
AB21
H_A#21 ITP_BPM#2 H_D#21 H_D#53
XDP/ITP SIGNALS
XDP/ITP SIGNALS
U4 AD1 PAD T112 Place voltage M24 AC26
H_A#22 A[21]# BPM[2]# ITP_BPM#3 H_D#22 D[21]# D[53]# H_D#54
DATA GRP 1
Y5 AC4 L22 AD20
DATA GRP 3
A[22]# BPM[3]# PAD T29 divider within D[22]# D[54]#
H_A#23 U1 AC2 ITP_BPM#4 H_D#23 M23 AE22 H_D#55
A[23]# PRDY# PAD T111 D[23]# D[55]#
H_A#24 R4 AC1 ITP_BPM#5 0.5" of GTLREF H_D#24 P25 AF23 H_D#56
H_A#25 A[24]# PREQ# ITP_TCK H_D#25 D[24]# D[56]# H_D#57
T5 AC5 pin P23 AC25
H_A#26 T3 A[25]# TCK AA6 ITP_TDI H_D#26 P22 D[25]# D[57]# AE21 H_D#58
H_A#27 A[26]# TDI ITP_TDO H_D#27 D[26]# D[58]# H_D#59
W2 AB3 T24 AD21
H_A#28 A[27]# TDO ITP_TMS +1.05V_VCCP H_D#28 D[27]# D[59]# H_D#60
W5 AB5 R24 AC22
H_A#29 A[28]# TMS ITP_TRST# H_D#29 D[28]# D[60]# H_D#61
Y4 AB6 L25 AD23
H_A#30 U2 A[29]# TRST# C20 ITP_DBRESET# H_D#30 T25 D[29]# D[61]# AF22 H_D#62
A[30]# DBR# PAD T114 D[30]# D[62]#
2
H_A#31 V4 H_D#31 N25 AC23 H_D#63
H_A#32 W3 A[31]# R290 L26 D[31]# D[63]# AE25
A[32]# [5] H_DSTBN#1 DSTBN[1]# DSTBN[3]# H_DSTBN#3 [5]
H_A#33 AA4 THERMAL R16 56 +1.05V_VCCP 1K/F M26 AF24
A[33]# [5] H_DSTBP#1 DSTBP[1]# DSTBP[3]# H_DSTBP#3 [5]
H_A#34 AB2 N24 AC20
A[34]# [5] H_DINV#1 DINV[1]# DINV[3]# H_DINV#3 [5]
B H_A#35 AA3 D21 H_PROCHOT# B
A[35]# PROCHOT# PAD T1
1
V1 A24 H_THERMDA V_CPU_GTLREF AD26 R26 COMP0 Note:
[5] H_ADSTB#1 ADSTB[1]# THERMDA GTLREF
THERMDC
B25 H_THERMDC R14 2 1 *1K/F_NC CPU_TEST1 C23
TEST1
MISC COMP[0]
COMP[1]
U26 COMP1
H_DPRTSTP need to daisy chain
1
A6 R17 2 1 *1K/F_NC CPU_TEST2 D25 AA1 COMP2
[11] H_A20M# A20M# TEST2 COMP[2] from ICH9 to IMVP6 to CPU.
H_THERMTRIP# R289 PAD T96 CPU_TEST3 COMP3
ICH
[11] H_FERR# A5 C7 H_THERMTRIP# [6,11] C24 Y1
C4 FERR# THERMTRIP# 2K/F PAD T97 CPU_TEST4 AF26 TEST3 COMP[3]
[11] H_IGNNE# IGNNE# TEST4
PAD T110 CPU_TEST5 AF1 E5
TEST5 DPRSTP# H_DPRSTP# [6,11,39]
D5 H CLK PAD T95 CPU_TEST6 A26 B5
[11] H_STPCLK# STPCLK# TEST6 DPSLP# H_DPSLP# [11]
2
C6 PAD T33 CPU_TEST7 C3 D24
[11] H_INTR LINT0 TEST7 DPWR# H_DPWR# [5]
[11] H_NMI B4 A22 CLK_CPU_BCLK [17] [6,17] CPU_MCH_BSEL0 B22 D6 H_PWRGOOD [11]
LINT1 BCLK[0] BSEL[0] PWRGOOD
[11] H_SMI# A3 A21 CLK_CPU_BCLK# [17] [6,17] CPU_MCH_BSEL1 B23 D7 H_CPUSLP# [5]
SMI# BCLK[1] BSEL[1] SLP#
[6,17] CPU_MCH_BSEL2 C21 AE6 H_PSI# [39]
BSEL[2] PSI#
Quard Core Only
F6 D2 Penryn Ball-out Rev 1a
TDI_1/RSV RSVD[06] PAD T32
D3
TDO_2/RSV COMP0
N5 COMP1
BMP_1#[0]/RSV COMP2
M4
BMP_1#[1]/RSV
FSB BCLK BSEL2 BSEL1 BSEL0
B2 COMP3
BMP_1#[2]/RSV
AE8
BMP_1#[3]/VSS 533 133