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ZY9B SYSTEM BLOCK DIAGRAM GPU CORE PWR
ISL6264 P44
CHARGER
ISL88731 P38
GPU IO PWR 3/5V SYS PWR
ISL62827 P45 ISL6237 P39
D DISCHARGER CPU CORE PWR D
+3V,+ 5V,+1.5V,+1.05V,+1.1V_VTT
P47 ISL62882 P40
CLOCK GENERATOR Fan Driver
SELGO: SLG8SP585V
BCLK: 133MHz
PEG_CLK: 100MHz
DPLL_REF_SSCLK: 120MHz
intel (PWM Type) +1.0V/+1.5V CPU VTT
ARD: 1.05V
CFD: 1.1V
X'TAL
14.318MHz P3
P36 G93334 + Linear P47 UP61111AQDD P41
CPU VGFX_AXG VTT 1.05V
DDR SYSTEM MEMORY
CPU & PCH
Dual Channel Arrandale (SG)* ISL62881 P46 UP61111AQDD P42
DDR III Clarksfield (Discrete)
XDP Conn.
800/ 1066 MHz P16
SO-DIMM 0 THERMAL DDR3 PWR
SO-DIMM 1 800 MT/s 1066 MT/s PROTECTION P48 TPS5116 P43
P14, 15 rPGA 989
(37.5mm X 37.5mm)
PCI-E PCIE
X16
P4.5.6.7 AMD GPU DISPLAY PORT
FDI DMI 2.5GT/s HDMI DISPLAY PORT
P26
Broadway-LP / Madison-Pro
1GB (64Mb x 32 IO x 8 pcs) CRT
LVDS
C
*[Arrandale Only] X4 DMI interface P17,18,19,20,21,22,23,24 HDMI P26
C
X'TAL
27.0MHz
Graphics Interfaces
FDI DMI LVDS_CRT_HDMI
INT_HDMI *[Arrandale Only]
CRT
HDD (SATA) *2
intel INT_CRT *[Arrandale Only]
Switch Grapgics P25
Note:
HM55 does not support USB 6 & 7
HM55 does not support SATA 2 & 3 P31 SATA0
INT_LVDS *[Arrandale Only] P25, 26 LVDS P25
SATA
SATA5 3.0 GT/s
Ibex Peak_M USB0
eSATA Conn. eSATA Buffer SATA1
P34 ODD (SATA)
USB 9
(Debug)
P34 PCI-Express PCIE-4 New Card
P31 PCI-E
2.5GT/s CLKOUT_PEG_4
SATA4 USB 0 P33
USB Port x 5
USB 1, 3, 11, 12 P34 USB 2.0 PCIE-1 & 2
B
(Debug)
USB mBGA 25mm)
676
(27mm X CLKOUT_PEG_1&3
Mini Card B
RTC WLAN / TV
X'TAL
P9
Bluetooth Azalia P8.9.10.11.12.13
32.768KHz
USB 10 & 13 P32
HDA PCIE-5 PCIE-6
USB 4 P36
CLKOUT_PCIE2 CLKOUT_PEG_B
SPI LPC USB10 & 13
CCD
USB 8 P29 X'TAL IEEE1394 & Broadcom
32.768KHz
Media Cardreader Giga-LAN
Audio CODEC SPI ROM EC (WPC775C)
FingerPrint 4MB x1 (Basic ME+Braidwood) JMB380-QGAZ0B BCM57780
ALC669X P29 P9 P27 X'TAL P28 X'TAL
USB 2 P29 P37 24.576MHz 25MHz
ONFi 2.0
Touch Screen
USB 5 P34 Braidwood IEEE1394a Card Reader Transformer P28
Dual Channel NAND Interface SPI ROM connector P26 Connector P26
P16 P37
A A
Front Stereo Amp Center Mono Amp Rear Audio Amp Sub-Amplifier
RJ45 Connector
P28
(G1453L/ 2W+2W) (G1442/ 2W) & Head phone (MAX9737) Touch Pad MMB
P30 P29 AN12947A P30 P30 P36 P35
SSID: DISCRETE: 030A
SSID: SWITCH GFX: 0308 Quanta Computer Inc.
Front Speaker Center Speaker Speaker S/PDIF SUBWOOFER Line in MIC Jack Int. D-MIC PROJECT : ZY9B
K/B COON. CIR SVID: 1025 Size Document Number Rev
P30 P29 P30 P30 P30 P30 P30 P125 P30 P36 P37
1A
ZY9B Block Diagram
Date: Monday, September 21, 2009 Sheet 1 of 49
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1 2 3 4 5 6 7 8
GPU PWR CTRL Option 1 (Default/ VDDR3 before VDDC)
+3.3V VIN VIN +1.5V +1.5V_SUS +1.8V +5V
VDDR3 +3V_D VDDC PG_GPUIO_EN VDDCI PG_1V_EN +1V (DP PLL PWR) PG_1.5V_EN VDDR1 PG_1.5V_EN VDDR4 PG_1.5V_EN BJT dGPU_PWROK MOS
dGPU_VRON dGPU_PWR_EN#
MOS (AO3413) ISL6264 ISL62872 G9334ADJ & MOS MOS (AO4710) MOS (AO6402) AO3413
P22 P44 P45 P47 P43 P43 P22 P22
A +3_D (0.5A) +VGPU_CORE (20A) +VGPU_IO (4.5A) +1V (3A) +1.5V_GPU (10A) +1.8V_GPU (3A) +5_GPU A
GPU PWR CTRL Option 2 (VDDR3 after VDDR1)
VIN VIN +1.5V +1.5V_SUS +3.3V +1.8V +5V
VDDC PG_GPUIO_EN VDDCI PG_1V_EN +1V (DP PLL PWR) PG_1.5V_EN VDDR1 +1.5V_GPU VDDR3 +3V_D VDDR4 PG_1.5V_EN BJT dGPU_PWROK MOS
dGPU_VRON dGPU_PWR_EN#
ISL6264 ISL62872 G9334ADJ & MOS MOS (AO4710) MOS (AO3413) MOS (AO6402) AO3413
P44 P45 P47 P43 P22 P43 P22 P22
+VGPU_CORE (20A) +VGPU_IO (4.5A) +1V (3A) +1.5V_GPU (10A) +3_D (0.5A) +1.8V_GPU (3A) +5_GPU
Thermal Follow Chart
Power States
CONTROL
POWER PLANE VOLTAGE DESCRIPTION ACTIVE IN
SIGNAL
B VIN +10V~+19V MAIN POWER ALWAYS ALWAYS B
+VCCRTC +3V~+3.3V RTC POWER ALWAYS ALWAYS NTC
Thermal
+3VPCU +3.3V EC POWER ALWAYS ALWAYS
Protection
+5VPCU +5V CHARGE POWER ALWAYS ALWAYS
+15V +15V CHARGE PUMP POWER ALWAYS ALWAYS
+3V_S5 +3.3V LAN/BT/CIR POWER S5_ON S0-S5 CPU 3V/5 V
H_ORICHOT# PM_THRMTRIP# SYS_SHDN#
CORE PWR
CPU WIRE-AND SYS PWR
+5V_S5 +5V USB POWER S5_ON S0-S5 H/W Throttling
+5V +5V HDD/ODD/Codec/TP/CRT/HDMI POWER MAINON S0
+3V +3.3V PCH/GPU/Peripheral component POWER MAINON S0
SML1ALERT#
+1.5VSUS +1.5V CPU/SODIMM CORE POWER SUSON S0-S3
PCH FAN Driver FAN
+0.75V_DDR_VTT +0.75V SODIMM Termination POWER MAINON S0
+VGFX_AXG variation Internal GPU POWER GFX_ON S0
SM-Bus
+1.8V +1.8V CPU/PCH/Braidwood POWER MAINON S0
C C
+1.5V +1.5V MINI CARD/NEW CARD POWER MAINON S0
EC
+1.1V_VTT +1.05V or +1.1V CPU VTT POWER MAINON S0 CPUFAN#
+1.05V +1.05V PCH CORE POWER MAINON S0
+VCC_CORE variation CPU CORE POWER VRON S0
LCDVCC +3.3V LCD POWER LVDS_VDDEN S0
+5V_GPU +5V SWITCHABLE PWM IC POWER dGPU_PWR_EN# Discrete enable
+GPU_CORE +0.9V~+1.1V GPU CORE POWER +3V_D Discrete enable
+GPU_IO +0.9V~+1.1V GPU I/O POWER PG_GPUIO_EN Discrete enable
+1.5V_GPU +1.5V VRAM CORE POWER PG_1.5V_EN Discrete enable
+1.8V_GPU +1.8V GPU_CRE/LVDS/PLL POWER +1.5V_GPU Discrete enable
+1V +1V DP/PEG POWER PG_1V_EN Discrete enable
D D
Quanta Computer Inc.
PROJECT : ZY9B
Size Document Number Rev
1A
PWR Status & GPU PWR CRL & THRM
Date: Wednesday, June 24, 2009 Sheet 2 of 49
1 2 3 4 5 6 7 8
5 4 3 2 1
+3V U26
180ohm/1.5A 150mA(20mil) L38 *BKP1608HS181T_6_1.5A +3V
L35 BKP1608HS181T_6_1.5A +3V_CLK 1 80mA(20mil)
VDD_DOT +VDDIO_CLK L36 BKP1608HS181T_6_1.5A
5 VDD_27 VDD_SRC_I/O 15 +1.05V
C459 C453 C458 C461 C452 C451 C466 17 18
VDD_SRC VDD_CPU_I/O C464 C467 C462 C465
D 24 VDD_CPU D
4.7u/10V_8 4.7u/10V_8 .1u/16V_4 .1u/16V_4.1u/16V_4.1u/16V_4 .1u/16V_4 29 3 C308 may be can save
VDD_REF DOT_96 CLK_BUF_DREFCLK (10)
4 .1u/16V_4 .1u/16V_4 10u/Y5V_8 10u/Y5V_8
DOT_96# CLK_BUF_DREFCLK# (10)
CLK_SDATA 31
CLK_SCLK SDA R757 0_4
32 SCL 27M 6 27M_CLK (18) Place each 0.1uF cap as close as
7 R758 *0_4 possible to each VDD IO pin. Place
27M_SS For ATI suggest
the 10uF caps on the VDD_IO plane.
R234 33_4 CPU_SEL 30 10
(10) CLK_ICH_14M REF_0/CPU_SEL SRC_1/SATA CLK_BUF_PCIE_3GPLL (10)
SRC_1#/SATA# 11 CLK_BUF_PCIE_3GPLL# (10)
C449 33p_4 13
SRC_2 CLK_BUF_DREFSSCLK (10)
SRC_2# 14 CLK_BUF_DREFSSCLK# (10)
1
XTAL_IN 28
Y3 XTAL_IN +3V
14.318MHZ XTAL_OUT 27 16 R242 10K_4
XTAL_OUT *CPU_STOP#
2
C450 33p_4 2 20
VSS_DOT CPU_1 TP7
8 VSS_27 CPU_1# 19 TP8
C 9 VSS_SATA CPU_0 23 CLK_BUF_BCLK (10) C
12 VSS_SRC CPU_0# 22 CLK_BUF_BCLK# (10)
21 VSS_CPU
26 25 CK_PWRGD_R
VSS_REF CKPWRGD/PD#
33 GND
SLG8SP585V
+3V +3V
CPU_CLK select SMBus
+1.05V
CLK Enable
R237
R235 1K/F_4
B B
2
R223 2.2K_4
*10K_4 CK_PWRGD_R
3 1 CLK_SDATA CLK_SDATA (14,15,32)
(10,16,33) ICH_SMBDATA
3
Q17
CPU_SEL Q18 2N7002K
2N7002K
(40) VR_PWRGD_CK505# 2 R236
R228 100K/F_4
10K_4 C430 +3V
*10p/50V/COG_4
1
R238
2
2.2K_4
0 1
A
(10,16,33) ICH_SMBCLK 3 1 CLK_SCLK CLK_SCLK (14,15,32) Quanta Computer Inc. A
CPU_SEL CPU0/1=133MHz CPU0/1=100MHz Q19
(default) 2N7002K PROJECT : ZY9B
Size Document Number Rev
1A
Clock Generator
Date: Thursday, September 17, 2009 Sheet 3 of 49
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5 4 3 2 1
AUBURNDALE/CLARKSFIELD PROCESSOR (DMI,PEG,FDI) AUBURNDALE/CLARKSFIELD PROCESSOR (CLK,MISC,JTAG)
Processor Compensation Signals
U45A U45B
B26 R492 49.9/F_4 R549 20/F_4 H_COMP3 AT23
PEG_ICOMPI COMP3
PEG_ICOMPO A26 BCLK A16 CLK_CPU_BCLK (11)
MISC
MISC
A24 B27 R559 20/F_4 H_COMP2 AT24 B16 CLK_CPU_BCLK# (11)
(8) DMI_TXN0 DMI_RX#[0] PEG_RCOMPO COMP2 BCLK#
C23 A25 R493 750/F_4
(8) DMI_TXN1 DMI_RX#[1] PEG_RBIAS
CLOCKS
B22 PEG_RXN[0..15] (17) R122 49.9/F_4 H_COMP1 G16 AR30 BCLK_ITP_P (16)
(8) DMI_TXN2 DMI_RX#[2] COMP1 BCLK_ITP
A21 K35 PEG_RXN0 AT30 BCLK_ITP_N (16)
D (8) DMI_TXN3 DMI_RX#[3] PEG_RX#[0] BCLK_ITP# D
J34 PEG_RXN1 R548 49.9/F_4 H_COMP0 AT26
PEG_RX#[1] PEG_RXN2 COMP0
(8) DMI_TXP0 B24 DMI_RX[0] PEG_RX#[2] J33 PEG_CLK E16 CLK_PCIE_3GPLL (10)
D23 G35 PEG_RXN3 D16 CLK_PCIE_3GPLL# (10)
(8) DMI_TXP1 DMI_RX[1] PEG_RX#[3] PEG_CLK#
DMI
DMI
B23 G32 PEG_RXN4 R15