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5 4 3 2 1
Yukon Block Diagram
PCB Layer Stackup
L1: Signal 1
L2: VCC
Project code: 91.4BC01.001
DDR2 SODIMM L3: Inner Signal 2
PCB P/N : 48.4BC01.0SA
D DIMM1
8,9
DDR II 533/667/800
AMD G792
32
REVISION : 08226-SA
L4: Inner Signal 3
L5: GND
D
DDR2 SODIMM K8 Rev.G L6: Signal 4
DDR II 533/667/800 4,5,
DIMM2
8,9 AM2 Socket 6,7
CLK GEN. 14.318MHz
ICS 9LPRS502 CPU V_CORE
HyperTransport
OUT
16x16
IN
(RTM875T-605) 3
INPUT OUTPUT
S-Vedio 13 DCBATOUT VCC_CORE_S0
Mini Card ATI CRT15
802.11a/b/g/n 25 PCI-E x 1 SYSTEM DC/DC
RJ45 TXFM LAN
10/100 PCI-E x 1
RS690MC LCD14 INPUT
DCBATOUT
OUTPUT
1D2V_S0
C C
24 24 1D8V_S3
Marvell8040 23 10,11,12,13
25MHz SYSTEM DC/DC
INT. MIC Array PCI-E x 4 INPUT OUTPUT
DCBATOUT 5V_S5
3D3V_S5
Line In
27 Codec SYSTEM LDO
AZALIA
27 ALC268 INPUT OUTPUT
MIC In
26
ATI 1D8V_S3 0D9V_S3
AMP SYSTEM LDO
B 27
G1432Q
27 SB600 25MHz
32.768KHz
INPUT
3D3V_S5
OUTPUT
1D2V_S5
B
INT.SPKR 3D3V_S0 2D5V_S0
AZALIA
3D3V_S0 1D5V_S0
AMP SYSTEM LDO
27 G1412Q LPC BUS
27 INPUT OUTPUT
Line Out
5V_AUX_S5
(No-SPDIF) DCBATOUT
MODEM USB SPI I/F BIOS LPC 3D3V_AUX_S5
16,17,18,19,20 KBC
Winbond W25X80-VSS
RJ11 MDC Card 32.768KHz 30 DEBUG
22 22 WPC8773L CONN. 30 Battery Charger
28
USB x 2
SATA INPUTS OUTPUTS
CCD .3M/1.3M
USB
HDD 21 14 Touch INT. AD+ DCBATOUT
Pad 29 KB 29 BAT+
A A
USB MINI USB
Wistron Incorporated
2 Port
22
BlueTooth
22 21F, 88, Hsin Tai Wu Rd
Hsichih, Taipei
Title
CDROM SATA BLOCK DIAGRAM
Size Document Number Rev
21 A3
Yukon SA
Date: Thursday, July 03, 2008 Sheet 1 of 43
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
CHANGE HISTORY
Size Document Number Rev
A3 Yukon SA
Date: Thursday, July 03, 2008 Sheet 2 of 43
5 4 3 2 1
5 4 3 2 1
3D3V_S0 3D3V_CLK_VDD
1 R162 2
1
1
1
1
1
0R0603-PAD C279 3D3V_CLK_VDDA 3D3V_S0
C301 C302 C280 C282 C273 C306
2
2
2
2
2
D 2 R159 1 D
1
1
SC10U10V5ZY-1GP SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP SC2D2U10V3ZY-1GP 0R0603-PAD
SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP SC2D2U10V3ZY-1GP C274 C281
2
2
3D3V_S0
R181
1 2 3D3V_48MPWR_S0 SCD1U16V2ZY-2GP
SCD01U16V2KX-3GP
SC4D7U6D3V3KX-GP
1
1
C304 C305
2D2R3J-2-GP 3D3V_CLK_VDD
1- PLACE ALL SERIAL TERMINATION DY AMD-TL58 S3 issue change R169.R170 to 0R
RESISTORS CLOSE TO U800
2
2
SC1U16V3ZY-GP U32
54 VDDCPU VDDA 50
2- PUT DECOUPLING CAPS CLOSE TO U800 3000mA.80ohm 14 49 R163 261R2F-GP
VDDSRC GNDA
POWER PIN 23 VDDSRC
28 56 CPUCLK_R R169 1 2 47D5R2F-1-GP
VDDSRC CPUCLK8T0 CPUCLK 6
44 55 CPUCLK#_R R170 1 2 47D5R2F-1-GP
VDDSRC CPUCLK8C0 CPUCLK# 6
5 VDD48 CPUCLK8T1 52
3D3V_S0 39 51
R182 2 0R0603-PAD VDDATIG CPUCLK8C1
1 2 VDDREF
60 16 1 4SRN33J-5-GP-U
VDDHTT SRCCLKT6 RN38 NBSRC_CLK 12
SRCCLKC6 17 2 3 NBSRC_CLK# 12
53 41 NBSRC_CLK_R
C303 GNDCPU ATIGCLKT0 NBSRC_CLK#_R
15 GNDSRC ATIGCLKC0 40
SC2D2U10V3ZY-1GP 22 37
GNDSRC ATIGCLKT1
29 GNDSRC ATIGCLKC1 36
C Parallel Resonance Crystal 45
8
GNDSRC ATIGCLKT2 35
34 C
C294 1 SC33P50V2JN-3GP GND48 ATIGCLKC2
2 38 GNDATIG ATIGCLKT3 30
1 GNDREF ATIGCLKC3 31 2 3 SRN33J-5-GP-U CLK_PCIE_MINI1 25
1
1
X3 58 18 1 RN41 4
GNDHTT SRCCLKT5 CLK_PCIE_MINI1# 25
X-14D31818M-44GP
DY R172
1MR2J-L2-GP SRCCLKC5 19
CLK_PCIE_MINI_R
3 X1 SRCCLKT4 20 2 3 SRN33J-5-GP-U SBSRC_CLK 16
C283 21 CLK_PCIE_MINI#_R 1 RN43 4 SBSRC_CLK# 16
2
SRCCLKC4 SBSRC_CLK_R
1 2 4 24
2
X2 SRCCLKT3 SBSRC_CLK#_R
SRCCLKC3 25
SC27P50V2JN-2-GP R180 SRCCLKT2 26
3D3V_S0 27
3D3V_S0 SRCCLKC2 CLK_PCIE_LAN_R
1 2 11 RESET_IN# SRCCLKT0 47 1 4 SRN33J-5-GP-U CLK_PCIE_LAN 23
61 46 CLK_PCIE_LAN#_R 2 RN37 3 CLK_PCIE_LAN# 23
NC#61 SRCCLKC0 SBLINK_CLK_R
10KR2J-3-GP SRCCLKT1 43
1
42 SBLINK_CLK#_R 1 4SRN33J-5-GP-U
SRCCLKC1 RN39 SBLINK_CLK 12
10KR2J-3-GPDY SRCCLKT7 12 2 3 SBLINK_CLK# 12
13 DY 1 R168 2
R184 SRCCLKC7 10KR2J-3-GP
9 57 CLK_REQA# 1 TP33 3D3V_CLK_VDD
9,19 SMBC0_SB
2
CLK_REQB# SMBCLK CLKREQA#
9,19 SMBD0_SB 10 SMBDAT CLKREQB# 32 1 DY 2 R178 CLK_REQB# TPAD28
33 0R2J-2-GP
CLKREQC# R183 2
DY 1
48 7 10KR2J-3-GP TP40 TPAD30
IREF 48MHZ_1 CLK48_USB_R 1
Ioh = 5 * Iref DY 48MHZ_0 6 2 CLK48_USB 19
8
7
6
5
R171
(2.32mA) 475R2F-L1-GP R179 33R2F-3-GP RN33
FS1/REF1 63
Voh = 0.71V @ 60 ohm 1% 64 SRN10KJ-6-GP
FS0/REF0
FS2/REF2 62
HTTCLK0 59
B B
06/09/2006
1
2
3
4
ICS951462YGLFT-GP
Check SLGO EXT CLK XSL84606 (56 Pin) or XSL84605 (64 Pin) pin to pin compatable with ICS951464
FS1 R165 2 1 33R2F-3-GP
FS0 R551 33R2F-3-GP SB_OSC_CLK 19
2 DY 1 CLK14_SIO 28
FS2 1 R166 2 33R2F-3-GP
EXT CLK FREQUENCY SELECT TABLE(MHZ) SBLINK_CLK# 2 3
NB_OSC 12
SBLINK_CLK 1 RN36 4SRN49D9F-GP HTREF_CLK_R R1672 1
33R2F-3-GP HTREF_CLK 12
FS2 FS1 FS0 CPU SRCCLK HTT PCI USB COMMENT
[2:1] DY
SBSRC_CLK# 1 4 CLK48_USB
SBSRC_CLK 2 RN46 3SRN49D9F-GP
1
0 0 0 Hi-Z 100.00 Hi-Z Hi-Z 48.00 Reserved
1
R161
NBSRC_CLK# DY 49D9R2F-GP EC61
0 0 1 X 100.00 X/3 X/6 48.00 Reserved 2 3
NBSRC_CLK 1 RN35 SRN49D9F-GP
SCD1U16V2ZY-2GP
4 DY
2
0 1 0 180.00 100.00 60.00 30.00 48.00 Reserved
2
CLK_PCIE_MINI1# DY
0 1 1 220.00 100.00 36.56 73.12 48.00 Reserved 1 4
CLK_PCIE_MINI1 2 RN44 3SRN49D9F-GP EMI REQUEST
1 0 0 100.00 100.00 66.66 33.33 48.00 Reserved
CLK_PCIE_LAN DY
1 0 1 133.33 100.00 66.66 33.33 48.00 Reserved 1 4
CLK_PCIE_LAN# 2 RN34 3SRN49D9F-GP
1 1 1 200.00 100.00 66.66 33.33 48.00 Normal ATHLON64 operation
A DY A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
CLKGEN_ICS951412
Size Document Number Rev
A3 SA
Yukon
Date: Thursday, July 03, 2008 Sheet 3 of 43
5 4 3 2 1
5 4 3 2 1
D D
U52A
1 OF 9
NB0HTTCLKOUT1 N6 AD5 CPUHTTCLKOUT1 CPUHTTCLKOUT1 10
10 NB0HTTCLKOUT1 NB0HTTCLKOUTJ1 L0_CLKIN_H1 L0_CLKOUT_H1 CPUHTTCLKOUTJ1
10 NB0HTTCLKOUTJ1 P6 L0_CLKIN_L1 L0_CLKOUT_L1 AD4 CPUHTTCLKOUTJ1 10
NB0HTTCLKOUT0 N3 AD1 CPUHTTCLKOUT0 CPUHTTCLKOUT0 10
10 NB0HTTCLKOUT0 NB0HTTCLKOUTJ0 L0_CLKIN_H0 L0_CLKOUT_H0 CPUHTTCLKOUTJ0
1D2V_LDO_S0 10 NB0HTTCLKOUTJ0 N2 L0_CLKIN_L0 L0_CLKOUT_L0 AC1 CPUHTTCLKOUTJ0 10
RN64
1 4 CPUHTTCTLIN1 V4 Y6 TP123 TPAD28
2 3 CPUHTTCTLINJ1
NB0HTTCTLOUT
V5
U1
L0_CTLIN_H1
L0_CTLIN_L1
L0_CTLOUT_H1
L0_CTLOUT_L1 W6
W2 CPUHTTCTLOUT0
TP124 TPAD28 ?
10 NB0HTTCTLOUT L0_CTLIN_H0 L0_CTLOUT_H0 CPUHTTCTLOUT0 10
SRN51J-GP NB0HTTCTLOUTJ V1 W3 CPUHTTCTLOUTJ0 CPUHTTCTLOUTJ0 10
C 10 NB0HTTCTLOUTJ L0_CTLIN_L0 L0_CTLOUT_L0 C
NB0CADOUT15 U6 Y5 CPUCADOUT15
NB0CADOUTJ15 L0_CADIN_H15 L0_CADOUT_H15 CPUCADOUTJ15
V6 L0_CADIN_L15 L0_CADOUT_L15 Y4 CPUCADOUT[15..0] 10
NB0CADOUT14 T4 AB6 CPUCADOUT14 CPUCADOUTJ[15..0] 10
NB0CADOUTJ14 L0_CADIN_H14 L0_CADOUT_H14 CPUCADOUTJ14
10 NB0CADOUT[15..0] T5 L0_CADIN_L14 L0_CADOUT_L14 AA6
NB0CADOUT13 R6 AB5 CPUCADOUT13
10 NB0CADOUTJ[15..0] NB0CADOUTJ13 L0_CADIN_H13 L0_CADOUT_H13 CPUCADOUTJ13
T6 L0_CADIN_L13 L0_CADOUT_L13 AB4
NB0CADOUT12 P4 AD6 CPUCADOUT12
NB0CADOUTJ12 L0_CADIN_H12 L0_CADOUT_H12 CPUCADOUTJ12
P5 L0_CADIN_L12 L0_CADOUT_L12 AC6
NB0CADOUT11 M4 AF6 CPUCADOUT11
NB0CADOUTJ11 L0_CADIN_H11 L0_CADOUT_H11 CPUCADOUTJ11
M5 L0_CADIN_L11 L0_CADOUT_L11 AE6
NB0CADOUT10 L6 AF5 CPUCADOUT10
NB0CADOUTJ10 L0_CADIN_H10 L0_CADOUT_H10 CPUCADOUTJ10
M6 L0_CADIN_L10 L0_CADOUT_L10 AF4
NB0CADOUT9 K4