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5 4 3 2 1
Model Name: 945GCM-S2L Revision 1.02
SHEET TITLE SHEET TITLE
01 COVER SHEET 28 REAR AUDIO JACK
D
02 BLOCK DIAGRAM 29 DISCRETE POWER D
03 BOM & PCB MODIFY HISTORY 30 VCORE PWM_ISL6312
04 P4_LGA775_A 31 ATX, OTHERS POWER
05 P4_LGA775_B 32 REALTEK RTL8111C/8101E/8102E
06 P4_LGA775_C 33 FRONT PANEL
07 P4_LGA775_D,E,F,G
08 GMCH-LAKEPORT_HOST
09 GMCH-LAKEPORT_DDRII
C C
10 GMCH-LAKEPORT_PCI E, DMI
11 GMCH-LAKEPORT_INT VGA
12 GMCH-LAKEPORT_GND
13 GMCH-LAKEPORT_PWR
14 DDRII CHANNEL A 1
15 DDRII CHANNEL B 2
16 DDRII TERMINATION
17 PCI EXPRESS*16 SLOT
B B
18 ICH7 PCI, USB, DMI, LAN
19 ICH7 IDE, GPIO, SATA, CTRL
20 ICH7 VCC, GND
21 GB/CK505-OC CLOCK.
22 PCI SLOT 1,2,PCIEX1
23 IDE/FLOPPY
24 ITE 8718 GBIX
25 COM_LPT
A A
26 BIOS,CI,HWM,KB/MS
om
27 AZALIA ALC662
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Gigabyte Technology
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Title
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Cover Sheet
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Size Document Number Rev
945GCM-S2L
in
Custom 1.02
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Date: Tuesday, October 02, 2007 Sheet 1 of 33
he
5 4 3 2 1
5 4 3 2 1
BLOCK DIAGRAM
INTEL Pentium4
LGA775
D
CLOCK GENERATOR D
VCORE = 1.4V
VCC3
CKVDD = 3.3V
PCI EXPRESS X16
VDDQ = 1.5V (AGP POWER 4X)
CHANNEL A
VCC3 = 3.3V
+12V = 12V DDRII DIMM X 1
3VDUAL = 3.3V
VCC = 5V GMCH
LAKEPORT(945GC) MAA0~14
1.8VSTR = 1.8V(MEMORY,SUSPEND POWER)
VTT_DDR = 0.9V
PAGE 14,15
MAA_CPC1~5
MAB_CPC1~5
MDD0~63 CHANNEL B
-DQSD0~7
DM0~7
DDRII DIMM X 1
1.8VSTR = 1.8V(MEMORY,SUSPEND POWER)
VCORE = 1.75V / SLEEP : 1.3V VTT_DDR = 0.9V
2_5VSTR = 2.5V(MEMORY) PAGE 16,17
VDDQ = 1.5V (AGP POWER 4X, HUBLINK)
C C
PCI EXPRESS X1
IDE Primary
ICH7
VCC = 5V PAGE 28
USB PORTS 0~7 SERIAL ATA
VCC25 = 2.5V(I/O,MEMORY/I,VLINK/I)
VCC = 5V 3VDUAL = 3.3V(SUSPEND POWER)
5VSB = 5V VCC3 = 3.3V
5VUSB = 5V RTCVDD = 3.3V VCC = 5V PAGE 21
PCI BUS
B FWH/HWMO B
PCI SLOT 1,2
VCC = 5V
+12 = 12V VCC3 = 3V PAGE 27
-12 = -12V
VCC = 5V
VCC3 = 3V
3VDUAL = 3V
REALTEK LPC BUS
AZALIA ALC662 RTL8111C/8101E/8102E LPC I/O ITE8718GB
+12V = 12V
VCC3 = 3.3V VCC = 5V
VCC = 5V 5VSB = 5V
AVDD = 5V PAGE 33 VBAT = 3V PAGE 39
A AUDIO PORTS : FRONT PANEL /CPU FAN I/O PORTS : A
FRONT AUDIO LIN_ OUT LINE_IN VCC = 5V
5VSB = 5V
+12 = 12V
PVCC = 5V
COMA LPT PS2 FDD
CD_IN MIC PAGE 34,35 PAGE 29,40
Gigabyte Technology
Title
BOM & PCB MODIFY HISTORY
Size Document Number Rev
Custom 945GCM-S2L 1.02
Date: Tuesday, October 02, 2007 Sheet 2 of 33
5 4 3 2 1
5 4 3 2 1
Model Name:945GCM-S2L Circuit or PCB layout change
for next version
Version: 1.02
DATE Change Item Reason
D D
Component value change
history 2007/09/27
Data Change Item Reason
2007/06/20 COMA+LPT PORT
2007/07/23 LAN RTL8111C/8101E/8102E CO-LAYOUT
2007/07/25 RN150 VCC3 LOADING FIX PWR AcBel(ATX-400C-A2ADB)
2007/08/02 FIX POWER ISSUE/LAN RTL8111C EBOM:9M945CM2L-00-10B
2007/08/15 R1.02:VIN 470UX3(FP)+RTL8111C OC GPIO65 PBOM:9M945CM2L-00-10C
2007/08/28 ADD GP65 CONTROL ISOLATEB FOR O.C FPBOM:9M945CM2L-00-10D
C 2007/09/10 CHANGE RTL8111C O.C VERSION PBOM:9M945CM2L-00-10E C
2007/09/27 FIX POWER SEQUENCE ISSUE PBOM:9M945CM2L-00-10F
B B
A A
om
Gigabyte Technology
l.c
ai
Title
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BOM & PCB MODIFY HISTORY
ho
Size Document Number Rev
945GCM-S2L
f@
Custom 1.02
in
xa
Date: Tuesday, October 02, 2007 Sheet 3 of 33
5 4 3 2 1
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5 4 3 2 1
R422
49.9/6/1
GTLREF1
VTT_OR
VCORE
R424 C262
100/6/1 1u/6/Y5V/10V/Z
R1
124/6/1
BC5 BC6 BC7 BC8 GTLREF0
VTT_OR
10u/12/X7R/6.3V/K 10u/12/X7R/6.3V/K 10u/12/X7R/6.3V/K 10u/12/X7R/6.3V/K
D D
R2 C1
249/6/1 1u/6/Y5V/10V/Z
VCORE
D-STEPPING(960 CPU)
BC1 BC2 BC3 BC4
10u/12/X7R/6.3V/K 10u/12/X7R/6.3V/K 10u/12/X7R/6.3V/K 10u/12/X7R/6.3V/K R3 62/6 -IERR
VTT_OR
R4 62/6 -BR0
VTT_OL
R5 62/6 -CPURST
VTT_OR
footprint:LGA775-3A9
RN1 62/8P4R/6
HA[3..16] LGA775A 7 8
[8] HA[3..16]
HA3 L5 D2 -HADS 5 6 TESTHI9
C A<3>* ADS* -HADS [8] C
A<4>* LGA775
HA4 P6 C2 -BNR 3 4 TESTHI8
BNR* -BNR [8]
HA5 M5 D4 -HIT 1 2 TESTHI10
A<5>* HIT* -HIT [8] VTT_OL
HA6 L4 A<6>* (1/8) RSP* H4 TP_CPU16
HA7 M4 G8 -BPRI 1.3K/4/1
A<7>* BPRI* -BPRI [8]
HA8 R4 B2 -DBSY R2873 R2874 0/6/X GTLREF0
A<8>* DBSY* -DBSY [8]
HA9 T5 C1 -DRDY +12V
A<9>* DRDY* -DRDY [8]
3
HA10 U6 E4 -HITM
A<10>* HITM* -HITM [8]
HA11 T4 AB2 -IERR
A<11>* IERR* D GTLREF2 [6]
HA12 U5 P3 -HINIT R2876 Q321
A<12>* INIT* -HINIT [19]
HA13 U4 C3 -HLOCK 1K/4/1 2N7002/SOT23/25pF/5
A<13>* LOCK* -HLOCK [8] G S
HA14 V5 E3 -HTRDY C2
A<14>* TRDY* -HTRDY [8] VCC3
HA15 V4 AD3 TP_CPU17 33P/4/NPO/50V/J
HA16 A<15>* BINIT* -DEFER
2
1
W5 A<16>* DEFER* G7 -DEFER [8]
3
TP_CPU18 N4 RSVD_3
P5 AB3 Q322
TP_CPU19 RSVD_4 MCERR*
-HREQ0 K4 R2877 MMBT2222A/SOT23/600mA/40
[8] -HREQ0 REQ<0>*
-HREQ1 J5 U2 TP_CPU1 1K/4/1
[8] -HREQ1 REQ<1>* AP<0>* SOT23
-HREQ2 M6 U3 TP_CPU2
[8] -HREQ2 REQ<2>* AP<1>* [24] GTLREF_UV0
-HREQ3
2
1
[8] -HREQ3 K6 REQ<3>*
-HREQ4 J6 F3 -BR0 R2878
[8] -HREQ4 REQ<4>* BR<0>* -BR0 [8]
HA[17..31] -HADSTB0 R6 G3 TESTHI8 576/6/1
[8] HA[17..31] [8] -HADSTB0 ADSTB<0>* TESTHI_8
HA17 AB6 G4 TESTHI9 GTLREF1
HA18 A<17>* TESTHI_9 TESTHI10 +12V
W6 A<18>* TESTHI_10 H5
3
B HA19 Y6 B
HA20 A<19>*
Y4 A<20>* D GTLREF3 [6]
HA21 AA4 J16 TP_CPU3 R2881 Q323
HA22 A<21>* DP<0>* 1K/4/1 2N7002/SOT23/25pF/5
AD6 A<22>* DP<1>* H15 TP_CPU4 G S
HA23 AA5 H16 TP_CPU5
HA24 A<23>* DP<2>* VCC3
AB5 A<24>* DP<3>* J17 TP_CPU6
HA25
2
1
AC5 A<25>*
3
HA26 AB4 H1 GTLREF0
HA27 A<26>* GTLREF0 GTLREF1 Q324
AF5 A<27>* GTLREF1 H2
HA28 AF4 E24 MCH_GTLREF R2882 MMBT2222A/SOT23/600mA/40
A<28>* GTLREF2 MCH_GTLREF [8]
HA29 AG6 H29 1K/4/1
HA30 A<29>* GTLREF_SEL SOT23
AG4 A<30>* [24] GTLREF_UV1
HA31
2
1
AG5 A<31>*
AH4 G23 -CPURST
A<32>* RESET* -CPURST [8]
AH5 A<33>*
AJ5 A<34>*
AJ6 B3 -RS0 C4
A<35>* RS<0>* -RS0 [8]
AC4 F5 -RS1 22p/4/NPO/50V/J
RSVD_1 RS<1>* -RS1 [8]
AE4 A3 -RS2
RSVD_2 RS<2>* -RS2 [8]
-HADSTB1 AD5
[8] -HADSTB1 ADSTB<1>*
CPU-SK/775/S/GF
A A
Gigabyte Technology
Title
P4_LGA775-A
Size Document Number Rev
B 945GCM-S2L 1.02
Date: Tuesday, October 02, 2007 Sheet 4 of 33
5 4 3 2 1
5 4 3 2 1
RN2 470/8P4R/6
7 8 FSBSEL0
LGA775B VTT_GMCH
HD[0..15] 5 6 FSBSEL22
[8] HD[0..15] HD[32..47] [8]
HD0 B4 G16 HD32 3 4 FSBSEL1
D<0>* D<32>*
HD1 C5 D<1>* LGA775 D<33>* E15 HD33 1 2
HD2 A4 E16 HD34
D<2>* D<34>*
HD3 C6 D<3>* (2/8) D<35>* G18 HD35
D HD4 A5 G17 HD36 D
HD5 D<4>* D<36>* HD37 RN5 62/8P4R/6
B6 D<5>* D<37>* F17
HD6 B7 F18 HD38 7 8 -BPM0
D<6>* D<38>* VTT_OR
HD7 A7 E18 HD39 5 6 -BPM1
HD8 D<7>* D<39>* HD40 -BPM5
A10 D<8>* D<40>* E19 3 4
HD9 A11 F20 HD41 RN61 2 -BPM4
HD10 D<9>* D<41>* HD42 -BPM3
B10 D<10>* D<42>* E21 7 8
HD11 C11 F21 HD43 5 6 -BPM2
HD12 D<11>* D<43>* HD44 TDI
D8 D<12>* D<44>* G21 3 4
HD13 B12 E22 HD45 C14 1 2 TMS
HD14 D<13>* D<45>* HD46 1u/6/Y5V/10V/Z 62/8P4R/6
C12 D<14>* D<46>* D22
HD15 D11 G22 HD47 R35 62/6 TDO
-DBI0 D<15>* D<47>* -DBI2
[8] -DBI0 A8 DB1<0>* DBI<2>* D19 -DBI2 [8]
STBN0 C8 G20 STBN2 R27 470/6 VR_RDY
[8] STBN0 DSTBN<0>* DSTBN<2>* STBN2 [8]
HD[16..31] STBP0 B9 G19 STBP2
[8] HD[16..31] [8] STBP0 DSTBP<0> DSTBP<2> STBP2 [8] HD[48..63] [8]
HD16 G9 D20 HD48 R36 62/6 -TRST
HD17 D<16>* D<48>* HD49 R37 62/6 TCK
F8 D<17>* D<49>* D17
HD18 F9 A14 HD50
HD19 D<18>* D<50>* HD51
E9 D<19>* D<51>* C15
HD20 D7 C14 HD52
HD21 D<20>* D<52>* HD53 FSBSEL0 R39 8.2K/4 BSEL0
E10 D<21>* D<53>* B15 [21] FSBSEL0 BSEL0 [11]
HD22 D10 C18 HD54 FSBSEL1 R40 8.2K/4 BSEL1
D<22>* D<54>* [21] FSBSEL1 BSEL1 [11]
HD23 F11 B16 HD55 FSBSEL2 R41 8.2K/4 BSEL2
D<23>* D<55>* [21] FSBSEL2 BSEL2 [11]
HD24 F12 A17 HD56
HD25 D<24>* D<56>* HD57
D13 D<25>* D<57>* B18
HD26 E13 C21 HD58
HD27 D<26>* D<58>* HD59
G13 D<27>* D<59>* B21
C HD28 F14 B19 HD60 C
HD29 D<28>* D<60>* HD61
G14 D<29>* D<61>* A19
HD30 F15 A22 HD62
HD31 D<30>* D<62>* HD63
G15 D<31>* D<63>* B22
-DBI1 G11 C20 -DBI3
[8] -DBI1 DB1<1>* DBI<3>* -DBI3 [8]
STBN1 G12 A16 STBN3
[8] STBN1
[8] STBP1
STBP1 E12
DSTBN<1>*
DSTBP<1>
DSTBN<3>*
DSTBP<3> C17 STBP3
STBN3 [8]
STBP3 [8]
CPU
NA FSB FSA
CPU-SK/775/S/GF
FSBSEL3 FSBSEL1 FSBSEL0 Clock
1 0 1 100MHz X
0 0 1 133MHz
0 1 1 166MHz
0 1 0 200MHz
VTT_GMCH
0 0 0 266MHz
LGA775D
A29
TCK AE1 TCK LGA775 VTT_1
VTT_2 B25
TDI AD1 B29
TDI
B TDO AF1 TDO (4/8) VTT_3
VTT_4 B30 B
TMS AC1 C29
-TRST TMS VTT_5
AG1 TRST* VTT_6 A26
-BPM0 AJ2 B27
-BPM1 BPM<0>* VTT_7
AJ1 BPM<1>* VTT_8 C28
-BPM2 AD2 A25
-BPM3 BPM<2>* VTT_9
AG2 BPM<3>* VTT_10 A28
-BPM4 AF2 A27
-BPM5 BPM<4>* VTT_11
AG3 BPM<5>* VTT_12 C30
-SYS_RST AC2 A30
[19,21,33] -SYS_RST DBR* VTT_13
AK3 ITPCLK<0> VTT_14 C25
AJ3 ITPCLK<1> VTT_15 C26
FSBSEL0 G29 C27
FSBSEL1 BSEL<0> VTT_16
H30 BSEL<1> VTT_17 B26
FSBSEL2 FSBSEL22 G30 D27
BSEL<2> VTT_18
N5 SPARE0 VTT_19 D28
C9 SPARE1 VTT_20 D25
TP_CPU7 E7 D26
R1914 R1893 SPARE2 VTT_21
AE6 SPARE4 VTT_22 B28
0/4/SHT/X 1K/4/1/X D16 D29
NC_DSS2 VTT_23
A20 NC_DSS3 VTT_24 D30
TP_CPU8 E23 AM6 VR_RDY
NC VTT_PWRGD VR_RDY [30]
VTT_OUT_1 AA1 VTT_OR
VTT_OUT_2 J1 VTT_OL
FOR FIX FSB1333 CPU VTT_SEL F27
F23 TP_CPU9
EXTBGREF
SFRANAD D14
A SFRANAC E6