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5 4 3 2 1
01
Clapton (EL7) AIO Block Diagram
Diamondville SC VID[0:6] CPU VCORE
D D
P 25
BGA437
22X22mm +/- CPU_CLK
P3,4
+/- HCLK Clock Gengerator
FSB/533 P 2
18.5" LVDS SDVO 82945GSE(GMCH)
CH7308 DDR2(400/533) Single-SODIMM
C
Panel
P 14
P 24 FCBGA998 P 13 C
27X27 mm
P 5,6,7,8,9
Giga Ethernet PCI-E x2 DMI
RJ-45
RTL8111DL
P 17
P 17 ODD P 20
USB 82801GBM SATA
4 in1 Card Reader HDD/SSD 20
P
RTS5159 P 19 (ICH7M)
BGA652
B B
Speaker HDA CODEC HD Audio USB
P23 ALC269 Camera Conn. Camera
P 23
31x31 mm P 14
Module
USB
Ext HP USB PORT X 5 P 10,11,12 USB/PCI-E WLAN
P 16
LPC(33 MHz) P 21 WLAN Module
Ext Mic EC
ITE 8502 22
P
Line
A A
out
PS/2 SPI Quanta Computer Inc.
K/B Flash PROJECT : EL7
Size Document Number Rev
P 18 P 22 1A
Block Diagram
Date: Friday, April 24, 2009 Sheet 1 of 34
5 4 3 2 1
5 4 3 2 1
Clock Generator +3V
02
+1.05V_VDD PM_STPPCI# R136 2.2K_4
+3V C371 L19 +1.05V
L18 0.1u/10V_4 PBY160808T-301Y-N_6 PM_STPCPU# R139 2.2K_4
PBY160808T-301Y-N_6 C372 C382 C383 C376 C380 C384 C385 C381 C379
0.1u/10V_4
C368 10u/10V_8 10u/10V_8 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 NEW_CLKREQ#_R R143 10K_4
10u/10V_8
D C378 U6 D
0.1u/10V_4 VDD_CK_VDD_PCI 9 55
C386 VDD_CK_VDD_48 VDD_PCI IO_VOUT
16 VDD_48
0.1u/10V_4 VDD_CK_VDD_PCI 23 7 SMBCK1
C370 VDD_CK_VDD_REF VDD_PLL3 SCLK SMBDT1 LCLK_EC C190 *33p/50V_4
4 VDD_REF SDA 6
0.1u/10V_4 CK505
C374 VDD_CK_VDD_PCI 46 45 PM_STPPCI#
VDD_SRC SRC5/PCI_STOP# PM_STPPCI# (12)
0.1u/10V_4 VDD_CK_VDD_CPU 62 44 PM_STPCPU# To SB CLKUSB_48 C369 15p/50V_4
VDD_CPU SRC5#/CPU_STOP# PM_STPCPU# (12)
+1.05V_VDD
C377 19 61 1 2 RP2 CLK_CPU_BCLK (3)
VDD_96_IO CPU0 14M_ICH
27 VDD_PLL3_IO CPU0# 60 3 4 *0X2_4 CLK_CPU_BCLK# (3) To CPU C187 *33p/50V_4
10u/10V_8 33 VDD_SRC_IO_1
52 VDD_SRC_IO_3 CPU1 58 1 2 RP4 CLK_MCH_BCLK (5)
43 VDD_SRC_IO_2 CPU1# 57 3 4 *0X2_4 CLK_MCH_BCLK# (5) To NB PCLK_ICH C189 10p/50V_4
56 VDD_CPU_IO
SRC8/ITP 54
53 Modified 2009/01/08 by Jimmy Hsu To 3G LCLK_EC C184 *33p/50V_4
SRC8#/ITP#
PCLK_DEBUG R104 10_4 PCLK_DEBUG_R 8 42 1 2 RP9 CLK_PCIE_3GPLL# (7)
(21) PCLK_DEBUG PCI0/CR#_A SRC10#
SRC10 41 3 4 *0X2_4 CLK_PCIE_3GPLL (7) To NB PCLK_DEBUG C183 *33p/50V_4
PCLK_PCM_R 10 ES2-0714-2
T25 PCI1/CR#_B
40 CLK_MCH_OE#_R R145 475/F_4
SRC11/CR#_H MCH_CLKREQ# (7)
PCLK_OZ129_R 11 39 NEW_CLKREQ#_R R144 475/F_4 CLK_48M_CR C375 *33p/50V_4
PCI2/TME SRC11#/CR#_G CLKREQ_WLAN# (21)
PCI_CLK_SIO_R 12 37 3 4 RP8 PE2CLK+ (21)
T26 PCI3 SRC9
C 38 1 2 *0X2_4 PE2CLK- (21) To WLAN CLKUSB_48 C366 *33p/50V_4 C
R109 10_4 PCLK_8502_R SRC9#
(22) LCLK_EC 13 PCI4/27M_SEL
SRC7/CR#_F 51 CLK To 3G
PCLK_ICH R108 33_4 PCLK_ICH_R 14 50 Modified 2009/01/08 by Jimmy Hsu
(11) PCLK_ICH PCIF5/ITP_EN SRC7#/CR#_E
SEL2 SEL1 SEL0 Frequence select
CG_XIN 3 48
XTAL_IN SRC6
CG_XOUT SRC6# 47 FSC FSB FSA CPU SRC PCI
2 XTAL_OUT
R127 47_4 34 3 4 RP7 PE1CLK+ (17) 1 0 1 100 100 33
(19) CLK_48M_CR R120 47_4 FSA SRC4
(12) CLKUSB_48 17 USB_48/FSA SRC4# 35 1 2 *0X2_4 PE1CLK- (17) To LAN
CLK_BSEL0 R114 2.2K_4 0 0 1 133 100 33 Default
CLK_BSEL1 FSB 64 31 3 4 RP6 CLK_PCIE_ICH (11)
CLK_BSEL2 R103 10K_4 FSB/TEST/MODE SRC3/CR#_C
SRC3#/CR#_D 32 1 2 *0X2_4 CLK_PCIE_ICH# (11) To SB 0 1 1 166 100 33
R105 33_4 FSC 5
(12) 14M_ICH R106 33_4 REF0/FSC/TESTSEL
(24) 14M_CH7308 65 VSS_BODY SRC2/SATA 28 3 4 RP5 CLK_PCIE_SATA (10) 0 1 0 200 100 33
15 VSS_PCI SRC2#/SATA# 29 1 2 *0X2_4 CLK_PCIE_SATA# (10) To SB
C193 18 0 0 0 266 100 33
27p/50V_4 CG_XIN VSS_48
22 VSS_IO SRC1/SE1 24 3 4 RP3 DREFSSCLK (7)
26 VSS_PLL3 SRC1#/SE2 25 1 2 *0X2_4 DREFSSCLK# (7) To NB 1 0 0 333 100 33
2
Y3 59 VSS_CPU
CL=20p 30 VSS_SRC1 SRC0/DOT96 20 3 4 RP1 DREFCLK (7) 1 1 0 400 100 33
14.318MHZ 36 21 1 2 *0X2_4 DREFCLK# (7) To NB
C194 VSS_SRC2 SRC0#/DOT96#
49 1 1 1 Reserved
1
27p/50V_4 CG_XOUT VSS_SRC3
1 VSS_REF CKPWRGD/PWRDWN# 63 VR_PWRGD_CK410 (12)
ICS9LPRS365BKLFT +1.05V R285 56_4
B B
ICS9LPRS365BKLFT To NB
+3V R98 10K_4 PCLK_OZ129_R R288 *0_4 CLK_BSEL0 R284 1K_4
(3) CPU_BSEL0 MCH_BSEL0 (7)
ICS9LPRS365 RTM875T-606 R283 *1K_4
(ALPRS365K13) (AL000875K06) PULL HIGH PULL DOWN R99 *10K_4
+1.05V R122 *1K_4
PCI2/TME
Pin 11 PCI2/TME internal PD NO OVERCLOCKING (default) NORMAL RUN
+3V R92 *10K_4 LCLK_EC R124 *0_4 CLK_BSEL1 R123 1K_4
HIGH 27MHz (3) CPU_BSEL1 MCH_BSEL1 (7)
Pin 13 PCI-4/27M_SEL PCI-4/27M_SEL PIN 24/25 IS 27MHz PIN 20/21 (default) LOW SRC R121 0_4
internal PD IS SRC/DOT R96 10K_4
+1.05V R97 *1K_4
PCIF-5/ITP_EN
Pin 14 PCIF-5/ITP_EN internal PD PIN 53/54 IS CPUITP PIN 53/54 IS SRC8 (default) R95 *10K_4 PCLK_ICH
+3V
R94 *0_4 CLK_BSEL2 R90 1K_4
(3) CPU_BSEL2 MCH_BSEL2 (7)
R101 10K_4 R93 *0_4
+3V :ICS9LPRS365BGLFT QCI:ALPRS365K13 +3V
Clock Gen I2C :SLG8SP512TTR: QCI:AL8SP512K05
A A
R286 R287
4.7K_4 4.7K_4
2
2
Q9 Q10
(12) SMBDT 3 1 SMBDT1
SMBDT1 (13,21) (12) SMBCK 3 1 SMBCK1
SMBCK1 (13,21) Quanta Computer Inc.
2N7002E 2N7002E PROJECT : EL7
Size Document Number Rev
1A
CLOCK GENERATOR
Date: Friday, April 24, 2009 Sheet 2 of 34
5 4 3 2 1
5 4 3 2 1
U8A CPU U8B
03
(5) H_A#[31:3] (5) H_D#[63:0] H_D#[63:0] (5)
H_A#3 P21 V19 H_D#0 Y11 R3 H_D#32
A[3]# ADS# H_ADS# (5) D[0]# D[32]#
H_A#4 H20 Y19 H_D#1 W10 R2 H_D#33
A[4]# BNR# H_BNR# (5) D[1]# D[33]#
H_A#5 N20 U21 H_D#2 Y12 P1 H_D#34
A[5]# BPRI# H_BPRI# (5) D[2]# D[34]#
H_A#6 R20 H_D#3 AA14 N1 H_D#35
A[6]# D[3]# D[35]#
0
GROUP
GROUP
ADDR
ADDR
DATA GRP 0
H_A#7 J19 T21 H_D#4 AA11 M2 H_D#36
A[7]# DEFER# H_DEFER# (5) D[4]# D[36]#
H_A#8 N19 T19 H_D#5 W12 P2 H_D#37
A[8]# DRDY# H_DRDY# (5) D[5]# D[37]#
H_A#9 G20 Y18 H_D#6 AA16 J3 H_D#38
DATA GRP 2
A[9]# DBSY# H_DBSY# (5) D[6]# D[38]#
D
H_A#10 M19 H_D#7 Y10 N3 H_D#39 D
H_A#11 A[10]# H_D#8 D[7]# D[39]# H_D#40
H21 A[11]# BR0# T20 H_BREQ#0 (5) Y9 D[8]# D[40]# G3
H_A#12 L20 H_D#9 Y13 H2 H_D#41
A[12]# D[9]# D[41]#
CONTROL
H_A#13 M20 F16 IERR# R237 56_4 H_D#10 W15 N2 H_D#42
A[13]# IERR# +1.05V D[10]# D[42]#
H_A#14 K19 V16 H_INIT#R R37 H_D#11 AA13 L2 H_D#43
A[14]# INIT# H_INIT# (10) D[11]# D[43]#
H_A#15 J20 1K/F_4 R36 330_4 +1.05V H_D#12 Y16 M3 H_D#44
H_A#16 A[15]# H_D#13 D[12]# D[44]# H_D#45
L21 A[16]# LOCK# W20 H_LOCK# (5) W13 D[13]# D[45]# J2
K20 H_D#14 AA9 H1 H_D#46
(5) H_ADSTB#0 ADSTB[0]# H_CPURST# (5) D[14]# D[46]#
T16 H_AP0 D17 D15 H_D#15 W9 J1 H_D#47
(5) H_REQ#[4:0] AP0 RESET# H_RS#[2:0] (5) D[15]# D[47]#
H_REQ#0 N21 W18 H_RS#0 Y14 K2
REQ[0]# RS[0]# (5) H_DSTBN#0 DSTBN[0]# DSTBN[2]# H_DSTBN#2 (5)
H_REQ#1 J21 Y17 H_RS#1 Y15 K3
REQ[1]# RS[1]# (5) H_DSTBP#0 DSTBP[0]# DSTBP[2]# H_DSTBP#2 (5)
H_REQ#2 G19 U20 H_RS#2 W16 L1
REQ[2]# RS[2]# (5) H_DINV#0 DINV[0]# DINV[2]# H_DINV#2 (5)
H_REQ#3 P20 W19 T7 H_DP#0 V9 M4 H_DP#2 T1
REQ[3]# TRDY# H_TRDY# (5) DP#0 DP#2
H_REQ#4 R19
REQ[4]# (5) H_D#[63:0] H_D#[63:0] (5)
AA17 H_D#16 AA5 C2 H_D#48
(5) H_A#[31:3] HIT# H_HIT# (5) D[16]# D[48]#
H_A#17 C19 V20 H_D#17 Y8 G2 H_D#49
A[17]# HITM# H_HITM# (5) D[17]# D[49]#
H_A#18 F19 H_D#18 W3 F1 H_D#50
H_A#19 A[18]# XDP_BPM#0 T13 H_D#19 D[18]# D[50]# H_D#51
E21 A[19]# BPM[0]# K17 U1 D[19]# D[51]# D3
H_A#20 A16 J18 XDP_BPM#1 T12 H_D#20 W7 B4 H_D#52
A[20]# BPM[1]# D[20]# D[52]#
DATA GRP 1
H_A#21 D19 H15 XDP_BPM#2 T9 H_D#21 W6 E1 H_D#53
H_A#22 A[21]# BPM[2]# XDP_BPM#3 T8 H_D#22 D[21]# D[53]# H_D#54
C14 A[22]# BPM[3]# J15 Y7 D[22]# D[54]# A5
ADDR GROUP 1
H_A#23 C18 K18 XDP_BPM#4 T20 H_D#23 AA6 C3 H_D#55
XDP/ITP SIGNALS
DATA GRP 3
C
H_A#24 A[23]# PRDY# XDP_BPM#5 H_D#24 D[23]# D[55]# H_D#56
C
C20 A[24]# PREQ# J16 XDP_BPM#5 Y3 D[24]# D[56]# A6
H_A#25 E20 M17 XDP_TCK H_D#25 W2 F2 H_D#57
A[25]# TCK XDP_TCK D[25]# D[57]#
H_A#26 D20 N16 XDP_TDI H_D#26 V3 C6 H_D#58
A[26]# TDI XPD_TDI D[26]# D[58]#
H_A#27 B18 M16 XDP_TDO H_D#27 U2 B6 H_D#59
H_A#28 A[27]# TDO XDP_TMS H_D#28 D[27]# D[59]# H_D#60
C15 A[28]# TMS L17 XPD_TMS T3 D[28]# D[60]# B3
H_A#29 B16 K16 XDP_TRST# H_D#29 AA8 C4 H_D#61
A[29]# TRST# XPD_TRST# D[29]# D[61]#
H_A#30 B17 V15 BR1# R39 PM_SYSRST# (12) H_D#30 V2 C7 H_D#62
H_A#31 A[30]# BR1# *0_4 R242 R241 H_D#31 D[30]# D[62]# H_D#63
C16 A[31]# +1.05V W4 D[31]# D[63]# D2
H_A#32 A17 G17 H_PROCHOT#_R 22_4 68_4 Y4 E2
A[32]# PROCHOT# H_PROCHOT# (25) (5) H_DSTBN#1 DSTBN[1]# DSTBN[3]# H_DSTBN#3 (5)
H_A#33 B14 E4 Y5 F3
THERM
A[33]# THRMDA H_THERMDA (16) (5) H_DSTBP#1 DSTBP[1]# DSTBP[3]# H_DSTBP#3 (5)
H_A#34 B15 E5 H_THERMDC (16) Y6 C5
A[34]# THRMDC (5) H_DINV#1 DINV[1]# DINV[3]# H_DINV#3 (5)
H_A#35 A14 T2 H_DP#1 R4 D4 H_DP#3
A[35]# DP#1 DP#3 T3
(5) H_ADSTB#1 B19 ADSTB[1]# THERMTRIP# H17 PM_THRMTRIP# (7,10)
H_AP1 M18 H_GTLREF A7 T1 COMP0 R220 27.4/F_4
T18 AP1 R8 *1K/F_4 ACLKPH GTLREF COMP[0] COMP1 R221 54.9/F_4
U5 ACLKPH COMP[1] T2
U18 R10 *1K/F_4 DCLKPH V5 F20 COMP2 R34 27.4/F_4
(10) H_A20M# A20M# DCLKPH COMP[2]
T16 V11 T14 H_BINIT# T17 F21 COMP3 R247 54.9/F_4
(10) H_FERR# FERR# BCLK[0] CLK_CPU_BCLK (2) BINIT# COMP[3]
H_IGNNE# J4 V12 T5 EDM R6 MISC
(10) H_IGNNE# IGNNE# BCLK[1] CLK_CPU_BCLK# (2) EDM
H CLK
R16 EXTGBREF M6 R18
(10) H_STPCLK# STPCLK# EXTBGREF DPRSTP# H_DPRSTP# (10,25)
T15 FORCEPR# N15 R17
(10) H_INTR LINT0 FORCEPR# DPSLP# H_DPSLP# (10)
R15 T4 H_HFPLL N6 U4
B (10) H_NMI LINT1 HFPLL DPWR# H_DPWR# (5) B
U17 T15 H_MCERR P17 V17
(10) H_SMI# SMI# MCERR# PWRGOOD H_PWRGD (10)
T6 H_RSP# T6 N18
RSP# SLP# H_CPUSLP# (5,10)
+1.05V R41 *1K_4 D6 NC1 RSVD3 C21 (2) CPU_BSEL0 J6 BSEL[0] CORE_DET A13 CORE_DET
+1.05V CAD Note: *1K_4 near CPU
R9 G6 C1 H5 B7 CPU_CMREF T39
NC
Place NC2 RSVD2 (2) CPU_BSEL1 BSEL[1] CMREF[1]
H6 NC3 RSVD1 A3 (2) CPU_BSEL2