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A B C D E
YUHINA2&3 Block Diagram
SYSTEM DC/DC
TPS51020DBT 38
INPUTS OUTPUTS
5V_S5
5V_S3
5V_S0
DCBATO UT
Project code: 91.40I01.001 3D3V_S 5
3D3V_S 3
4
CLK GEN. 4
Intel CPU
3D3V_S 0
PCB P/N : 48.40I01.0SB
ICS9514 02AGT
3 REVISION : 03245-2 SYSTEM DC/DC
Mobile P4 TPS5110 37
/Northwood INPUTS OUTPUTS
/Prescott 4, 5 2D5V_S 5
DCBATO UT
FSB 1D5V_S 0
400/53 3/800MHz
APL5331 36
CRT 13
DDR*2 2D5V_S 3 1D25V_ S0
266/333/ 400MHz ATI TV OUT 21 CPU DC/DC
11,12 RC300M LCD
MAX154 6AETL 39,40
3 CM2843A CIM25 39 3
XGA/SXGA+
6,7,8,9,10
14 INPUTS OUTPUTS
ALIK I/F Micro-P
ATTINY12 L-4SI DCBATO UT +VCC_CORE
66MHz
Realtek 42 1.3V 44A
10/100Mb RJ45
RTL8100C
26/A/4 23
24 +VID
BAT CONN 1.2V 0 .3A
Thermal & 43
2x FAN PCI BUS
33MHz CARDBUS MAXIM CHARGER
G768D 20 PCI 1520 CARDBUS AD CONN MAX1909
GHK PWR SW TWO SLOT 43 41
TPS2224A
Line In 25/B/1
AC'97 26 27 27 INVERTER INPUTS OUTPUTS
Mic In AC-Link
31 CODEC 14
BT+
2
ALC655
30
ATI Power DCBATOUT
18V 4 .0A
2
IXP150 Button
35
UP+5V
5V 10 0mA
EMI
Mini-PCI PCB LAYER
OP AMP
Line Out 45
L1: Signal 1
31 G1421 802.11A/B/G
31 21/B/2 25
L2: VCC/GND
LPC BUS 33MHz
L3: Signal 2
USB
2.0 16,17,18,19
L4: Signal 3
MODEM/BT
MDC Card KBC LPC LPC L5: GND
INT.SPKR PIDE NS SIO
SIDE
31 22
USB M38857 4MB DEBUG L6: Signal 4
ATA100 2.0 PC87392 SST49L F040
1
CONN. 1
34 33 32 32
HDD CD ROM USB Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21 21 X 4 22 Taipei Hsien 221, Taiwan, R.O.C.
Title
PS/2 BLOCK DIAGRAM
FDD PRN FIR Touch INT KB
Port29 Pad Debug Size Document Number Rev
Custom
21 28 33 33 con 33 YUHINA2&3 -2
Date: Tuesday, March 23, 2004 Sheet 1 of 46
A B C D E
1D2V_VID 1D2V_VID 4,5,39
1D5V_S0 1D5V_S0 6,9,15,36,45
2D5V_S0 2D5V_S0 7,15,18,44,45
2D5V_S3 2D5V_S3 8,9,11,12,18,36,37,44,45
3D3V_S0 3D3V_S0 3,4,6,7,9,11,13,14,15,16,17,18,19,20,21,22,23,25,26,27,28,30,32,33,34,35,39,44,45,46
3D3V_S3 3D3V_S3 8,14,16,17,18,19,30,33,44,45
3D3V_S5 3D3V_S5 4,8,17,18,19,22,30,35,36,38,44,45
3D3V_LAN_S5 3D3V_LAN_S5 22,23,24,44
5V_USB1_S0 5V_USB1_S0 22
5V_USB3_S0 5V_USB3_S0 22
5V_CRT_S0 5V_CRT_S0 13
5VA_AUD_S0 5VA_AUD_S0 30,31,46
5V_S0 5V_S0 6,9,13,14,15,18,20,21,22,25,27,29,30,31,32,33,34,36,39,40,42,44,45
5V_S5 5V_S5 15,37,38,42,44
+5V_UP_S5 +5V_UP_S5 14,42,45
5V_AUX_S5 5V_AUX_S5 16,20,35,38,39,41,42,43,45,46
LCDVDD LCDVDD 14
AD+ AD+ 41,43,45
DCBATOUT DCBATOUT 14,15,18,20,35,37,38,40,41,42,44,45,46
PCI DEVICE RESOURCE ASSIGNMENT VCC_FAN VCC_FAN 20
BUS DEVICE IDSEL PCI_REQ# PCI_GNT# INT_IRQ#
A_SKT_VCC_S0 A_SKT_VCC_S0 26,27
A_SKT_VPP_S0 A_SKT_VPP_S0 27
LAN 1 5 PCI_AD26 REQ#4 GNT#4 IRQD#
CardBus 1 9 PCI_AD20 REQ#1 GNT#1 IRQB#/IR QA#
MiniPCI 1 6 PCI_AD21 REQ#2 GNT#2 IRQE#
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Table of Content / HISTORY
Size Document Number Rev
A3
YUHINA2&3 -2
Date: Thursday, March 25, 2004 Sheet 2 of 46
3D3V_S0 CLK_VDD 3D3V_S0
R367 R323
1 2 CLK_VDDA 1 2 ** 1 2 ITP_CPUCLK ITP_CPUCLK 4,5
0R5J-1 0R5J-1 R320 DUMMY-0R3-0-U
SCD1U16V
SCD1U16V
DUMMY-SCD1U16V
SCD1U16V
SCD1U16V
SCD1U16V
SCD1U16V
CLK_VDD U40 DUMMY-SC4D7U10V5ZY ** 1 2 ITP_CPUCLK# ITP_CPUCLK# 4,5
C341 C334 R321 DUMMY-0R3-0-U
DUMMY-SC4D7U10V5ZY
C374
C371
SCD1U16V
C354
C356
C357
C372
C373
C386
C355
9 36 SCD1U16V RN10 SRN33-2-U2 CPUCLK CPUCLK 4
VDDXTAL VDDA R319
1 37 ** 1 4 1 2 49D9R3F
13 VDDREF VSSA ** 2 3 R322 1 2 49D9R3F
VDDPCI
19 40 CPUCLK_EXT_R CPUCLK# CPUCLK# 4
29 VDDPCI#19 CPUT0 39 CPUCLK#_EXT_R RN9 SRN33-2-U2
VDD48M CPUC0 NBCLK 7
30 44 NBCLK_EXT_R ** 1 4 R317
1 2 49D9R3F
48 VDDAGP CPUT1 43 ** 2 3 R318
1 2 49D9R3F
NBCLK#_EXT_R
VDDSD CPUC1
42 NBCLK# 7
VDDCPU 47 NB_DDRCLK_EXT_R ** R344
1 2 33R2
-2 8
SDRAMOUT NB_DDRCLK 7
5 GNDXTAL 32 AGPCLK0_EXT_R ** R345 1 2 33R2
GNDREF AGPCLK0 AGPCLK0 7
BC66 18 31 AGPCLK1_EXT_R ** R346 1 2 33R2 AGPCLK_66
GNDPCI AGPCLK1 AGPCLK_66 15
1 2 CK-408_GEN_X1 24
GNDPCI#24
XTAL-14D3 18M
1- PLACE ALL THE SERIES TERMINATION 25 16
GND48M PCICLK0
1
RESISTORS AS CLOSE AS U300 AS SC10P50V2JN-1 33 17
GNDAGP PCICLK1
2
46 20
POSSIB LE X4 R351 41 GNDSD PCICLK2 21 3D3V_S0
2- ROUTE ALL CPUCLK/#, NBCLK/# AND 1MR3 GNDCPU PCICLK3
22
6 PCICLK4 23
ITPCLK/# AS DIFFERENT PAIR RULE SB
1
2
3- PUT DECOUPLING CAPS C LOSE TO U300 BC61 XIN PCICLK5
11 PCI_SEL66/33# 1 R422 2 10KR3
1 2 CK-408_GEN_X2 7 PCI66/33#SEL
POWER P IN XOU T
14 FS3 **R424 1 2 22R2 ALINK_CLK ALINK_CLK 16
SC10P50V2JN-1 35 FS3/PCICLK_F0 15 FS4 1 R425 2 10KR3
-2 11,17 SMBC_SB
34
SCLK FS4/PCICLK_F1
1 R483 2 10KR3
11,17 SMBD_SB SDATA 26 ALINK
** R421
1 2 10 @@24/48#SEL 28 1 R347 2 33R2 66MHz
4,35,39 VID_PWRGD EXT_CLKEN
4,16,19,39 PM_STPCPU# 45 VTTPWRGD/PD# @ 48MHz_0 27
USB_48M_2
TP54
USB_48M 17 SB
0R0603-PAD 1 2 12 CPU_STP# @ 48MHz_1 TPAD30
R423 10KR3 PCI_STOP# @ 2 CKG_FS0 R418 1 2 DUMMY-33R2
CODEC_14M
FS0/REF0 CODEC_14M 30
2
38 3 CKG_FS1 ** R3971 2 33R2 SB_OSC
Ioh = 5 * I ref IREF FS1/REF1 SB_OSC 17
R420 4 CKG_FS2 R395 1 2 DUMMY-0R3-0-U
FS2/REF2
1
(2.32mA )
DUMMY-10KR3 Voh = 0.71V @ 60 ohm R331 ICS951402AGT
1
1
475R3F
1
R396 R182
10KR3 DUMMY-1K2R3F EXT CLK FREQUENCY SELECT TABLE(MHZ)
2
CPU & MEMORY Freq. Selection
2
2
NB_X1_1 7
FS4 FS3 FS2 FS1 FS0 CPU MEM AGP PCI
1
R180
CPU BSEL 1 BSEL 0
SB DUMMY-1KR3F 0 0 0 0 0 100.01 100.01 66.66 33.33
3D3V_S0 3D3V_S0 @These inputs have 120K internal pull-up resistor to VDD 0 0 0 0 1 133.33 133.33 66.66
400M Hz 0 0 33.33
2
533M Hz 0 1 @@ Internal pull-down res istors to GND 0 0 0 1 0 200.01 200.01 66.66 33.33
1
1
R482 R481 800M Hz 1 0 0 0 0 1 1 166.64 166.64 66.66 33.33
4K7R3 4K7R3
CLOSE TO NB 0 0 1 0 0 100.01 133.34 66.66 33.33
2
2
R417 1KR3 0 0 1 0 1 133.34 100.01 66.66 33.33
CKG_FS0 1 2
BSEL0 4,10
R419 1KR3 0 0 1 1 0 133.16 166.45 66.66 33.33
CKG_FS1 1 2 BSEL1 4,10
0 0 1 1 1 166.45 133.16 66.66 33.33
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Clock Generator -ICS951402
Size Document Number Rev
A3
YUHINA2&3 -2
Date: Thursday, April 08, 2004 Sheet 3 of 46
U22D VCC_CORE
U22B
8 GTL_A#[16:3]
1
GTL_A#16 N5 G1 GTL_ADS# 8
N4 A#16 ADS# AC1 R146
GTL_A#15 AP#0 8 GTL_D#[15:0] GTL_D#[47:32] 8
N2 A#15 AP#0 V5 TPAD30 TP48 1KR2 D25 T23
GTL_A#14 AP#1 GTL_D#15 GTL_D#47
A#14 AP#1 D#15 D#47
1
GTL_A#13 M1 AA3 BINIT# TPAD30 TP35 GTL_D#14 J21 T22 GTL_D#46
N1 A#13 BINIT# G2 D#14 D#46
GTL_A#12 GTL_BNR# 8 TPAD30 TP43 R66 GTL_D#13 D23 T25 GTL_D#45
2
A#12 BNR# 470R3 D#13 D#45
GTL_A#11 M4 D2 GTL_BPRI# 8 DPSLP# GTL_D#12 C26 T26 GTL_D#44
M3 A#11 BPRI# H21 D#12