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1 2 3 4 5 6 7 8
PCB STACK UP
8L
QL6 BLOCK DIAGRAM 01
CPU CPU THERMAL
LAYER 1 : TOP SENSOR
Penryn 14.318MHz
A LAYER 2 : SGND PAGE 5 A
478P (uPGA)/35W
LAYER 3 : IN1 PAGE 3,4 CLK_CPU_BCLK,CLK_CPU_BCLK#
CLOCK GEN
LAYER 4 : SGND CLK_MCH_BCLK,CLK_MCH_BCLK#
DREFCLK,DREFCLK# ALPRS355B MLF64PIN
LAYER 5 : SVCC FSB 667/800/1066
DREFSSCLK,DREFSSCLK#
PAGE 2
LAYER 6 : IN2
LAYER 7 : SGND PS8101
LAYER 8 : BOT PAGE 18 27MHz
NORTH BRIDGE
DDRII 667/800 MHz HDMI CON
DDRII-SODIMM1
PAGE 18
PAGE 10,11 Cantiga NVIDIA
PCI-Express
16X
NB9M-64bit CRT
DDRII-SODIMM2 DDRII 667/800 MHz
B
533p PAGE 18
B
PAGE 10,11
PAGE 5~9 Dual Link
PAGE 12~16 LCD CONN
32.768KHz PAGE 17
DMI LINK NBSRCCLK, NBSRCCLK#
SATA - HDD
SATA0 150MB USB2.0
PAGE 28 0,1,2 8 9 12MHz 6 7,10,11
SYSTEM CHARGER(ISL6251AHAZ-T) USB2.0 Ports BlueTooth Webcam
SOUTH BRIDGE Mini PCI-E Card x2
PAGE 32 SATA1 150MB X3 PAGE 31 PAGE 29 PAGE 17
Express Card x1
SATA - CD-ROM CR for UMA
RTS5158E PAGE 28,31
PAGE 28 PAGE 23
SYSTEM POWER ISL6237IRZ-T
ICH9-M
PAGE 33
E-SATA
SATA5 150MB PCI-E
PAGE 31 X2 X1 X1
C DDR II SMDDR_VTERM Azalia C
1.8V/1.8VSUS(TPS51116REGR) Mini PCI-E Express
PAGE 37
PAGE 19,20,21,22 LAN
Card Realtek Card
Analog (Wireless LAN PCIE-LAN (NEW CARD)
VCCP +1.5V AND GMCH / Robson)
1.05V(RT8204) 32.768KHz LPC Realtek RTL8102E/8111C
(10/100/GagaLAN)
ALC268 PAGE 28
PAGE 34 MDC CONN PAGE 31 PAGE 26,27
PAGE 25 PAGE 24
VGACORE(1.025V)Oz8118
Keyboard ENE KBC 25MHz
PAGE 36 Touch Pad PAGE 29 AUDIO
Amplifier
KB3926 C0 SPI RJ45
TPA6017A2
CPU CORE ISL6266A PAGE 26
PAGE 22
PAGE 35 PAGE 25
PAGE 30
D
microphone Audio Jacks Jack to D
(Phone/ MIC) Speaker
PAGE 17 PAGE 24 PAGE 25
GMT G9931P1U
SPI PROJECT : QL6
FAN Quanta Computer Inc.
PAGE 29 PAGE 30
Size Document Number Rev
Custom
NB5 Block Diagram 2A
Date: Tuesday, February 26, 2008 Sheet 1 of 40
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
4,6,9,10,11,12,14,15,17,18,19,20,21,22,24,25,26,28,29,30,31,35,36,38 +3V
02
3,4,5,6,8,9,19,22,29,34,35 +1.05V
+3V
L33
1 2 +3V_CK_MAIN
HCB1608KF-181T15_6 U14
C480
C523 C476 C772 C496 C475 +3V_CK_MAIN 23 61
VDDPLL3 CPUCLKT0 CLK_CPU_BCLK 3
10U/6.3V_8 .1U/10V_4 .1U/10V_4 .1U/10V_4 .1U/10V_4 .1U/10V_4 16 60
A VDD48 CPUCLKC0 CLK_CPU_BCLK# 3 A
9
4
VDDPCI
VDDREF
CK505 CPUCLKT1 58 CLK_MCH_BCLK 5
L49 46 57
VDDSRC CPUCLKC1 CLK_MCH_BCLK# 5
1 2 +3V_CK_CPU +3V_CK_CPU 62
HCB1608KF-181T15_6 VDDCPU SRC8 RP50 4
CPUT2_ITP/SRCT8 54 3 *4P2R-S-0 CLK_CPU_ITP 3
+3V_CK_MAIN2 19 53 SRC8# 2 1
VDD96I/O CPUC2_ITP/SRCC8 CLK_CPU_ITP# 3
C778 C486 27
10U/6.3V_8 .1U/10V_4 VDDPLL3I/O SRC0 RP61 4
33 VDDSRCI/O DOTT_96/SRCT0 20 3 *4P2R-S-0 DREFCLK 6
43 21 SRC0# 2 1 int
VDDSRCI/O DOTC_96/SRCC0 DREFCLK# 6
52 VDDSRCI/O
24 SRC1
L34 27MHz_Nonss/SRCCLK1/SE1 SRC1# RP47 2
56 VDDCPU_IO 27Mhz_ss/SRCCLC1/SE2 25 1 4P2R-S-0 CLK_PCIE_VGA 12
1 2 +3V_CK_MAIN2 55 4 3 des
NC CLK_PCIE_VGA# 12
HCB1608KF-181T15_6 28
SRCCLKT2/SATACL CLK_PCIE_NEW 28
SRCCLKC2/SATACL 29 CLK_PCIE_NEW# 28
C521 C514 C783 C487 C524 C511 C495 CG_XIN 3
10U/6.3V_8 .1U/10V_4 .1U/10V_4 .1U/10V_4 .1U/10V_4 .1U/10V_4 .1U/10V_4 CG_XOUT X1
2 X2 SRCCLKT3/CR#_C 31
SRCCLKC3/CR#_D 32
*100K/F_4 R286 34
SRCCLKT4 CLK_PCIE_3GPLL 6
SRCCLKC4 35 CLK_PCIE_3GPLL# 6 int
SRC1 RP51 2 1 *4P2R-S-0 DREFSSCLK 6
63 45 SRC1# 4 3
21 CK_PWG CK_PWRGD/PD# PCI_STOP# PM_STPPCI# 21 DREFSSCLK# 6
+3V CPU_BSEL1 R282 2.2K_4 FSB 64 44
+3V FSLB/TEST_MODE CPU_STOP# PM_STPCPU# 21
48 RP60 4 3 4P2R-S-33
SRCCLKT6 CLK_PCIE_ICH 20 27M_NONSS 14
SRCCLKC6 47 CLK_PCIE_ICH# 20 2 1 27M_SS 14
2
7 SCLK SRCCLKT7/CR#_F 51 CLK_PCIE_WLAN 31 des
Q11 R272 R271 10,11,28,31 CGCLK_SMB 6 50
SDATA SRCCLKC7/CR#_E CLK_PCIE_WLAN# 31
2
B R240 10K/F_4 10K/F_4 10,11,28,31 CGDAT_SMB B
10K/F_4 2N7002 37
SRCCLKT9 CLK_PCIE_LAN 26
3 1 CGDAT_SMB 22 38
21 PDAT_SMB CLK_PCIE_LAN# 26
1
GND SRCCLKC9
26 GND
TME 18 41
GND48 SRCCLKT10 CLK_PCIE_SATA 19
59 GNDCPU SRCCLKC10 42 CLK_PCIE_SATA# 19
15 GNDPCI
+3V 1 40
GNDREF SRCCLKT11/CR#_H CLK_PCIE_WWAN 31
30 GNDSRC SRCCLKC11/CR#_G 39 CLK_PCIE_WWAN# 31
Q12 36 GNDSRC
2
49 GNDSRC
2N7002 8 R_CLK_NEWCARD_OE# R270 475/F_4
PCICLK0/CR#_A CLK_NEWCARD_OE# 28
3 1 CGCLK_SMB 10 R_CLK_MCH_OE# R244 475/F_4
21 PCLK_SMB PCICLK1/CR#_B CLK_MCH_OE# 6
11 TME R231 33_4
PCICLK2/TME PCLK_DEBUG 31
12 R_PCLK_KBC R260 33_4
PCICLK3 PCLK_KBC 30
13 27M_SEL
PCICLK4/27_SELECT
0=overclocking
65 ITP_EN R255 33_4
of CPU and Y2 EPAD PCLK_ICH 20
CG_XIN 1 CG_XOUT R281 22_4
DV-2 modify
SRC Allowed 2 PCI_F5/ITP_EN 14 CLK_48M_USB 21
R278 22_4
CLK_48M_CR 23
1 = overclocking 17 FSA R287 2.2K_4 CPU_BSEL0
14.318MHZ USB_48MHZ/FSLA
1
1
FSC R246 10K/F_4 CPU_BSEL2
of CPU and SRC C470 C478 5 FSLC R273 33_4
FSLC/TST_SL/REF CLK_14M_ICH 21
not Allowed 27P/50V_4 27P/50V_4
2
2
RTM875N-606-VD-GR
+3V
C C
CK505 QFN64
2
des R268 ICS ICS9LPRS355BKLF ALPRS355000 +3V
10K/F_4 27M_SEL
PIN20 PIN21 PIN24 PIN25 Silego SLG8SP513VTR AL8SP513000
1
27M_SEL PIN13 CLK_MCH_OE# R235 2 1 10K/F_4
Realtek RTM875N-606-VD-GR AL000875000
2
0=UMA DOT96T DOT96C SRCT1/LCDT_100 SRCT1/LCDT_100 CLK_NEWCARD_OE# R269 2 1 10K/F_4
int R274
*10K/F_4
1 = External
1
VGA SRCT0 SRCC0 27Mout-NSS 27Mout-SS
0=UMA
1 = External VGA C466 *33P/50V_4 PCLK_KBC
DV-2 modify FSC FSB FSA CPU SRC PCI C467 *27P/50V_4 PCLK_ICH
CPU Clock select
+3V C457 *33P/50V_4 PCLK_DEBUG
CPU_BSEL0 R289 0_4
1 0 1 100 100 33
3 CPU_BSEL0 MCH_BSEL0 6
0 0 1 133 100 33 C484 10P/50V_4 CLK_48M_USB
2
0 1 1 166 100 33 C482 10P/50V_4 CLK_48M_CR
*10K/F_4 R288 *1K/F_4
R266 0 1 0 200 100 33 C463 *33P/50V_4 CLK_14M_ICH
R_PCLK_KBC CPU_BSEL1 R540 0_4
3 CPU_BSEL1 MCH_BSEL1 6
1
D D
0 0 0 266 100 33 for EMI
ITP_EN
1 0 0 333 100 33
2
2
+1.05V R538 *1K/F_4
R248 1 1 0 400 100 33
10K/F_4 *10K/F_4 CPU_BSEL2 R233 0_4
R261
3 CPU_BSEL2 MCH_BSEL2 6
1 1 1 RSVD 100 33 PROJECT : QL6
Quanta Computer Inc.
1K to NB only when
1
1
XDP is implement.No
+1.05V R239 *1K/F_4 XDP can use 0 ohm
Enable ITP CLK
Size Document Number Rev
Custom
NB5 Clock Generator 2A
Date: Tuesday, February 26, 2008 Sheet 2 of 40
1 2 3 4 5 6 7 8
5 4 3 2 1
2,4,5,6,8,9,19,22,29,34,35 +1.05V
5 H_A#[35:3]
H_A#3
H_A#4
J4
U18A
A[3]# ADS# H1 H_ADS# 5 5 H_D#[63:0]
U18B H_D#[63:0]
03
L5 A[4]# BNR# E2 H_BNR# 5
ADDR GROUP 0
H_A#5 L4 G5 H_D#0 E22 Y22 H_D#32
A[5]# BPRI# H_BPRI# 5 D[0]# D[32]#
H_A#6 K5 H_D#1 F24 AB24 H_D#33
H_A#7 A[6]# H_D#2 D[1]# D[33]# H_D#34
M3 A[7]# DEFER# H5 H_DEFER# 5 E26 D[2]# D[34]# V24
H_A#8 N2 F21 H_D#3 G22 V26 H_D#35
A[8]# DRDY# H_DRDY# 5 D[3]# D[35]#
H_A#9 J1 E1 H_D#4 F23 V23 H_D#36
D A[9]# DBSY# H_DBSY# 5 D[4]# D[36]# D
H_A#10 N3 H_D#5 G25 T22 H_D#37
H_A#11 A[10]# H_D#6 D[5]# D[37]# H_D#38
P5 A[11]# BR0# F1 HBREQ#0 5 E25 D[6]# D[38]# U25
DATA GRP 0
DATA GRP 0
DATA GRP 2
H_A#12 P2 H_D#7 E23 U23 H_D#39
A[12]# D[7]# D[39]#
CONTROL
CONTROL
H_A#13 L2 D20 H_IERR# R41 56.2/F_4 +1.05V H_D#8 K24 Y25 H_D#40
H_A#14 A[13]# IERR# H_D#9 D[8]# D[40]# H_D#41
P4 A[14]# INIT# B3 H_INIT# 19 G24 D[9]# D[41]# W22
H_A#15 P1 H_D#10 J24 Y23 H_D#42
H_A#16 A[15]# H_D#11 D[10]# D[42]# H_D#43
R1 A[16]# LOCK# H4 H_LOCK# 5 J23 D[11]# D[43]# W24
M1 H_D#12 H22 W25 H_D#44
5 H_ADSTB#0 ADSTB[0]# H_CPURST# 5 D[12]# D[44]#
C1 H_D#13 F26 AA23 H_D#45
5 H_REQ#[4:0] RESET# D[13]# D[45]#
H_REQ#0 K3 F3 H_RS#0 H_D#14 K22 AA24 H_D#46