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A B C D E
1 1
2
Compal confidential 2
Schematics Document
AMD K8 with
3
ATI RS480M+ATI SB400 3
2005-08-29
REV:0.8
4 4
Security Classification Compal Secret Data
Issued Date 2005/03/01 Deciphered Date 2005/04/06 Title
Cover Page
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-2771 0.8
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, August 30, 2005 Sheet 1 of 53
A B C D E
A B C D E
Compal confidential
File Name : LA-2771
Memory BUS(DDR)
DDR-SO-DIMM-0
1 Thermal Sensor Mobile BANK 0, 1, 2, 3 page 8,10
1
ADM1032
page 4
AMD Athlon 64 2. 5V DDR- 400
754 pin DDR-SO-DIMM-1
page 4, 5, 6, 7 BANK 0, 1, 2, 3 page 9,10
Clock Generator
Fan Control ICS 951412
page 4 2. 5V DDR- 400
HT 16x16 1000MHZ page 16
1 x PCIE
New Card
LVDS Panel ATI-RS480M Connector
page 27
Interface page 17
705 BGA
2 CRT & TV OUT page 11, 12, 13, 14 TV tuner 2
page 34
page 18 A-Link Express
2 x PCIE
USB conn X3
USB2.0 page 34
Side Port(VRAM)
16M x 16 page 15 BT Conn
ATI-SB400 AC-LINK
page 34
ATA-100
Primary IDE
3.3V 33 MHz PCI BUS 564 BGA Audio CKT MODEM
page 19, 20, 21, 22 AMOM page 31 AMOM page 32
LAN CardBus Controller PATA HDD AMP & Audio Jack
MINI PCI RTL 8100CL TI PCI7411/PCI1510 Connector page 33
LPC BUS page 24
page 30 page 29 page 25,26,27
3 3
CDROM
RTC CKT. Connector
page 19 RJ45 CONN Slot 0 1394 Card reader page 24
page 29 page 27 page 25 page 26
ENE KB910/L
page 37, 38
Power OK CKT. SPR CONN.
page 42 *RJ45 CONN
Touch Pad Int.KBD *MIC IN JACK
page 35 page 35
*LINE OUT JACK
*1394 CONN
Power On/Off CKT. BIOS *SPDIF CONN
page 35 page 39 *DC JACK
*TVOUT CONN
*USB CONN x1
*CIR x1
4
DC/DC Interface CKT. 4
page 40
page 41
Power Circuit DC/DC Security Classification Compal Secret Data
Issued Date 2005/03/01 Deciphered Date 2005/04/06 Title
page 43~49 Block Diagram
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-2771 0.8
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, August 30, 2005 Sheet 2 of 53
A B C D E
A
Voltage Rails BOM STATUS :
+5VS VRAM@ ,VRAMIC@, SAMSUNG@, HYNIX@, 2HDD@ ,7411@ ,EXP@ ,17_EXP@
+3VS ,15_EXO@,CIR@ ,D@, C@, 15.4@, DOCK@, WL_LED@
power
plane +2.5VS
+12VALW +5V
+1.8VS
+5VALW +2.5V
+1.5VS
+3VALW +1.25V
+2.5VDDA 45@ ( for 45 level RTC battery )
State +1.8VALW
+CPU_CORE
+1.2V_HT
HAL10 17" VRAM@ , SAMSUNG@, HYNIX@, 2HDD@ ,7411@ ,EXP@ ,17_EXP@ ,CIR@
S0 O O O ,D@ ,DOCK@,WL_LED@
S1
O O O HAL20 FF 15.4" VRAM@ , SAMSUNG@, HYNIX@, 2HDD@ ,7411@ ,EXP@ ,15_EXP@ ,CIR@
S3 ,C@ ,DOCK@,WL_LED@, 15.4@(LED)
O O X
S5 S4/AC
O X X HAL20 DF 15.4" EXP@, C@ ,DOCK@ ,15.4@(LED), CIR@, WLAN@, 15_EXP@
S5 S4/AC don't exist
X X X
O MEANS ON
X MEANS OFF
PCI Devices
1 1
INTERNAL
DEVICE IDSEL # REQ/GNT # PIRQ
SM BUS
IDE A
LPC I/F
PCI to PCI
AC97 AUDIO B
A C97 MODEM B
OHCI#1 USB D
OHCI#1 USB D
EHCI USB D
SAT A#1 A
SAT A#2 A
EXTERNAL
Wire less LAN AD18 3 F
LAN AD22 1 G
CARD BUS & 1394 AD20 2 E ,H
Security Classification Compal Secret Data
Issued Date 2005/03/01 Deciphered Date 2005/04/06 Title
Notes List
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-2771 0.8
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, August 30, 2005 Sheet 3 of 53
A
A B C D E
ZZZ1
L A -2771 REV 0
H_CADIP[0..15] H_CADOP[0..15]
<11> H_CADIP[0..15] H_CADOP[0..15] <11>
H_CADIN[0..15] H_CADON[0..15]
<11> H_CADIN[0..15] H_CADON[0..15] <11>
Fan Control Circuit
4 JP1A 4
+5VS
Claw Hammer-DTR
H_CADIP15 T25 N26 H_CADOP15
H_CADIN15 L0_CADIN_H15 L0_CADOUT_H15 H_CADON15 B+
R25 N27 1 2
H_CADIP14 L0_CADIN_L15 L0_CADOUT_L15 H_CADOP14
U27 L25
H_CADIN14 L0_CADIN_H14 L0_CADOUT_H14 H_CADON14 C2 C1
U26 M25
H_CADIP13 L0_CADIN_L14 L0_CADOUT_L14 H_CADOP13 0.1U_0402_16V4Z 10U_1206_16V4Z
V25 L26
H_CADIN13 L0_CADIN_H13 L0_CADOUT_H13 H_CADON13 +3VS
U25 L27 2 1
L0_CADIN_L13 L0_CADOUT_L13
8
1
2
5
6
H_CADIP12 W27 J25 H_CADOP12
H_CADIN12 L0_CADIN_H12 L0_CADOUT_H12 H_CADON12 D
W26 K25
P
L0_CADIN_L12 L0_CADOUT_L12
2
HTT Interface
H_CADIP11 AA27 G25 H_CADOP11 3 G Q1
L0_CADIN_H11 L0_CADOUT_H11 <37,38> EN_FAN1 +IN
H_CADIN11 AA26 H25 H_CADON11 1 FAN1_ON 3 SI3456DV-T1_TSOP6 R1
H_CADIP10 L0_CADIN_L11 L0_CADOUT_L11 H_CADOP10 OUT S
AB25 L0_CADIN_H10 L0_CADOUT_H10 G26 2 -IN 10K_0402_5%
H_CADIN10 AA25 G27 H_CADON10 U1A
4
L0_CADIN_L10 L0_CADOUT_L10
G
H_CADIP9 AC27 E25 H_CADOP9 LM358A_SO8
1
H _CADIN9 L0_CADIN_H9 L0_CADOUT_H9 H_CADON9
AC26 F25
4
H_CADIP8 L0_CADIN_L9 L0_CADOUT_L9 H_CADOP8
AD25 L0_CADIN_H8 L0_CADOUT_H8 E26
H _CADIN8 AC25 E27 H_CADON8 JP2
H_CADIP7 L0_CADIN_L8 L0_CADOUT_L8 H_CADOP7 FAN1
T27 L0_CADIN_H7 L0_CADOUT_H7 N29 1 2 1
H _CADIN7 T28 P29 H_CADON7 R2
L0_CADIN_L7 L0_CADOUT_L7 2
1000P_0402_50V7K
C4 10U_0805_10V4Z
H_CADIP6 V29 M28 H_CADOP6 100K_0402_5%
L0_CADIN_H6 L0_CADOUT_H6 3
1
1
H _CADIN6 U29 M27 H_CADON6 1 1
H_CADIP5 L0_CADIN_L6 L0_CADOUT_L6 H_CADOP5 R3 ACES_85205-0300
V27 L0_CADIN_H5 L0_CADOUT_H5 L29
H _CADIN5 V28 M29 H_CADON5 150K_0402_5%
H_CADIP4 L0_CADIN_L5 L0_CADOUT_L5 H_CADOP4 D1 @
Y29 L0_CADIN_H4 L0_CADOUT_H4 K28
H _CADIN4 W29 K27 H_CADON4 1N4148_SOT23 2 2
2
H_CADIP3 L0_CADIN_L4 L0_CADOUT_L4 H_CADOP3
AB29 L0_CADIN_H3 L0_CADOUT_H3 H28
C3
H _CADIN3 AA29 H27 H_CADON3
H_CADIP2 L0_CADIN_L3 L0_CADOUT_L3 H_CADOP2
AB27 G29
3
2
H _CADIN2 L0_CADIN_H2 L0_CADOUT_H2 H_CADON2
AB28 L0_CADIN_L2 L0_CADOUT_L2 H29
3 H_CADIP1 H_CADOP1 3
AD29 L0_CADIN_H1 L0_CADOUT_H1 F28
H _CADIN1 AC29 F27 H_CADON1
H_CADIP0 L0_CADIN_L1 L0_CADOUT_L1 H_CADOP0
AD27 L0_CADIN_H0 L0_CADOUT_H0 E29 <37,38> FAN_SPEED1
H _CADIN0 AD28 F29 H_CADON0 1
L0_CADIN_L0 L0_CADOUT_L0
@ C5
1000P_0402_50V7K
H_CLKIP1 Y25 J26 H_CLKOP1 2
<11> H_CLKIP1 H_CLKIN1 L0_CLKIN_H1 L0_CLKOUT_H1 H_CLKON1 H_CLKOP1 <11>
<11> H_CLKIN1 W25 J27 H_CLKON1 <11>
H_CLKIP0 L0_CLKIN_L1 L0_CLKOUT_L1 H_CLKOP0
<11> H_CLKIP0 Y27 J29 H_CLKOP0 <11>
+1.2V_HT H_CLKIN0 L0_CLKIN_H0 L0_CLKOUT_H0 H_CLKON0
<11> H_CLKIN0 Y28 K29 H_CLKON0 <11>
L0_CLKIN_L0 L0_CLKOUT_L0
R4 49.9_0402_1% 2 1 R27 N25
R5 49.9_0402_1% 2 L0_CTLIN_H1 L0_CTLOUT_H1
1 R26 P25
H_CTLIP0 L0_CTLIN_L1 L0_CTLOUT_L1 H_CTLOP0
<11> H_CTLIP0 T29 P28 H_CTLOP0 <11>
+1.2V_HT H_CTLIN0 L0_CTLIN_H0 L0_CTLOUT_H0 H_CTLON0
<11> H_CTLIN0 R29 P27 H_CTLON0 <11>
L0_CTLIN_L0 L0_CTLOUT_L0
R6 44.2_0603_1% 2 1 LVREF1 AF27 AJ27 LDTSTOP#
L0_REF1 LDTSTOP_L LDTSTOP# <13,19>
R7 44.2_0603_1% 1 2 LVREF0 AE26
L0_REF0
1 2 +2.5VS
FOX_PZ75403-2941-42 R8
680_0402_5%
Thermal Sensor THERMDA_CPU
THERMDA_CPU <6>
ADM1032 THERMDC_CPU
THERMDC_CPU <6>
+3VS
2 W =1 5mil 2
U2 2
EC_SMC_2 8 1 C6
<37,38> EC_SMC_2 SCLK VDD
1
EC_SMD_2 7 2 THERMDA_CPU C7 0.1U_0402_16V4Z
<37,38> EC_SMD_2 SDATA D+ 1
6 3 THERMDC_CPU 2200P_0402_50V7K
ALERT# D- 2
5 4
GND THERM#
ADM1032AR_SOP8
1 1
Security Classification Compal Secret Data
Issued Date 2005/03/01 Deciphered Date 2005/04/06 Title
Claw Harmmer & Fan
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-2771 0.8
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, August 30, 2005 Sheet 4 of 53
A B C D E
A B C D E
50 mil width/20 mil space
+1.25VREF_CPU
JP1B
+2.5V AG12 MEMVREF1
34.8_0603_1% 1 R10 MEMZN
34.8_0603_1%
2
2 1 R11 MEMZP
D14
C14
MEMZN Claw Hammer-DTR
1 MEMZP 1
<8> DDR_SDQ[0..63]
DDR_SDQ63 A16 AE8 DDR_CKE0
DDR_SDQ62 MEMDATA63 MEMCKEA DDR_CKE1 DDR_CKE0 <8>
B15 AE7 DDR_CKE1 <9>
DDR_SDQ61 MEMDATA62 MEMCKEB
A12
DDR_SDQ60 MEMDATA61 DDR_CLK7
B11 D10 DDR_CLK7 <8>
DDR_SDQ59 MEMDATA60 MEMCLK_H7 DDR_CLK7# DDR_CLK7 R12 120_0402_5% DDR_CLK7#
A17 C10 DDR_CLK7# <8> 1 2
DDR_SDQ58 MEMDATA59 MEMCLK_L7 DDR_CLK6
A15 E12 DDR_CLK6 <9>
DDR_SDQ57 MEMDATA58 MEMCLK_H6 DDR_CLK6# DDR_CLK6 R13 120_0402_5% DDR_CLK6#
C13 E11 DDR_CLK6# <9> 1 2
DDR_SDQ56 MEMDATA57 MEMCLK_L6 DDR_CLK5
A11 AF8 DDR_CLK5 <8>
DDR_SDQ55 MEMDATA56 MEMCLK_H5 DDR_CLK5# DDR_CLK5 R14 120_0402_5% DDR_CLK5#
A10 AG8 DDR_CLK5# <8> 1 2
DDR_SDQ54 MEMDATA55 MEMCLK_L5 DDR_CLK4
B9 AF10 DDR_CLK4 <9>
DDR_SDQ53 MEMDATA54 MEMCLK_H4 DDR_CLK4# DDR_CLK4 R15 120_0402_5% DDR_CLK4#
C7 MEMDATA53 MEMCLK_L4 AE10 DDR_CLK4# <9> 1 2
DDR_SDQ52 A6 V3
DDR_SDQ51 MEMDATA52 MEMCLK_H3
C11 MEMDATA51 MEMCLK_L3 V4
DDR_SDQ50 A9 K5
DDR_SDQ49 MEMDATA50 MEMCLK_H2
A5 MEMDATA49 MEMCLK_L2 K4
DDR_SDQ48 B5 R5
DDR_SDQ47 MEMDATA48 MEMCLK_H1
C5 MEMDATA47 MEMCLK_L1 P5
DDR_SDQ46 A4 P3
DDR_SDQ45 MEMDATA46 MEMCLK_H0
E2 MEMDATA45 MEMCLK_L0 P4
DDR_SDQ44 E1
DDR_SDQ43 MEMDATA44
A3 MEMDATA43 MEMCS_L7 D8
DDR_SDQ42 B3 C8
DDR_SDQ41 MEMDATA42 MEMCS_L6
E3 MEMDATA41 MEMCS_L5 E8
DDR_SDQ40 F1 E7
DDR_SDQ39 MEMDATA40 MEMCS_L4 DDR_SCS#3
G2 MEMDATA39