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8 7 6 5 4 3 2 1
Last Schematic Update Date:
10/03/2001
D
Cover Sheet 1 D
MS-6547 VERSION:0B
Block Diagram
MAIN CLOCK GEN
2
3
SIS 645/650 CHIPSET
DDR CLOCK BUFFER 4
Willamette/Northwood 478pin mPGA-B Processor Schematics
mPGA478-B INTEL CPU Sockets 5-6
SIS 645/650 NORTH BRIDGE 7- 10
CPU: DDR SLOT 11-12
Willamette/Northwood mPGA-478B Processor DDR TERMINATOR 13
SIS 961A SOUTH BRIDGE 14-17
System Brookdale Chipset:
AGP SLOT 18
C
SIS 645/650 (North Bridge) C
+961A (South Bridge) PCI SLOTS 19-21
On Board Chipset: IDE CONNECTOR 22
USB CONNECTOR 23
LPC Super I/O -- W83697HF
KB/MS CONNECTOR 24
Expansion Slots: AC'97 CODEC 25
AGP2.0 SLOT * 1
AUDIO CONNECTOR 26
PCI2.2 SLOT* 5
CNR CONNECTOR 27
CNR SLOT * 1
LPC I/O(W83697HF) 28
HARDWARE MONITOR 29
B
PARALLEL PORT 30 B
SERIAL PORT 31
FLASH MEMORY 32
VRM 9.X 33
VOLTAGE REGULATOR 34-35
ATX POWER CON & VGA CON 36
FRONT PANEL 37
Decoupling Capacitor 38
MS-3 (D-LED) 39
A A
MICRO-STAR INT'L CO.,LTD.
Title
COVER PAGE
Size Document Number Rev
C MS-6547 1.0A
Date: , 13, 2001 Sheet 1 of 39
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
System Block Diagram
D D
SOCKET-478
Host Bus
Support Dual Monitor
SSTL-2 Termination
VGA VGA SLOT DDR SDRAM (Only for DDR)
D-SUB
SIS645/650
DIMM 1 DIMM 2 DIMM 3 Rtt
C VGA Connector VGA CONNECTOR VGA C
HyperZip Analog In
Support Max to six-PCI Devices
512 MB
AC'97
Audio Codec
PCI SLOT 5 PCI SLOT 4 PCI SLOT 3 PCI SLOT 2 PCI SLOT 1 Analog Out
SiS961 ACR
IDE 1 IDE 2
KEYBOARD PS/2
/MOUSE
B USB 0 USB 2 B
USB 1 USB 4
LPC Bus USB 3 USB 5
FAN FAN FAN CONTROL VOLTAGE MONITOR
1 2
TEMPERATURE MONITOR
LPC Super I/O
Legacy FAN CONTROL
ROM
A GPIOs IR/CIR GAME/MIDI SERIAL PARALLEL FLOPPY
A
MICRO-STAR INT'L CO.,LTD.
Title
System Block Diagram
Size Document Number Rev
B MS-6547 1.0A
Date: , 13, 2001 Sheet 2 of 39
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
VCC3 Main Clock Generator
(3 OPTIONS)
1: (ICS)
2: (Cypress)
3. (Hitachi)
L48 CP24
X_COPPER By-Pass Capacitors
80_0805 Place near to the Clock Outputs
U15
D 952001AF
CPUCLK0 R215 49.9
D
1 CPUCLK-0 R216 49.9
VDDREF Damping Resistors
11 VDDZ
13 Place near to the CPUCLK1 R213 49.9
VDDPCI Clock Outputs CPUCLK-1 R214
19 49.9
VDDPCI
28 VDD48
+ CE7 CB178 CB177 CB196 CB179 29
22u 0.1u 0.1u 0.1u CB180 CB1970.1u CB182 CB198 VDDAGP SDCLK C110 10p
42 VDDCPU
0.1u 0.1u 0.1u 0.1u 48 40 R237 33 CPUCLK0
VDDSD CPUCLK0 CPUCLK0 5
39 R238 33 CPUCLK-0
CPUCLK#0 CPUCLK-0 5
12 AGPCLK0 C111 10p
PCI_STOP# R235 CPUCLK1
45 44 33 CPUCLK1 7
CPU_STOP# CPUCLK1 R236 CPUCLK-1 AGPCLK1 C112 10p
43 33 CPUCLK-1 7
CPUCLK#1
5 47 R234 22 SDCLK
VSSREF SDCLK SDCLK 8
8 ZCLK0 C163 10p
VSSZ R239 AGPCLK0
18 31 22 AGPCLK0 7
VSSPCI AGPCLK0 R240 AGPCLK1 ZCLK1 C164 10p
24 30 22 AGPCLK1 18
VSSPCI AGPCLK1
25 VSS48
32 9 R289 22 ZCLK0
VSSAGP ZCLK0 ZCLK0 9
41 10 R290 22 ZCLK1
VSSCPU ZCLK1 ZCLK1 14
46 CN18 10p
VSSSD FS3 RN76 7
PCICLK_F0/FS3 14 8 33 96XPCLK
96XPCLK 14
PCICLK2 1 2
VCC3 VCC3 15 FS4 5 6 SIOPCLK PCICLK1 3 4
PCICLK_F1/FS4 SIOPCLK 28
16 3 4 PCICLK1 SIOPCLK 5 6
PCICLK0 PCICLK1 19
17 1 2 PCICLK2 96XPCLK 7 8
PCICLK1 PCICLK2 20
20 RN77 33
R219 R218 PCICLK2
PCICLK3 21 7 8
10K 10K PCICLK3 PCICLK5 CN19 1 2 10p
C PCICLK4 22
23
5
3
6
4 PCICLK4
PCICLK3 20
PCICLK4 21
PCICLK4 3 4
C
PCICLK5 PCICLK5 PCICLK3
1 2 PCICLK5 21 5 6
33 2 FS0 RN111 33 7 8
VCCP PD#/VTT_PWRGD REF0/FS0 FS1 REFCLK0
REF1/FS1 3 7 8 REFCLK0 9
R207 4 FS2 5 6 REFCLK1
REF2/FS2 REFCLK1 15
Q27 Q26 R217 475 38 3 4 APICCLK APICCLK C161 10p
IREF APICCLK 15
48M 27 1 2
10K NPN-MBT3904LT1-S-SOT23 26
NPN-MBT3904LT1-S-SOT23 24_48M/MULTISEL R241 UCLK48M REFCLK0 C153 10p
22 UCLK48M 16
MULTISEL R242 22 SIO48M
SIO48M 28
CP26 X_COPPER REFCLK1 C160 10p
SCLK 35
VCC3 34
SDATA UCLK48M C113 10p
L49 SMBCLK
SMBCLK 4,11,12,15,27
36 SMBDAT SIO48M C114 10p
VDDA SMBDAT 4,11,12,15,27
X_80_0805
CB194 CB187 CB181
0.1u 0.1u 100P
37 VSSA
VCC3 Frequency Selection
XOUT
XIN
B R291 2.7K FS0 B
6
7
VCC3 R292 X_2.7K FS1
Y1 R288 X_2.7K FS2
R271 X_2.7K FS3
R276 X_2.7K FS4
14M-16pf-HC49S-D
+ CE11
CB195 CB184 C143 C134
10p 10p
22u 0.1u 100P MULTISEL R220 X_0
R243 X_4.7K
VCC3
SIS650 CLOCK SIS650 CLOCK
FS4 FS3 FS2 FS1 FS0 CPU SDRAM ZCLK AGPCLK PCI FS4 FS3 FS2 FS1 FS0 CPU SDRAM ZCLK AGPCLK PCI
(MHz) (MHz) (MHz) (MHz) (MHz) (MHz) (MHz) (MHz) (MHz) (MHz)
0 0 0 0 0 1 0 0 0 0
0 0 0 0 1 1 0 0 0 1
0 0 0 1 0 1 0 0 1 0
0 0 0 1 1 1 0 0 1 1
0 0 1 0 0 1 0 1 0 0
0 0 1 0 1 1 0 1 0 1
0 0 1 1 0 1 0 1 1 0
A 0
0
0
1
1
0
1
0
1
0
1
1
0
1
1
0
1
0
1
0
A
0 1 0 0 1 1 1 0 0 1
0 1 0 1 0 1 1 0 1 0
0 1 0 1 1 1 1 0 1 1 MICRO-STAR INT'L CO.,LTD.
0 1 1 0 0 1 1 1 0 0
0 1 1 0 1 1 1 1 0 1
0 1 1 1 0 1 1 1 1 0 Title
0 1 1 1 1 1 1 1 1 1 MAIN CLOCK GEN
Size Document Number Rev
B MS-6547 1.0A
Date: , 13, 2001 Sheet 3 of 39
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Clock Buffer (DDR)
D (OPTIONS)
D
1: (ICS-93705)
CP11 X_COPPER
VCC2.5V
L28
CBVDD
X_80_0805
By-Pass Capacitors
Place near to the Clock Buffer
CB126 CB127 CE5 + CB88 CB87 CB110 CB123 CB111
0.01u 0.1u 0.1u 0.1u 0.1u 0.1u
0.1u X_22u DDRCLK0 C58 X_10p
DDRCLK1 C59 X_10p
DDRCLK[0..8]
DDRCLK[0..8] 11,12
DDRCLK2 C62 X_10p
DDRCLK-[0..8]
DDRCLK-[0..8] 11,12
DDRCLK3 C64 X_10P
SMBCLK
SMBCLK 3,11,12,15,27
SMBDAT DDRCLK5 C65 X_10P
SMBDAT 3,11,12,15,27
U7 FWDSDCLKO DDRCLK4 C38 X_10P
FWDSDCLKO 8
93705CF
DDRCLK8 C39 X_10P
C CBVDD 15
C
VDDI2C DDRCLK7 C42 X_10P
4 VDD
11 VDD
21 DDRCLK6 C45 X_10P
VDD
28 VDD
34 VDD
CP14 X_COPPER 38 VDD R111 DDRCLK0 DDRCLK-0 C57 X_10P
45 3 0
VDD CLK0 R112 DDRCLK1
5 0
CLK1 R115 DDRCLK2 DDRCLK-1 C60 X_10P
10 0
L32 CLK2 R118 DDRCLK3
20 0
CLK3 R119 DDRCLK5 DDRCLK-2 C61 X_10P
16 22 0
VCC2.5V AVDD CLK4 R81 DDRCLK4
46 0
X_80_0805 CLK5
+ CE4 CB124 CB118 44 R82 0 DDRCLK8 DDRCLK-3 C63 X_10P
22u CLK6 R85 DDRCLK7
39 0
0.1u 0.01u CLK7 R89 DDRCLK6 DDRCLK-5 C66 X_10P
29 0
CLK8
17 AGND CLK9 27
DDRCLK-4 C37 X_10P
SMBCLK R116 0 12 2 R110 0 DDRCLK-0
SMBDAT SCLK CLK#0 R113 DDRCLK-1 DDRCLK-8 C40 X_10P
R86 0 37 6 0
SDATA CLK#1 R114 DDRCLK-2
9 0
FWDSDCLKO CLK#2 R117 DDRCLK-3 DDRCLK-7 C41 X_10P
13 19 0
CLK_IN CLK#3 R120 DDRCLK-5
23 0
CLK#4 R80 DDRCLK-4 DDRCLK-6 C44 X_10P
47 0
CLK#5 R83 DDRCLK-8
43 0
CLK#6 R84 DDRCLK-7
40 0
CLK#7 R88 DDRCLK-6
30 0
CLK#8
CLK#9 26
14
B NC
FB_OUT 33 R87 22 FB_OUT B
FB_OUT 35 32
FB_IN NC
C43
10p
36 NC
GND
GND