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ZZZ1 ZZZ2 ZZZ3 ZZZ4 ZZZ5 ZZZ6
DAZ 12.1W_PCB_LA5191P 12.1W_PCB_LS5191P 12.1W_PCB_LS5192P 12.1W_PCB_LS5193P 12.1W_PCB_LS5194P
Part Number = DA80000EF10 Part Number = DA60000C410 Part Number = DA40000K110 Part Number = DA40000K010 Part Number = DA20000GH10
1 1
KIUE0
2
Schematics Document 2
Mobile Penryn PGA with Intel
3 Cantiga_GM45+ICH9-M core logic 3
REV:1.0
4 4
Security Classification Compal Secret Data Compal Electronics,Ltd.
Issued Date Title
Deciphered Date
Cover Sheet
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KIUE0_LA-5191P
Date: Thursday, June 25, 2009 Sheet 1 of 43
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Compal confidential
Model Name : KIUE0 Mobile Penryn
File Name : LA-5191P
uPGA-478 CPU Clock Gen.
SLG8SP556VTR
TP Lock,HDD,Bettery Charging,Power LED on MB ICS9LPRS387AKLFT
1 CAPS ,NUM Lock,BT,Wlan,NOVO,Power LED on Sub-Brd page4,5,6 page16 1
H_A#(3..35) FSB
H_D#(0..63) 667/800/1066MHz
CRT Conn DDR3-800(1.5V)
DDR3-1067(1.5V)
page18
Intel Cantiga GMCH DDR3-SO-DIMM X2
GM45 BANK 0, 1, 2, 3 page 14,15
LCD Conn LVDS I/F uFCBGA 1329 Dual Channel UP TO 8G
page17 page 7,8,9,10,11,12,13
DMI 4
C-Link
PCIeMini Card PCIeMini Card USB
2
3G Reserve 5V 480MHz Intel ICH9-M USB 6
USB Right
USB port 0
Int. Camera
USB port 2
BT conn
USB port 6
2
USB port 3 USB port 8 PCIe 1x
page 29 page 29 5V 480MHz page 28 page 17 page 28
1.5V 2.5GHz(250MB/s)
PCIeMini Card PCIeMini Card mBGA-676
SATA port 1,5 CardReader FP conn USB Conn
SSD WLAN 5V 1.5GHz(150MB/s)
SATA port 1,5 PCIe port 3
USB port 7 USB port 9 USB port 11
page 29 page 29 page 25 page 33 page 28
SIM Card Express Card SATA port 0 SATA HDD0
page29
USB 5V 1.5GHz(150MB/s) page 23
USB port 10
5V 480MHz
Express Card PCIe 1x
page 29 1.5V 2.5GHz(250MB/s)
SATA port 4
PCIe port 4
5V 1.5GHz(150MB/s)
eSATA USB Left
RTL8111DL Giga PCIe 1x USB port 4 USB port 4
RJ45 page 23 page 23
page 24 1.5V 2.5GHz(250MB/s) 5V 480MHz
PCIe port 6 page 24 page 19,20,21,22
3 3
HD Audio 3.3V/24.576MHZ/48MHZ
Audio Codec
ALC272-GR
page26
Sub-Board List LPC BUS
EC Int MIC Conn
Finger Printer/B Switch/B ENE KB926D3 HP Conn
page31 page27
KB Light/B SPI ROM AMP-TPA6017
Power/B Int.KBD SPI BUS page30 page27
page32
4 4
2-CH SPK
Touch Pad G-SENSOR 1.5W X 2
page32 page28
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008/03/24 Deciphered Date 2008/04/ Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
MB Block Diagram
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KIUE0_LA-5191P
Date: Wednesday, June 24, 2009 Sheet 2 of 43
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Voltage Rails SIGNAL
STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5#
1 1
Power Plane Description S1 S3 S5 G3 Full ON HIGH HIGH HIGH HIGH
VIN Adapter power supply (19V) ON ON ON OFF S1(Power On Suspend) LOW HIGH HIGH HIGH
B+ AC or battery power rail for power circuit. ON ON ON OFF
S3 (Suspend to RAM) LOW LOW HIGH HIGH
+CPU_CORE Core voltage for CPU ON OFF OFF OFF
+0.75VS 0.75V switched power rail for DDR terminator ON OFF OFF OFF S4 (Suspend to Disk) LOW LOW LOW HIGH
+1.05VS 1.05V switched power rail ON OFF OFF OFF
S5 (Soft OFF) LOW LOW LOW LOW
+1.5VS 1.5V switched power rail ON OFF OFF OFF
+1.5V 1.8V power rail for DDR ON ON OFF OFF G3 LOW LOW LOW LOW
+3VALW 3.3V always on power rail ON ON ON OFF
VL 3.3V always on power rail ON ON ON ON
+3V_SB 3.3V power rail for LAN ON ON OFF OFF
+3V_LAN 3.3V power rail for LAN ON ON OFF OFF
+3V_WLAN 3.3V power rail for LAN ON ON OFF OFF BTO Option Table
+3VS 3.3V switched power rail ON OFF OFF OFF
+5VALW 5V always on power rail ON ON ON OFF
Function CRT LAN Finger printer BLUE TOOTH 3G SIM slot Mini card
2
+5VL 5V always on power rail ON ON ON ON 2
+5V_SB 5V power rail for SB ON ON OFF OFF description (Q) (C) (F) (B) (3) (D2)
+5VS 5V switched power rail ON OFF OFF OFF
+VSB VSB always on power rail ON ON ON OFF
explain
+RTCVCC RTC power ON ON ON ON BTO
+GPU_CORE Core voltage for VGA chip ON ON OFF OFF
+1.8VS 1.8V power rail for NB ON OFF OFF OFF
External PCI Devices
EC SM Bus1 address EC SM Bus2 address
Power Device Address Power Device Address
3 3
+3VALW EC KB926 D3 +3VALW EC KB926 D3
+3VALW Smart Battery CPU THM Sen
+3VALW SMSC SMC1402
ICH9M SM Bus address
Power Device Address
+3V_SB ICH9M
Clock Generator
+3VS (SLG8SP556V)
+3VS DDR DIMM0
+3VS DDR DIMM1
4 Express 4
+3VS
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008/03/24 Deciphered Date 2008/04/ Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
MB Notes List
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KIUE0_LA-5191P
Date: Wednesday, June 24, 2009 Sheet 3 of 43
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5 4 3 2 1
ME@
JCPU1A
H_A#3 J4 H1 H_ADS#
7 H_A#[3..16] A[3]# ADS# H_ADS# 7 +1.05VS
ADDR GROUP_0
H_A#4 L5 E2 H_BNR#
A[4]# BNR# H_BNR# 7
H_A#5 L4 G5 H_BPRI#
A[5]# BPRI# H_BPRI# 7
H_A#6 K5 H_IERR# R1 1 2 56_0402_5%
H_A#7 A[6]# H_DEFER#
M3 A[7]# DEFER# H5 H_DEFER# 7
D H_A#8 N2 F21 H_DRDY# H_PROCHOT# R2 1 2 68_0402_5% D
A[8]# DRDY# H_DRDY# 7
H_A#9 J1 E1 H_DBSY#
A[9]# DBSY# H_DBSY# 7
H_A#10 N3
H_A#11 A[10]# H_BR0#
P5 A[11]# BR0# F1 H_BR0# 7
H_A#12 P2 H_PROCHOT#
A[12]#
CONTROL
H_A#13 L2 D20 H_IERR#
H_A#14 A[13]# IERR# H_INIT#
P4 A[14]# INIT# B3 H_INIT# 20
H_A#15 P1
H_A#16 A[15]# H_LOCK# Q36
R1 A[16]# LOCK# H4 H_LOCK# 7
H_ADSTB#0 M1 2N7002_SOT23
7 H_ADSTB#0 ADSTB[0]# D
1
C1 H_RESET#
RESET# H_RESET# 7
H_REQ#0 K3 F3 H_RS#0 2 EC_PROCHOT EC_PROCHOT 31
7 H_REQ#0 REQ[0]# RS[0]# H_RS#0 7
H_REQ#1 H2 F4 H_RS#1 G
7 H_REQ#1 REQ[1]# RS[1]# H_RS#1 7
H_REQ#2 K2 G3 H_RS#2 S
7 H_REQ#2 H_RS#2 7
3
H_REQ#3 REQ[2]# RS[2]# H_TRDY#
7 H_REQ#3 J3 REQ[3]# TRDY# G2 H_TRDY# 7
H_REQ#4 L1
7 H_REQ#4 REQ[4]#
G6 H_HIT#
HIT# H_HIT# 7
H_A#17 Y2 E4 H_HITM#
A[17]# HITM# H_HITM# 7
H_A#18 U5
7 H_A#[17..35] A[18]#
H_A#19 R3 AD4 XDP_BPM#0
A[19]# BPM[0]#
ADDR GROUP_1
H_A#20 XDP_BPM#1
H_A#21
W6
U4
A[20]# BPM[1]# AD3
AD1 XDP_BPM#2
Hardware force mechanism for throttling
H_A#22 A[21]# BPM[2]# XDP_BPM#3
Y5 A[22]# BPM[3]# AC4
H_A#23 U1 AC2 XDP_BPM#4
XDP/ITP SIGNALS
H_A#24 A[23]# PRDY# XDP_BPM#5
R4 A[24]# PREQ# AC1
H_A#25 T5 AC5 XDP_TCK
H_A#26 A[25]# TCK XDP_TDI
T3 A[26]# TDI AA6
H_A#27 W2 AB3 XDP_TDO
H_A#28 A[27]# TDO XDP_TMS
W5 A[28]# TMS AB5
C H_A#29 Y4 AB6 XDP_TRST# C
H_A#30 A[29]# TRST# XDP_DBRESET# +3VS +3VS
U2 A[30]# DBR# C20 XDP_DBRESET# 21
H_A#31 V4
H_A#32 A[31]#
W3 A[32]#
1
H_A#33 AA4 THERMAL 1
H_A#34 A[33]# H_PROCHOT#
AB2 A[34]#
H_A#35 AA3 D21 C1 U1 R3 @
H_ADSTB#1 A[35]# PROCHOT# H_THERMDA 0.1U_0402_16V4Z 10K_0402_5%
7 H_ADSTB#1 V1 ADSTB[1]# THERMDA A24
H_THERMDC 2
B25
2
H_A20M# THERMDC EC_SMB_CK2
20 H_A20M# A6 A20M# 1 VDD SMCLK 8 EC_SMB_CK2 31
ICH
H_FERR# A5 C7 H_THERMTRIP#
20 H_FERR# FERR# THERMTRIP# H_THERMTRIP# 8,20
H_IGNNE# C4 H_THERMDA 2 7 EC_SMB_DA2
20 H_IGNNE# IGNNE# DP SMDATA EC_SMB_DA2 31
H_STPCLK# D5 1 2 H_THERMDC 3 6
20 H_STPCLK# STPCLK# DN ALERT#
H_INTR C6 H CLK C2 2200P_0402_50V7K
20 H_INTR LINT0
H_NMI B4 A22 CLK_CPU_BCLK THERM# 4 5
20 H_NMI LINT1 BCLK[0] CLK_CPU_BCLK 16 THERM# GND
H_SMI# A3 A21 CLK_CPU_BCLK#
20 H_SMI# SMI# BCLK[1] CLK_CPU_BCLK# 16
M4 RSVD[01] +3VS 1 2
N5 H_THERMDA, H_THERMDC routing together, R4 10K_0402_5% EMC1402-1-ACZL-TR_MSOP8
RSVD[02]
T2 RSVD[03] Trace width / Spacing = 10 / 10 mil
RSVD pins on the CPU V3
B2
RSVD[04]
RESERVED
RSVD[05]
should be left as NO D2
D22
RSVD[06]
RSVD[07]
CONNECT D3
F6
RSVD[08]
RSVD[09] Address:100_1100
B B
+5VS
Penryn FAN1 Conn C3 1 2 10U_0805_10V4Z
U2 +5VS
1 VEN GND 8
2 VIN GND 7
1
+VCC_FAN1 3 6
EN_FAN1 R5 1 VO GND
2 100_0402_5% 4 5 @
XDP Reserve for debug , Please close to CPU side 31 EN_FAN1
1
VSET
G996P11U_SO8
GND D1
1SS355TE-17_SOD323-2
C4
2
+3VS 2200P_0402_50V7K D2 1 2 @ BAS16_SOT23-3
2
XDP_DBRESET# R6 1 2 @ 1K_0402_5%
FAN +5VS DROOP +3VS
C5 1 2 1U_0603_10V4Z
1
+1.05VS C6 1 2 0.1U_0402_16V4Z
XDP_TDI R8 1 2 54.9_0402_1% R7 40mil
10K_0402_5% JFAN1
XDP_TMS R9 1 2 54.9_0402_1% +VCC_FAN1 1
2
1
31 FAN_SPEED1 2 2
XDP_TDO R10 1 2 @ 54.9_0402_1% 1 3 3
XDP_TRST# R11 1 2 54.9_0402_1% C7 4
1000P_0402_50V7K GND ME@
A 5 GND A
XDP_TCK R12 1 54.9_0402_1% 2
2
E&T_3801-F03N-01R
Security Classification Compal Secret Data Compal Electronics,Ltd.
Issued Date 2008/03/25 Deciphered Date 2008/04/ Title
Penryn(1/3)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev