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5 4 3 2 1
GIGABYTE XP-K8U-X Schematics REV:1.0 DATE: 94/04/04
SHEET TITLE SHEET TITLE
D D
1 COVER SHEET
2 BOM & PCB MODIFY HISTORY
3 BLOCK DIAGRAM
4,5,6,7 AMD K8 CLAWHAMMER
8 ~ 13 ULI M1689 SINGLE CHIP
14 CLOCK GENERATOR
15,16,17 DDR SDRAM DIMMS 1,2,3 & DDR Termination
C C
18 AGP SLOT
19,20 PCI SLOT 1,2,3,4,5
21 IDE , FRONT USB , SATA
22 SMSC LPC I/O
23 BIOS & FDD
24 AUDIO AC97
25 AUDIO JACK & GAMEPORT
B B
26 COM,PRT,KB/MS
27 RTL8100C & USB CONNECTOR
28 VCORE (PWM ISL6568CR)
29 FRONT PANEL
30 VCC12,VCC18,VCC25,VDDQ
31 ATX, DC POWER
COMPONENT SIDE
(0.5 oz. Copper)
VCC SIDE
32 DDR POWER(5VDUAL,3VDUAL,25VSTR,VTTDDR) (1 oz. Copper)
GND SIDE
A (1 oz. Copper) A
SOLDER SIDE
33 POWER SEQUENCE (0.5 oz. Copper)
34 R_USB , RESET AXPER
Title
COVER SHEET
35 H/W SETTING Size Document Number Rev
Custom 1.0
XP-K8U-X
Date: Thursday, July 21, 2005 Sheet 1 of 36
5 4 3 2 1
5 4 3 2 1
XP-K8U-X REV. 1.0 ULi M1689 single chip FOR AMD K8_754
Component value change history Circuit or PCB layout change for next version
Date Change Item Reason Date Change Item
D D
C C
B B
A A
Title
<br><br> Size Document Number Rev<br> CustomXP-K8U-X <RevCode><br><br> Date: Wednesday, May 11, 2005 Sheet 2 of 36<br> 5 4 3 2 1<br> 5 4 3 2 1<br><br><br><br><br> XP-K8U-X REV. 1.0 ULi M1689 single chip FOR AMD K8_754<br> Component value change history Circuit or PCB layout change for next version<br> Date Change Item Reason Date Change Item Reason<br>D 2005/04/04 Form GA-K8U REV:1.01 to AXPER XP-K8U-X REV:1.0 PCB Modify D<br> For RTCVDD AC plug off drop issue<br> 2005/05/11 FOR PVT<br><br><br><br><br>C C<br><br><br><br><br>B B<br><br><br><br><br>A A<br><br><br><br><br> AXPER<br> Title<br> BOM & PCB MODIFY HISTORY<br> Size Document Number Rev<br> Custom 1.0<br> XP-K8U-X<br> Date: Wednesday, May 11, 2005 Sheet 3 of 36<br> 5 4 3 2 1<br> 5 4 3 2 1<br><br><br><br><br> XP-K8U-X BLOCK DIAGRAM CPUCLKT<br> CPUCLKC<br> USBCLK<br><br><br> SMBDAT<br> System Block Diagram CLK66<br> SMBCLK<br><br>D DDR SDRAM CLOCK D<br><br> AMD K8 CLAWHAMMER GEN<br> LANCLK<br> DIMM 1 Rtt RTM360-803<br> FWH33<br> 25VSTR=2.5V SSTL-2 /<br> VCC12=1.2V 25VDDA=2.5V DDRVREF=1.25V PCICLK_F<br> VCC25=2.5V VTTDDR=1.25V P.15 Termination ICS950405 SB14CLK<br> 25VSTR=2.5V CPUVREF=1.25V PCICLK0<br> HT12B=1.2V<br> 25VSTR=2.5V PCICLK1 AUDIO14<br> P.4,5,6,7 VTTDDR=1.25V<br> P.17 PCICLK2<br> DIMM 2 LPC14CLK<br> PCICLK3<br> 25VSTR=2.5V<br> LDT DDRVREF=1.25V<br> P.15<br> PCICLK4<br> LINK LPC33 P.14<br><br><br><br> AGP 8X SLOT DIMM 3<br> VDDQ=1.5V 25VSTR=2.5V<br> GVREF_CG=0.35V or 0.75V DDRVREF=1.25V<br> P.16<br>C P.18 ULI M1689 C<br><br><br><br><br> VCC12=1.2V<br> VDDQ=1.5V<br> PCI SLOT 1~5 IDE 1,2 (ATA133)<br> P.19,20 VCC18=1.8V P.21<br> 3VDUAL=3.3V<br> REAR USB2.0 X4 18VSB=1.8V<br> SATA 1,2<br> FUSEPWR=5V VCC3=3.3V P.21<br> P.27,34<br> RTCVDD=3V<br><br> FRONT USB2.0 X4<br> FUSEPWR1=5V Analog Out<br> P.21<br> AVDD=5V<br> P.25<br> LAN RTL8100C AC'97_ALC 850<br>B VDD25=2.5V AVDD33=3.3V Analog In B<br> P.27 AVDD=5V<br> P.8,9,10 P.24 AVDD=5V<br> P.25<br> P.11,12,13<br><br> 3D Audio Out<br> LPC<br> AVDD=5V<br> Bus P.25<br><br><br><br> SMSC VOLTAGE MONITOR SPDIF<br> P.22<br> LPC47M997 P.25<br> TEMPERATURE MONITOR<br> FWH 5VSB=5V P.22<br> BIOS P.22<br> P.23<br><br><br><br><br>A A<br><br><br><br> IR SERIAL PARALLEL FLOPPY GAME PORT KEYBOARD/MOUSE<br> P.22 P.26 P.26 P.23 P.23<br> 5VDUAL=5V<br> FUSEVCC=5V<br> AXPER<br> P.26 Title<br> BLOCK DIAGRAM<br> Size Document Number Rev<br> Custom 1.0<br> XP-K8U-X<br> Date: Wednesday, May 11, 2005 Sheet 4 of 36<br> 5 4 3 2 1<br> 5 4 3 2 1<br><br><br><br><br> Clawhammer HT Interface<br>D D<br><br><br><br><br> VCC12 HT12B<br> SOCKET_754A HT12B<br><br> D29 VLDT0_A6 VLDT0_B6 AH29<br> D27 VLDT0_A5 VLDT0_B5 AH27<br> HT12B D25 AG28 C1<br> VLDT0_A4 VLDT0_B4 10U/8/X5/6.3V<br> C28 VLDT0_A3 VLDT0_B3 AG26<br> C26 VLDT0_A2 VLDT0_B2 AF29<br> B29 VLDT0_A1 VLDT0_B1 AE28<br> B27 VLDT0_A0 VLDT0_B0 AF25<br> R1 49.9/6/1 L0_CADIN_H15 T25 L0_CADIN_H15 L0_CADOUT_H15 N26 L0_CADOUT_H15 Near CPU side on Top side<br> R2 49.9/6/1 L0_CADIN_L15 R25 N27 L0_CADOUT_L15<br> R3 49.9/6/1 L0_CADIN_H14 L0_CADIN_L15 L0_CADOUT_L15 L0_CADOUT_H14<br> U27 L0_CADIN_H14 L0_CADOUT_H14 L25<br> R4 49.9/6/1 L0_CADIN_L14 U26 M25 L0_CADOUT_L14<br> R5 49.9/6/1 L0_CADIN_H13 L0_CADIN_L14 L0_CADOUT_L14 L0_CADOUT_H13<br> V25 L0_CADIN_H13 L0_CADOUT_H13 L26<br> R6 49.9/6/1 L0_CADIN_L13 U25 L27 L0_CADOUT_L13<br> R7 49.9/6/1 L0_CADIN_H12 L0_CADIN_L13 L0_CADOUT_L13 L0_CADOUT_H12<br> W27 L0_CADIN_H12 L0_CADOUT_H12 J25<br> R8 49.9/6/1 L0_CADIN_L12 W26 K25 L0_CADOUT_L12<br> R9 49.9/6/1 L0_CADIN_H11 L0_CADIN_L12 L0_CADOUT_L12 L0_CADOUT_H11<br> AA27 L0_CADIN_H11 L0_CADOUT_H11 G25<br> R10 49.9/6/1 L0_CADIN_L11 AA26 H25 L0_CADOUT_L11<br> R11 49.9/6/1 L0_CADIN_H10 L0_CADIN_L11 L0_CADOUT_L11 L0_CADOUT_H10<br>C AB25 L0_CADIN_H10 L0_CADOUT_H10 G26 C<br> R12 49.9/6/1 L0_CADIN_L10 AA25 G27 L0_CADOUT_L10<br> R13 49.9/6/1 L0_CADIN_H9 L0_CADIN_L10 L0_CADOUT_L10 L0_CADOUT_H9<br> AC27 L0_CADIN_H9 L0_CADOUT_H9 E25<br> R14 49.9/6/1 L0_CADIN_L9 AC26 F25 L0_CADOUT_L9<br> R15 49.9/6/1 L0_CADIN_H8 L0_CADIN_L9 L0_CADOUT_L9 L0_CADOUT_H8<br> AD25 L0_CADIN_H8 L0_CADOUT_H8 E26<br> R16 49.9/6/1 L0_CADIN_L8 AC25 E27 L0_CADOUT_L8<br> L0_CADIN_H7 L0_CADIN_L8 L0_CADOUT_L8 L0_CADOUT_H7<br> T27 L0_CADIN_H7 L0_CADOUT_H7 N29<br> L0_CADIN_L7 T28 P29 L0_CADOUT_L7<br> L0_CADIN_H6 L0_CADIN_L7 L0_CADOUT_L7 L0_CADOUT_H6<br> V29 L0_CADIN_H6 L0_CADOUT_H6 M28<br> L0_CADIN_L6 U29 M27 L0_CADOUT_L6<br> L0_CADIN_H5 L0_CADIN_L6 L0_CADOUT_L6 L0_CADOUT_H5<br> V27 L0_CADIN_H5 L0_CADOUT_H5 L29<br> L0_CADIN_L5 V28 M29 L0_CADOUT_L5 L0_CADIN_L[0..7]<br> L0_CADIN_L5 L0_CADOUT_L5 L0_CADIN_L[0..7] (9)<br> L0_CADIN_H4 Y29 K28 L0_CADOUT_H4<br> L0_CADIN_L4 L0_CADIN_H4 L0_CADOUT_H4 L0_CADOUT_L4 L0_CADIN_H[0..7]<br> W29 L0_CADIN_L4 L0_CADOUT_L4 K27 L0_CADIN_H[0..7] (9)<br> L0_CADIN_H3 AB29 H28 L0_CADOUT_H3<br> L0_CADIN_L3 L0_CADIN_H3 L0_CADOUT_H3 L0_CADOUT_L3 L0_CADOUT_L[0..15]<br> AA29 L0_CADIN_L3 L0_CADOUT_L3 H27 L0_CADOUT_L[0..15] (9)<br> L0_CADIN_H2 AB27 G29 L0_CADOUT_H2<br> L0_CADIN_L2 L0_CADIN_H2 L0_CADOUT_H2 L0_CADOUT_L2 L0_CADOUT_H[0..15]<br> AB28 L0_CADIN_L2 L0_CADOUT_L2 H29 L0_CADOUT_H[0..15] (9)<br> L0_CADIN_H1 AD29 F28 L0_CADOUT_H1<br> L0_CADIN_L1 L0_CADIN_H1 L0_CADOUT_H1 L0_CADOUT_L1 L0_CLKOUT_L[0..1]<br> AC29 L0_CADIN_L1 L0_CADOUT_L1 F27 L0_CLKOUT_L[0..1] (9)<br> HT12B L0_CADIN_H0 AD27 E29 L0_CADOUT_H0<br> L0_CADIN_L0 L0_CADIN_H0 L0_CADOUT_H0 L0_CADOUT_L0 L0_CLKOUT_H[0..1]<br> AD28 L0_CADIN_L0 L0_CADOUT_L0 F29 L0_CLKOUT_H[0..1] (9)<br> R17 49.9/6/1 L0_CLKIN_H1 Y25 J26 L0_CLKOUT_H1<br> R18 49.9/6/1 L0_CLKIN_L1 L0_CLKIN_H1 L0_CLKOUT_H1 L0_CLKOUT_L1<br> W25 L0_CLKIN_L1 L0_CLKOUT_L1 J27<br> L0_CLKIN_H0 Y27 J29 L0_CLKOUT_H0<br> (9) L0_CLKIN_H0 L0_CLKIN_H0 L0_CLKOUT_H0<br> L0_CLKIN_L0 Y28 K29 L0_CLKOUT_L0<br> HT12B L0_CLKIN_L0<br> (9) L0_CLKIN_L0 L0_CLKOUT_L0<br> R19 49.9/6/1 L0_CTLIN_H1 R27 N25<br>B L0_CTLIN_H1 L0_CTLOUT_H1 B<br> R20 49.9/6/1 L0_CTLIN_L1 R26 P25<br> HOLE5<br> HOLE6<br> HOLE1<br> HOLE2<br> HOLE3<br> HOLE4<br> L0_CTLIN_H0 L0_CTLIN_L1 L0_CTLOUT_L1 L0_CTLOUT_H0<br> (9) L0_CTLIN_H0 T29 L0_CTLIN_H0 L0_CTLOUT_H0 P28 L0_CTLOUT_H0 (9)<br> L0_CTLIN_L0 R29 P27 L0_CTLOUT_L0<br> (9) L0_CTLIN_L0 L0_CTLIN_L0 L0_CTLOUT_L0 L0_CTLOUT_L0 (9)<br> 1<br> 2<br> 17<br> 18<br> 19<br> 20<br> HYPER TRANSPORT - LINK0<br><br><br><br><br> VCC12<br> VCC12 VCC12<br><br><br><br> 1 C292 C293 C285 C286 C287 C288 C289 C290<br> C2 C3 + EC1 0.22U/4/X/6.3V 0.22U/4/X/6.3V 0.22U/4/X/6.3V 0.22U/4/X/6.3V 0.22U/4/X/6.3V 0.22U/4/X/6.3V 0.22U/4/X/6.3V 0.22U/4/X/6.3V<br> 10U/8/X5/6.3V/X 22U/12/Y/10V 100U/D/10V/57/X<br><br> VCORE<br><br> Near CPU side<br><br>A COUPON1 COUPON1 1 A<br> 2 COUPON/X<br> VCC12 COUPON2 COUPON2 1 2 COUPON/X VCC<br><br> IMPEDENCE TESTING COUPON<br> C4 C5 C6 C7<br> AXPER<br> 1U/6/Y/16V 1U/6/Y/16V/X 1U/6/Y/16V/X 0.22U/4/X/6.3V Title<br> K8 SOCKET 754-1<br> Size Document Number Rev<br> Custom 1.0<br> XP-K8U-X<br> Date: Wednesday, May 11, 2005 Sheet 5 of 36<br> 5 4 3 2 1<br> 5 4 3 2 1<br><br><br><br><br> Place a cap every 0.5 in. on VTTDDR traces between CPU and DDR.<br> MD[0..63]<br> MD[0..63] (17)<br> MAA[0..13]<br> MAA[0..13] (15,17)<br> -DQS[0..17]<br> -DQS[0..17] (17)<br> VTTDDR<br> R21 51.1/6/1/X SOCKET_754B VTTDDR<br> VTTDDR<br> VTTDDR_SENSE AE13 D17<br> (32) VTTDDR_SENSE VTT_SENSE VTT_A4<br>D A18 D<br> CPUVREF VTT_A1 C8 C9 C10 C11 C12<br> VTT_A2 B17<br> CPUVREF AG12 C17 0.22U/4/X/6.3V 0.22U/4/X/6.3V 0.22U/4/X/6.3V/X 0.22U/4/X/6.3V/X 0.22U/4/X/6.3V/X<br> MEMVREF1 VTT_A3<br> VTT_B1 AF16<br> R22 10/6/1 MEMZN D14 AG16<br> 25VSTR MEMZN VTT_B2<br> R23 10/6/1 MEMZP C14 AH16<br> MEMZP VTT_B3 VTTDDR<br> VTT_B4 AJ17<br><br> MEMRESET_L AG10<br> MAB[0..13] AE8 MEMCKEA<br> MAB[0..13] (15,16,17) MEMCKEA MEMCKEA (15,16,17)<br> AE7 MEMCKEB C13 C14 C15 C16 C17<br> MEMCHECK[0..7] MEMCKEB MEMCKEB (15,16,17)<br> MD63 A16 0.22U/4/X/6.3V 0.22U/4/X/6.3V/X 0.22U/4/X/6.3V/X 0.1U/4/Y/16V 0.1U/4/Y/16V/X<br> MEMCHECK[0..7] (17) MEMDATA63<br> MD62 B15 D10 DCLK7<br> MEMBANKA[0..1] MEMDATA62 MEMCLK_H7 DCLK7 (15,17)<br> MD61 A12 C10 -DCLK7<br> MEMBANKA[0..1] (15,17) MEMDATA61 MEMCLK_L7 -DCLK7 (15,17)<br> MD60 B11 E12<br> MEMBANKB[0..1] MD59 MEMDATA60 MEMCLK_H6 VTTDDR<br> MEMBANKB[0..1] (15,16,17) A17 MEMDATA59 MEMCLK_L6 E11<br> MD58 A15 AF8 DCLK5<br> -CS[0..5] MEMDATA58 MEMCLK_H5 DCLK5 (15,17)<br> MD57 C13 AG8 -DCLK5<br> -CS[0..5] (15,16,17) MEMDATA57 MEMCLK_L5 -DCLK5 (15,17)<br> MD56 A11 AF10<br> MD55 MEMDATA56 MEMCLK_H4<br> A10 MEMDATA55 MEMCLK_L4 AE10<br> MD54 B9 V3 C18 C19 C20 C21<br> MD53 MEMDATA54 MEMCLK_H3 100P/4/N/50V/X 100P/4/N/50V/X 1n/4/X/50V 1n/4/X/50V/X<br> C7 MEMDATA53 MEMCLK_L3 V4<br> MD52 A6 K5<br> MD51 MEMDATA52 MEMCLK_H2<br> C11 MEMDATA51 MEMCLK_L2 K4<br> MD50 A9 R5 DCLK1<br> MEMDATA50 MEMCLK_H1 DCLK1 (16,17)<br> MD49 A5 P5 -DCLK1<br> MEMDATA49 MEMCLK_L1 -DCLK1 (16,17)<br><br> Locate close to CPU socket<br> MD48 B5 P3 DCLK0<br> MEMDATA48 MEMCLK_H0 DCLK0 (15,17)<br>C MD47 C5 P4 -DCLK0 C<br> MEMDATA47 MEMCLK_L0 -DCLK0 (15,17)<br> MD46 A4<br> MD45 MEMDATA46<br> E2 MEMDATA45 MEMCS_L7 D8<br> MD44 E1 C8 VTTDDR<br> MD43 MEMDATA44 MEMCS_L6 -CS5<br> A3 MEMDATA43 MEMCS_L5 E8<br> MD42 B3 E7 -CS4<br> MD41 MEMDATA42 MEMCS_L4 -CS3<br> E3 MEMDATA41 MEMCS_L3 D6<br> MD40 F1 E6 -CS2<br> MD39 MEMDATA40 MEMCS_L2 -CS1 C22 C23 C24 C25 C26 C27<br> G2 MEMDATA39 MEMCS_L1 C4<br> MD38 G1 E5 -CS0 10U/8/X5/6.3V 10U/8/X5/6.3V/X 10U/8/X5/6.3V/X 10U/8/X5/6.3V 10U/8/X5/6.3V/X 10U/8/X5/6.3V<br> MD37 MEMDATA38 MEMCS_L0<br> L3 MEMDATA37<br> MD36 L1 H5 -SRASA<br> MEMDATA36 MEMRASA_L -SRASA (15,17)<br> MD35 G3 D4 -SCASA<br> MEMDATA35 MEMCASA_L -SCASA (15,17)<br> MD34 J2 G5 -SWEA<br> MEMDATA34 MEMWEA_L -SWEA (15,17)<br> MD33 L2<br> MD32 MEMDATA33 MEMBANKA1 VTTDDR VTTDDR<br> M1 MEMDATA32 MEMBANKA1 K3<br> MD31 W1 H3 MEMBANKA0<br> MD30 MEMDATA31 MEMBANKA0<br> W3 MEMDATA30<br> MD29 AC1 E13<br> MD28 MEMDATA29 RSVD_MEMADDA15<br> AC3 MEMDATA28 RSVD_MEMADDA14 C12<br> MD27 W2 E10 MAA13 C28 C29<br><br><br><br><br> +<br> MD26 MEMDATA27 MEMADDA13 MAA12 10U/8/X5/6.3V 10U/8/X5/6.3V EC2 C299<br> Y1 MEMDATA26 MEMADDA12 AE6<br> MD25 AC2 AF3 MAA11 1000U/D/6.3V/8C 22U/12/Y/10V<br> MD24 MEMDATA25 MEMADDA11 MAA10<br> AD1 MEMDATA24 MEMADDA10 M5<br> MD23 AE1 AE5 MAA9<br> MD22 MEMDATA23 MEMADDA9 MAA8<br> AE3 MEMDATA22 MEMADDA8 AB5<br> MD21 AG3 AD3 MAA7<br> MD20 MEMDATA21 MEMADDA7 MAA6<br> AJ4 MEMDATA20 MEMADDA6 Y5<br> MD19 AE2 AB4 MAA5<br>B MEMDATA19 MEMADDA5 B<br> MD18 AF1 Y3 MAA4<br> MEMDATA18 MEMADDA4<br> CPUVREF<br> MD17 AH3 V5 MAA3<br> MD16 MEMDATA17 MEMADDA3 MAA2<br> AJ3 MEMDATA16 MEMADDA2 T5<br> MD15 AJ5 T3 MAA1<br> MD14 MEMDATA15 MEMADDA1 MAA0 25VSTR<br> AJ6 MEMDATA14 MEMADDA0 N5<br> MD13 AJ7<br> MD12 MEMDATA13 -SRASB<br> AH9 MEMDATA12 MEMRASB_L H4 -SRASB (15,16,17)<br> MD11 AG5 F5 -SCASB<br> MEMDATA11 MEMCASB_L -SCASB (15,16,17)<br> MD10 AH5 F4 -SWEB CPUVREF<br> MEMDATA10 MEMWEB_L -SWEB (15,16,17)<br> MD9 AJ9 R24 C30 C31<br> MEMDATA9<br> MD8<br> MD7<br> AJ10<br> AH11<br> MEMDATA8 MEMBANKB1 L5<br> J5<br> MEMBANKB1<br> MEMBANKB0 40 150/6/1 0.1U/4/Y/16V 10U/8/X5/6.3V<br> MEMDATA7 MEMBANKB0<br> MD6<br> MD5<br> AJ11 MEMDATA6 MAB15 TP15<br> MILS CPUVREF<br> AH15 MEMDATA5 RSVD_MEMADDB15 E14<br> MD4 AJ15 D12 MAB14 TP16<br> MD3 MEMDATA4 RSVD_MEMADDB14 MAB13 C32 C33 C34 R25<br> AG11 MEMDATA3 <br/><br/><br/>
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