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5 4 3 2 1
SYSTEM DC/DC
ISL62392 42
INPUTS OUTPUTS
5V_S5(6A)
JV71-M V Block Diagram
3D3V_S5(7A)
DCBATOUT
5V_AUX_S5
3D3V_AUX_S5
D
Project code: 91.4FX01.001 SYSTEM DC/DC D
TPS51124 43
PCB P/N : 48.4FX01.0SA
INPUTS OUTPUTS
SMSC REVISION : 09242 -1
CLK GEN. Mobile CPU EMC2102 DCBATOUT
1D05V_S0(9A)
1D5V_S3(12A)
ICS9LPRS365B Penryn 34
3 RT9026 44
4, 5 1D5V_S3
DDR_VREF_S3
(1.2A)
VRAM
HOST BUS 667/800/[email protected] 64MbX16X4 512M
RT9018 44
DDR2 Cantiga 1D5V_S3 1D1V_S0(2A)
800 MHz PCIex16 VGA HDMI
16,17 AGTL+ CPU I/F 20
DDR Memory I/F N10M-GS-B-A2-128
52~57
TPS51117 45
DDR2 INTEGRATED GRAHPICS LCD DCBATOUT FBVDD(4A)
LVDS, CRT I/F
18
800 MHz 16,17 6,7,8,9,10,11 CHARGER
CRT ISL88731A 47
X4 DMI 19
C-Link0
400MHz INPUTS OUTPUTS
C
CardBus MS/MS Pro/xD C
USB
RTS5159 /MMC/SD DCBATOUT BT+
31
CPU DC/DC
ISL6266A
ICH9M 41
6 PCIe ports INPUTS OUTPUTS
LINE IN PCI/PCI BRIDGE LAN
Giga LAN TXFM RJ45
ACPI 2.0 26 26
29 BCM5784 25 DCBATOUT VCC_CORE
4 SATA 38A
12 USB 2.0/1.1 ports
Int MIC ETHERNET (10/100/1000MbE) VGA_CORE
High Definition Audio RT8202A
47
18 Codec AZALIA LPC I/F
Serial Peripheral I/F INPUTS OUTPUTS
ALC888S
27 Matrix Storage Technology(DO)
DCBATOUT VGA_CORE
MIC In Active Managemnet Technology(DO) 13A
PCIe Mini 1 Card
29 Wire LAN 33 GFXCORE
ISL6263A
B
12,13,14,15 46 B
INT.SPKR
1.5W
OP AMP INPUTS OUTPUTS
MAX9789A
29 30 DCBATOUT VCC_GFXCORE
(7A)
LPC BUS
LINE OUT
29 USB SPI BIOS LPC PCB STACKUP
SATA Mini USB KBC (2MB)
Winbond 36 DEBUG
MODEM
HDD SATA Blue Tooth
23
Camera WPCE773 CONN.36
TOP L1
21 GND L2
RJ11 MDC Card 35
MEDIA
30 SATA USB KEY S L3
Finger 38 S L4
ODD SATA
Printer 37
4 Port 24
22 Touch INT. GND L5
Pad 37 KB 35 BOTTOM L6
A A
UMA
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
BLOCK DIAGRAM
Size Document Number Rev
A2
JV71 -2
Date: Thursday, July 02, 2009 Sheet 1 of 60
5 4 3 2 1
A B C D E
ICH9M Integrated Pull-up Cantiga chipset and ICH9M I/O controller
ICH9M Functional Strap Definitions Rev.1.5 page 92 Hub strapping configuration
ICH9 EDS 642879 and Pull-down Resistors Montevina Platform Design guide 22339
page 218
0.5
Signal Usage/When Sampled Comment ICH9 EDS 642879 Rev.1.5
HDA_SDOUT XOR Chain Entrance/ Allows entrance to XOR Chain testing when TP3 Pin Name Strap Description Configuration
PCIE Port Config1 bit1, pulled low.When TP3 not pulled low at rising edge SIGNAL Resistor Type/Value
Rising Edge of PWROK of PWROK,sets bit1 of RPC.PC(Config Registers: CL_CLK[1:0] PULL-UP 20K CFG[2:0] FSB Frequency 000 = FSB1067
offset 224h). This signal has weak internal pull-down Select 011 = FSB667
CL_DATA[1:0] PULL-UP 20K 010 = FSB800
others = Reserved
4 HDA_SYNC PCIE config1 bit0,
Rising Edge of PWROK.
This signal has a weak internal pull-down.
Sets bit0 of RPC.PC(Config Registers:Offset 224h)
CL_RST0# PULL-UP 20K
CFG[4:3] Reserved
4
DPRSLPVR/GPIO16 PULL-DOWN 20K CFG8
GNT2#/ PCIE config2 bit2, This signal has a weak internal pull-up. CFG[15:14]
GPIO53 Rising Edge of PWROK. Sets bit2 of RPC.PC2(Config Registers:Offset 0224h) ENERGY_DETECT PULL-UP 20K CFG[18:17]
GPIO20 Reserved This signal should not be pulled high. HDA_BIT_CLK PULL-DOWN 20K
CFG5 DMI x2 Select 0 = DMI x2
GNT1#/ ESI Strap (Server Only) ESI compatible mode is for server platforms only. HDA_DOCK_EN#/GPIO33 PULL-UP 20K 1 = DMI x4 (Default)
GPIO51 Rising Edge of PWROK This signal should not be pulled low for desttop CFG6 iTPM Host 0= The iTPM Host Interface is enabled(Note2)
and mobile. HDA_RST# PULL-DOWN 20K Interface 1=The iTPM Host Interface is disalbed(default)
HDA_SDIN[3:0] PULL-DOWN 20K 0 = Transport Layer Security (TLS) cipher
Top-Block Sampled low:Top-Block Swap mode(inverts A16 for CFG7 Intel Management suite with no confidentiality
GNT3#/ Swap Override. all cycles targeting FWH BIOS space). HDA_SDOUT PULL-DOWN 20K engine Crypto strap 1 = TLS cipher suite with
GPIO55 Rising Edge of PWROK. Note: Software will not be able to clear the confidentiality (default)
Top-Swap bit until the system is rebooted HDA_SYNC PULL-DOWN 20K
0 = Reverse Lanes,15->0,14->1 ect..
without GNT3# being pulled down. GLAN_DOCK# The pull-up or pull-down active when configured for native CFG9 PCIE Graphics Lane 1= Normal operation(Default):Lane
GLAN_DOCK# functionality and determined by LAN controller Numbered in order
GNT0#: Boot BIOS Destination Controllable via Boot BIOS Destination bit GNT[3:0]#/GPIO[55,53,51] PULL-UP 20K
SPI_CS1#/ Selection 0:1. (Config Registers:Offset 3410h:bit 11:10). 0 = Enable (Note 3)
GPIO58 Rising Edge of PWROK. GNT0# is MSB, 01-SPI, 10-PCI, 11-LPC. GPIO[20] PULL-DOWN 20K CFG10 PCIE Loopback enable 1= Disabled (default)
Integrated TPM Enable, Sample low: the Integrated TPM will be disabled. GPIO[49] PULL-UP 20K 00 = Reserve
Rising Edge of CLPWROK Sample high: the MCH TPM enable strap is sampled CFG[13:12] XOR/ALL 10 = XOR mode Enabled
SPI_MOSI low and the TPM Disable bit is clear, the LDA[3:0]#/FHW[3:0]# PULL-UP 20K 01 = ALLZ mode Enabled (Note 3)
Integrated TPM will be enable. 11 = Disabled (default)
LAN_RXD[2:0] PULL-UP 20K
3 DMI Termination Voltage, The signal is required to be low for desktop LDRQ[0] PULL-UP 20K
CFG16 FSB Dynamic ODT 0 = Dynamic ODT Disabled
1 = Dynamic ODT Enabled (Default) 3
Rising Edge of PWROK. applications and required to be high for
GPIO49 mobile applications. LDRQ[1]/GPIO23 PULL-UP 20K 0 = Normal operation(Default):
CFG19 DMI Lane Reversal Lane Numbered in Order
PME# PULL-UP 20K
1 = Reverse Lanes
PCI Express Lane Signal has weak internal pull-up. Sets bit 27 PWRBTN# PULL-UP 20K DMI x4 mode[MCH -> ICH]:(3->0,2->1,1->2and0->3)
SATALED# Reversal. Rising Edge of MPC.LR(Device 28:Function 0:Offset D8) DMI x2 mode[MCH -> ICH]:(3->0,2->1)
of PWROK. SATALED# PULL-UP 15K
SPKR No Reboot. If sampled high, the system is strapped to the SPI_CS1#/GPIO58/CLGPIO6 PULL-UP 20K Digital Display Port 0 = Only Digital Display Port
Rising Edge of PWROK. "No Reboot" mode(ICH9 will disable the TCO Timer (SDVO/DP/iHDMI) or PCIE is operational (Default)
system reboot feature). The status is readable SPI_MOSI PULL-DOWN 20K CFG20 Concurrent with PCIe 1 =Digital display Port and PCIe are
via the NO REBOOT bit. operting simulataneously via the PEG port
SPI_MISO PULL-UP 20K
0 =No SDVO Card Present (Default)
TP3 XOR Chain Entrance. This signal should not be pull low unless using SPKR PULL-DOWN 20K SDVO_CTRLDATA SDVO Present
Rising Edge of PWROK. XOR Chain testing. 1 = SDVO Card Present
TACH_[3:0] PULL-UP 20K
0 = LFP Disabled (Default)
GPIO33/ Flash Descriptor Sampled low:the Flash Descriptor Security will be TP[3] PULL-UP 20K Local Flat Panel
HDA_DOCK Security Override Strap overridden. If high,the security measures will be L_DDC_DATA (LFP) Present 1= LFP Card Present; PCIE disabled
_EN# Rising Edge of PWROK in effect.This should only be enabled in manufacturing USB[11:0][P,N] PULL-DOWN 15K
environments using an external pull-up resister. NOTE:
1. All strap signals are sampled with respect to the leading edge of
the (G)MCH Power OK (PWROK) signal.
2. iTPM can be disabled by a 'Soft-Strap' option in the
2 Flash-decriptor section of the Firmware. This 'Soft-Strap' is 2
activated only after enabling iTPM via CFG6.
Only one of the CFG10/CFG/12/CFG13 straps can be enabled at any time.
1 UMA
1
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Reference
Size Document Number Rev
A3
JV71 -2
Date: Thursday, July 02, 2009 Sheet 2 of 60
A B C D E
3D3V_S0
3D3V_S0 1D05V_S0
1 R554 2 3D3V_VDD48_S0
0R0603-PAD
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Do Not Stuff
SCD1U16V2ZY-2GP
Do Not Stuff
Do Not Stuff
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SC4D7U6D3V3KX-GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
Do Not Stuff
C456 C457 C455 C450 C417 C435 C444 C436 C416 C430 C419 C445 C448 C454 C418
SC4D7U6D3V3KX-GP
Do Not Stuff
DY DY DY DY
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
DY
4 4
3D3V_S0 3D3V_VDD48_S0 1D05V_S0
3D3V_S0
CL=20pF