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5 4 3 2 1
Schematics Page Index (Title / Revision / Change Date)
Page Title of Schematics Page Rev. Date Page Title of Schematics Page Rev. Date
01 Schematics Page Index 2.0 08/24 36 AUDIO (MUTE) 2.0 08/24
02 Block Diagram 2.0 08/24 37 EXPRESS CARD/MDC 2.0 08/24
03 Yonah(HOST BUS) 1/2 2.0 08/24 38 PCI (PCI BUS) 2.0 08/24
D
04 Yonah(HOST BUS) 2/3 2.0 08/24 39 PCI ( ILINK) 2.0 08/24 D
05 Yonah(Power/Gnd) 3/3 2.0 08/24 40 PCI (MS-DUO/MDC) 2.0 08/24
06 CALISTOGA (HOST) 1/7 2.0 08/24 41 Button/LID Switch/EMI CAP 2.0 08/24
07 CALISTOG (DMI) 2/7 2.0 08/24 42 USB2.0 2.0 08/24
08 CALIST (GRAPHIC) 3/7 2.0 08/24 43 HOLE 2.0 08/24
09 CALISTOGA (DDRII) 4/7 2.0 08/24 44 Power Design Diagram 2.0 08/24
10 CALIST (POWER,VCC) 5/7 2.0 08/24 45 DCIN&Charger 2.0 08/24
11 CALIST (VCC CORE) 6/7 2.0 08/24 46 SYS Power (+3_3V/+5V) 2.0 08/24
12 CALIST (VSS) 7/7 2.0 08/24 47 SYS Power(+1_5V/+1_05V) 2.0 08/24
13 DDRII(SO-DIMM_0) 1/3 2.0 08/24 48 DDR2 Power(+1_8V/+0_9V) 2.0 08/24
14 DDRII(SO-DIMM_1) 2/3 2.0 08/24 49 CPU_Vcore ---MAX8771 2.0 08/24
15 DDRII(Termination) 3/3 2.0 08/24 50 Others power plan 2.0 08/24
16 LVDS 2.0 08/24 51 OVP protection 2.0 08/24
17 CRT 2.0 08/24 52 History ( 1 ) 2.0 08/24
18 LAN CONTROLL 2.0 08/24 53 History ( 2 ) 2.0 08/24
C C
19 LAN TRANSFORMER 2.0 08/24 54
20 CLOCK GEN 2.0 08/24 55
21 ICH7-M( PCI/USB ) 1/5 2.0 08/24 56
22 ICH7-M( LPC,IDE,SATA )2/5 2.0 08/24 57
23 ICH7-M( GPIO) 3/5 2.0 08/24 58
24 ICH7-M( POWER) 4/5 2.0 08/24 59
25 ICH7-M( GND) 5/5 2.0 08/24 60
26 SATA HDD/CD-ROM 2.0 08/24
27 EC+KBC 2.0 08/24
28 Flash ROM/X-Bus 2.0 08/24
29 LED/Touch PAD 2.0 08/24
30 Mini-PCIE Card 2.0 08/24
31 FAN 2.0 08/24
32 OIDE 2.0 08/24
B 33 AUDIO(CODEC & POWER) 2.0 08/24 B
34 AUDIO( AMP & HP & SPK) 2.0 08/24
35 AUDIO( EXTMIC) 2.0 08/24
P. Leader Check by Design by
A A
HON HAI Precision Ind. Co., Ltd.
Project Code & Schematics Subject: MS70 Main Board PCB P/N: (FUBAI) 1P-0068100-6011 FOXCONN
Title
Index Page
CCPBG - R&D Division
(NAN YA) 1P-0068200-6011
Size Document Number Rev
(HANSTAR) 1P-0068500-6011 A3 MS70-1-01 2.0
Date: Tuesday, August 22, 2006 Sheet 1 of 55
5 4 3 2 1
1 2 3 4 5 6 7 8
RAPTOR/MS70(CALISTOGA GM/GML Block Diagram)
CPU Clock Gen.
LVDS Yonah/Celeron M X,TAL
A WSXGA+ LVDS/VGA 9LPR321AKLF 14.318MHZ A
PAGE 16
Processor MLF64
VGA Micro-FCBGA-478 PAGE 20
D-type-15p (Socket 478 -pin Micro FCPGA)
PAGE 17 SO-DIMM 0
PAGE 3~5
Ext. Mic In 400/533
Jack FSB
533/667 MHZ MHZ
PAGE 35
DDR(II) 200 pin
HEAD PAGE 13
PHONE North Bridge
JACK SO-DIMM 1
PAGE 34 Calistoga 400/533 MHZ
400/533
ALC262 945GM
TPA6011A 400/533 MHZ
Codec 940GML MHZ
Int. Speaker AZALIA uFCBGA
1.0 Walt x 2
DDR(II) 200 pin
PAGE 34 PAGE 33 PAGE 6~12
B
PAGE 34 PAGE 14 B
MDC 1.5 Modem X4 DMI
12 pin
(Direct Media Interface)
RJ11 (T60M955.01)
PAGE 37
USB2.0 USB 2.0
33MHZ, 3.3V PCI BUS South Bridge PCIE
CONN.X2
PAGE 42
MS/MS DUO/SD
PAGE 40 TI PCI8402ZHK ICH7-M
CardReader USB2.0
652 BGA Mini-Card PCIE
iLINK
GHK 216 (T60H938.02 JP)
PCIE + USB2.0
PAGE 39~40
PAGE 39 PAGE 21~25 PAGE 30
LPC Oide
C
PAGE 32 C
Marvell 10/100
IDE ATA 100
SATA 1.5Gb/s
Netswap
Ethernet
PCI-E
ENE KB3910SFC1 Express Card
88E8036
RJ45 NS681601P
QFN-65 EC+KBC PCIE
PAGE 37
PAGE 19 PAGE 18 LQFP-176
PAGE 27 PATA SATA
ODD HDD
PWM PAGE 26 PAGE 26
XBUS SMB Channel 1
PS/2 SMB Channel 2
Thermal Sensor
BUTTON G781-1P8
Flash BIOS BATT CONN. (CPU/GMCH)
D
& LED FAN uSOP-8 D
Lid Switch Touchpad 1MB
PAGE 41 PAGE 31 PAGE 29 PAGE 29 PAGE 28 PAGE 45 PAGE 3
HON HAI Precision Ind. Co., Ltd.
FOXCONN
Title Block Diagram
CCPBG - R&D Division
Size Document Number Rev
Custom MS70-1-01 2.0
Date: Tuesday, August 22, 2006 Sheet 2 of 55
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
4,5,6,10,11,22,24,41,47,50,51 +1_05VRUN
U1A
6 H_A#[31..3]
H_A#3 J4 H1
A[3]# ADS# H_ADS# 6
H_A#4 L4 E2
A[4]# BNR# H_BNR# 6
H_A#5 M3 G5
A[5]# BPRI# H_BPRI# 6
H_A#6 K5 A[6]#
1
ADDR GROUP 0
H_A#7 M1 H5
A[7]# DEFER# H_DEFER# 6
H_A#8 N2 F21 R1
A[8]# DRDY# H_DRDY# 6
H_A#9 J1 E1
A[9]# DBSY# H_DBSY# 6
H_A#10 N3 56_J
H_A#11 A[10]#
A P5 F1 H_BREQ#0 6 0402 A
2
H_A#12 A[11]# BR0#
P2 A[12]#
H_A#13 H_IERR#
CONTROL
L1 A[13]# IERR# D20
H_A#14 P4 B3
A[14]# INIT# H_INIT# 22
H_A#15 P1
H_A#16 A[15]#
R1 A[16]# LOCK# H4 H_LOCK# 6
6 H_ADSTB#0 L2 ADSTB[0]# H_CPURST# 6
B1 4,5,6,10,11,22,24,41,47,50,51 +1_05VRUN
6 H_REQ#[4..0] RESET# H_RS#[2..0] 6
H_REQ#0 K3 F3 H_RS#0
H_REQ#1 REQ[0]# RS[0]# H_RS#1
H2 REQ[1]# RS[1]# F4
H_REQ#2 K2 G3 H_RS#2
H_REQ#3 REQ[2]# RS[2]#
J3 REQ[3]# TRDY# G2 H_TRDY# 6
H_REQ#4 L5 0402 150_J R2
REQ[4]# XDP_TDI
6 H_A#[31..3] HIT# G6 H_HIT# 6 2 1
H_A#17 Y2 E4
A[17]# HITM# H_HITM# 6
H_A#18 U5 0402 39_J R3
H_A#19 A[18]# XDP_BPM#0 XDP_TMS
R3 A[19]# BPM[0]# AD4 1 30MIL TP1 2 1
ADDR GROUP 1
H_A#20 W6 AD3 XDP_BPM#1 1
A[20]# BPM[1]# 30MIL TP2
Layout note: H_A#21 U4 AD1 XDP_BPM#2 1
A[21]# BPM[2]# 30MIL TP3
H_A#22 Y5 AC4 XDP_BPM#3 1
no stub on A[22]# BPM[3]# 30MIL TP4
XDP/ITP SIGNALS
H_A#23 U2 AC2 XDP_BPM#4 1
A[23]# PRDY# 30MIL TP5
H_STPCLK# H_A#24 R4 AC1 XDP_BPM#5 1 0402 27_J R4
A[24]# PREQ# 30MIL TP6
H_A#25 T5 AC5 XDP_TCK XDP_TCK 1 2
H_A#26 A[25]# TCK XDP_TDI
T3 A[26]# TDI AA6
H_A#27 W3 AB3 XDP_TDO 1 30MIL TP7 0402 680_J R5
H_A#28 A[27]# TDO XDP_TMS XDP_TRST#
W5 A[28]# TMS AB5 05/04 2 1
H_A#29 Y4 AB6 XDP_TRST#
H_A#30 A[29]# TRST# A0206
W2 A[30]# DBR# C20 1 30MIL TP8
H_A#31 Y1 Debug port not used .
B A[31]# PROCHOT# B
6 H_ADSTB#1 V4 D21
THERM
ADSTB[1]# PROCHOT#
A24 H_THERMDA resistors close to CPU.
THERMDA H_THERMDC
22 H_A20M# A6 A20M# THERMDC A25
22 H_FERR# A5 FERR#
C4 C7 PM_THRMTRIP#
22 H_IGNNE# IGNNE# THERMTRIP# PM_THRMTRIP# 7
R6
1 0_J 2 H_STPCLK#_R D5 PM_THRMTRIP#
22 H_STPCLK# STPCLK#
0402 C6
22 H_INTR LINT0 should connect to
H CLK
22 H_NMI B4 LINT1 BCLK[0] A22 CLK_CPU_BCLK 20
22 H_SMI# A3 SMI# BCLK[1] A21 CLK_CPU_BCLK# 20 ICH7-M and GMCH
1 TP_A32# AA1
without T-ing (No
TP9 30MIL RSVD[01]
1 TP_A33# AA4 T22 TP_EXTBREF 1 stub)
TP10 30MIL RSVD[02] RSVD[12] 30MIL TP11
1 TP_A34# AB2
TP12 30MIL RSVD[03]
1 TP_A35# AA3
TP13 30MIL RSVD[04]
TP_A36# TP_SPARE0
RESERVED
TP14 30MIL 1 M4 RSVD[05] RSVD[13] D2 1 30MIL TP15
1 TP_A37# N5 F6 TP_SPARE1 1
TP16 30MIL RSVD[06] RSVD[14] 30MIL TP17
1 TP_A38# T2 D3 TP_SPARE2 1
TP18 30MIL RSVD[07] RSVD[15] 30MIL TP19
1 TP_A39# V3 C1 TP_SPARE3 1
TP20 30MIL RSVD[08] RSVD[16] 30MIL TP21 +3VRUN 7,8,10,13,14,16,17,20,21,22,23,24,26,27,28,29,30,33,37,39,41,49,50
1 TP_APM0# B2 AF1 TP_SPARE4 1
TP22 30MIL RSVD[09] RSVD[17] 30MIL TP23
1 TP_APM1# C3 D22 TP_SPARE5 1 W/S:10/10 (microstrip)
TP24 30MIL RSVD[10] RSVD[18] 30MIL TP25
C23 TP_SPARE6 1
RSVD[19] 30MIL TP26
1 TP_HFPLL B25 C24 TP_SPARE7 1
TP27 30MIL RSVD[11] RSVD[20] 30MIL TP28
CPU_478P FOX_PZ47823-2743-01
A#[32-39], APM#[0-1]:
1
Leave escape routing
2
2
2
place close to thermal sensor R7
on for future
1
C R8 R9 R10 C
functionality 4.7K_J C1 4.7K_J 2.2K_J 2.2K_J
H_THERMDA 0402 0.1U_16V_M_B 0402 0402 0402
2
2
0402
1
1
1
1
C2
2200P_50V_K_B U2
0402 1 8 SMB_THRM_CLK 13,27
2
VCC SCL
ICH7M's GPIO12: VIL---> -0.5V ~ 0.8V 2 D+ SDA 7 SMB_THRM_DATA 13,27
VIH---> 2.0V ~ 3.3+0.5V H_THERMDC 3 6
4,5,6,10,11,22,24,41,47,50,51 +1_05VRUN D- ALERT# PM_THRM# 27
YONAH's PROCHOT#: VIL---> -0.1V ~ 0.3*VCCP 4 THERM# GND 5
VIH---> 0.7*VCCP ~ VCCP+0.1 23,27,49 OVT_EC# 1 2 R_OVT_EC#
R11 0402 0_J G781-1P8f
SM bus Address :
1
7,8,10,13,14,16,17,20,21,22,23,24,26,27,28,29,30,33,37,39,41,49,50 +3VRUN
1001101 = 9A
R12
22,27,28,45,46 +ECVCC For G781-1P8
68_J Place Thermal-Sensor near
1
0402
2