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A GREAT ER M EA SU R E O F C O N F I D E N C E the saved time to acquire significantly more
data, providing greater insight into produc-
tion processes.
In most cases, the structures being tested
in parallel are located within a single Test El-
ement Group (TEG). Even among leading-
edge IC manufacturers, very few have pro-
gressed to the point of testing structures in
different TEGs simultaneously. Implement-
ing parallel test involves using the paramet-
ric tester's controller to inter-leave execution
of the multiple tests in a way that maximizes
the use of processing time and test instru-
mentation capacity that would otherwise be
standing idle. With appropriate test struc-
tures design, this multi-threaded* approach
to test sequencing can reduce the execution
time for multiple tests on multiple structures
Parallel Parametric
to little more than the time needed to execute
the longest test in the sequence.
* Thread: The context and code path in which
Test Methodologies
program execution takes place, from start to
finish, through a series of tasks.
Parallel vs. Traditional
Sequential Mode Testing
To illustrate the throughput advantage
Randall Lee that parallel testing offers, it's helpful to
Keithley Instruments, Inc. contrast it with the traditional approach to
parametric test, in which each test in the
sequence must be completed before the next
Background Fundamentals of Parallel Testing one begins. The total test time for an indi-
The production of many electronic devic- The simplest definition of parallel para- vidual TEG is approximately the sum of the
es begins with wafer processing. In addition metric test is "an emerging strategy for test times for the individual test devices, plus
to CMOS ICs, this can include such diverse wafer-level testing that involves concur- any delays due to switching latencies, which
devices as RF components based on III-V rent execution of multiple tests on multiple can be significant.
compounds and chemical detectors based on scribe line test structures." This strategy can Today's parametric test systems can be
carbon nanotube (CNT) FETs. In both R&D help today's highly automated, 24/7 fabs equipped with up to eight source-measure
and production applications, there is a great maximize the throughput of their existing units (SMUs), although most systems have
deal of effort devoted to increasing device parametric test hardware, reduce their cost fewer installed. Nevertheless, consider a
test throughput in order to shorten the time of test, and lower ownership costs. Further- tester equipped with eight SMUs operating
to market and reduce costs. more, parallel test offers fabs the flexibility in sequential mode for simple tests such as
One way of doing this is to run tests in to choose whether they want to increase their measuring a resistor, which requires one
parallel on wafer test elements (as opposed to wafer test throughput dramatically, or use SMU for the two nodes. In this case, seven
testing devices sequentially) using automated
or semi-automated wafer probers connected Conpin Force V Delay Meas I Devint
Conpin Force V Delay Meas I Devint
to parametric test systems. This reduces Conpin Force V Delay Meas I Devint
Conpin Force V Delay Meas I Devint
overhead time and increases throughput by Conpin Force V Delay Meas I
using instruments that might otherwise sit Conpin Force V Delay Meas I
Devint
idle, waiting for a test routine to call them Conpin Force V Delay Meas I
4 DUT Parallel is approximately
into action. Two basic strategies exist for par- Conpin Force V Delay Meas I 3