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5 4 3 2 1
Sapporo 1.0 BLOCK DIAGRAM 14.318MHz
CPU CORE P38 CPU Thermal
Sensor Clock Generator
D Merom MAX6657 P04
CK505
D
+1.05V/+1.5V /+1.25V/+1.25VM P17
P37
478Pins
P35 (Micro-FCBGA) P4,P5
3VPCU/5VPCU
Ambient Light Sensor
667/800 MHz FSB
1.8V/SMDDR_VTERM/SMDR_VREF
P36
Cable Docking
BATT CHARGER LVDS
MAX8724/1908 P34 LCD Panel P18 1 TO 4 USB HUB
Crestline Singal Channel DDR2
DDR2-SODIMM1 P16 LINE IN
DISCHARGE R.G,B 1299 uFCBGA LINE OUT
P33 CRT port P27
RJ45
P7,P8,P9,P10,P11 CRT PORT
+3VM_LAN_SW/3V_S5/+3V_CK505/3VSUS/+3V SVIDEO OUT
P39 POWER JACK
C C
DMI
+5V/5VSUS P35
PCI-E
SATA/PATA WLAN MiniCard
HDD (1.8 inch) P28 P19
ICH8M PCI-E
PATA
DVD-ROM P28
USB 2.0 PCI BUS PCMCIA Controller LAN
USB PORT 0 P30 P12,P13,P14,P15 Ricoh 5C847 Intel Nineveh-MM
P20,P21
P24,P25
USB PORT 1(POWER
USB) P30
SMBUS PCMCIA /SMART CARD
P20 1394 P21
B RJ45 B
Bluetooth Module P30 P25
Accelerometer
LIS3LV02DL Azalia
FingerPrint(AES2501B)
P30 AMP
Audio AUDIO
3.3V LPC, 33MHz TPA6211A JACK
SPI CODEC
WWAN MiniCard P23 P23
P19 AD1981 P22,P23
SIM CARD AMP
P19 USB for Docking P32 MIC
SYSTEM JACK
TPM (1.2) BIOS TLV2462CDGKR
P23 P23
SLB9635
P31
SMSC KBC1070 MODEM RJ11
A A
P26 MDC 1.5 P30 JACK P30
PROJECT : OT2
FAN Track Keyboard Quanta Computer Inc.
P29 PointP29 P29 Size Document Number Rev
Custom System Block Diagram 1A
Date: Thursday, March 22, 2007 Sheet 1 of 42
5 4 3 2 1
5 4 3 2 1
INDEX Power & Ground
Control
Pg# Description NOTE Label ACTIVE Description Signal
VIN S0, S3, S4, S5.M0.M1.Moff AC ADAPTER (19V)
1 Schematic Block Diagram
MBAT S0, S3, S4, S5.M0.M1.Moff MAIN BATTERY + (10~17V)
2 System Information
D D
VCCRTC S0, S3, S4, S5.M0.M1.Moff RTC & KBC POWER (3_3V)
3 System Power Block Diagram
+15V S0, S3, S4, S5.M0.M1.Moff +15V
4-5 Merom CPU/THERMAL SENSOR
CPU_CORE S0 CPU CORE POWER (1.25/1.15V) VRON
7-11 Crestline_
+1.05V S0 FSB POWER (1.05V) MAIND
12-15 ICH8_M
+1.05VM M0.M1 IAMT_ON
16 DDR II SO-DIMM
+3V S0 MAIND
17 CLOCK GEN
3VSUS S0, S3 SUSON
18 LCD CONNECTOR / LCD PWR
3V_S5 S0, S3, S4, S5 S5_ON
19 WAN/WWAN /SIM CARD connector
3VPCU S0, S3, S4, S5.M0.M1.Moff ALWAYS POWER (3V)
20-21 CARDBUS CONTROLLER
+5V S0 MAIND
22-23 AUDIO CODEC / AUDIO JACK
C C
5VSUS S0, S3 SUSON
24-25 LAN/TRANSFORMER
5V_S5 S0, S3, S4, S5 S5_ON
26 KBC
5VPCU S0, S3, S4, S5.M0.M1.Moff ALWAYS POWER (5V)
27 CRT PORT
+1.5V S0 MAIND
28 HDD / CD-ROM
+1.5VM M0.M1 IAMT_ON
29 FAN,KB,LEDs,TRACK POINT
1.8VSUS S0, S3 DDR CORE POWER SUSON
30 USB,BLUE TOOTH,FINGER PRINT, MDC,TPM
+2.5V S0 MAINON
31 POWER SEQUENCE,BIOS
SMDDR_VTERM S0 DDR COMMAND & CONTROL PULL UP POWER MAINON
32 CABLE DOCKING
SMDDR_VREF S0, S3 DDR REF POWER SUSON
33 DISCHARGE
VDDA S0 AUDIO ANALOG POWER (5V) MAINON
B 34 -CHARGER(MAX1908/8724) B
+3V_CK505 M0.M1 IAMT_ON
35 MAX1999(3VPCU/5VPCU)
+3V_LAN_SW M0.M1 IAMT_ON
36 MAX1992(1.8VSUS/DDR_VTERM)
37 MAX1540 (+1.05V/+1.5V) +1.25V S0 MAIND
38 --MAX8736 +1.25VM M0.M1 IAMT_ON
39 +3VM/+3V_S5/1.25V_M
40 POWER SEQUENCE
PCI DEVICES IRQ ROUTING PCB STACK UP SM BUS
DEVICE IDSEL # REQ/GNT # PCI_INT LAYER 1 : TOP DEVICE ADDRESS BUS
LAYER 2 : GND
CLOCK GENERATOR
A
LAYER 3 : IN1 A
LAYER 4 : IN2 DDR II
LAYER 5 : VCC
Accelemter sensor
LAYER 6 : IN3 PROJECT : OT2
LAYER 7 : GND CHARGER Quanta Computer Inc.
LAYER 8 : BOT Size Document Number Rev
CPU THERMAL SENSOR Custom System Information 1A
Date: Thursday, March 22, 2007 Sheet 2 of 42
5 4 3 2 1
5 4 3 2 1
S5_ON
SYSTEM POWER BLOCK DIAGRAM S.W
3V_S5
MOS-FET
IAMT_ON
S.W
D
S.W MOS-FET +3V_CK505 D
Adaptor MOS-FET
IAMT_ON
3VPCU S.W
ALWAYS MOS-FET +3VM_LAN_SW
VIN
MAX1999 IAMT_ON
SC4215 +1.25VM
VIN
MAIND
S.W +3V
C
MOS-FET C
CHARGER 3VSUS
SUSD
MAX8724/1908
MAIND
+5V
+15V S.W
MOS-FET
SUSD 5VSUS
5VPCU
ALWAYS
SUSON
S.W MAINON
BATTERY MOS-FET
B
MAX1992 SMDDR_VTERM B
1.8VSUS TPS51100
SMDDR_VREF
MAINON
MAINON
SC4215 +1.25V
1.5V
VIN
MAX1540 MAIND
1.05V_M S.W
MOS-FET +1.05V
IAMAT_ON
VIN
MAINON
VRON
KBC_PW_ON S5_ON S5_OND
TC7SH08FU DISCHARGE
A A
SLP_S5# SUSON SUSD
TC7SH08FU DISCHARGE
CPU_VID[0..5]
SLP_S3# MAIND
HWPG MAX1907 TC7SH08FU DISCHARGE
CPU_CORE
DPRSLPVR
PROJECT : OT2
STP_CPU# Quanta Computer Inc.
Size Document Number Rev
Custom System pwr block diagram 1A
Date: Thursday, March 22, 2007 Sheet 3 of 42
5 4 3 2 1
1 2 3 4 5 6 7 8
H_ADS# (6)
H_A#[3..16] U21A H_D#[0..63] U21B H_D#[0..63]
(6) H_A#[3..16] (6) H_D#[0..63] H_D#[0..63] (6)
H_A#3 J4 H1 H_D#0 E22 Y22 H_D#32
A[3]# ADS# PAD T25 D[0]# D[32]#
H_A#4 L5 E2 H_D#1 F24 AB24 H_D#33
A[4]# BNR# H_BNR# (6) D[1]# D[33]#
H_A#5 L4 G5 H_D#2 E26 V24 H_D#34
A[5]# BPRI# H_BPRI# (6) D[2]# D[34]#
H_A#6 K5 H_D#3 G22 V26 H_D#35
H_A#7 A[6]# H_D#4 D[3]# D[35]# H_D#36
M3 A[7]# DEFER# H5 H_DEFER# (6) F23 D[4]# D[36]# V23
H_A#8 N2 F21 H_D#5 G25 T22 H_D#37
A[8]# DRDY# H_DRDY# (6) D[5]# D[37]#
H_A#9 J1 E1 H_D#6 E25 U25 H_D#38
A[9]# DBSY# H_DBSY# (6) D[6]# D[38]#
H_A#10 N3 H_D#7 E23 U23 H_D#39
A A[10]# H_BR0# (6) D[7]# D[39]# A
0
ADDR GROUP
DATA GRP 0
H_A#11 P5 F1 H_D#8 K24 Y25 H_D#40
DATA GRP 2
H_A#12 A[11]# BR0# R112 56 H_D#9 D[8]# D[40]# H_D#41
P2 A[12]# G24 D[9]# D[41]# W22
H_A#13 L2 D20 H_IERR# 1 2 +1.05V H_D#10 J24 Y23 H_D#42
CONTROL
H_A#14 A[13]# IERR# H_D#11 D[10]# D[42]# H_D#43
P4 A[14]# INIT# B3 H_INIT# (12) J23 D[11]# D[43]# W24
H_A#15 P1 H_D#12 H22 W25 H_D#44
H_A#16 A[15]# H_D#13 D[12]# D[44]# H_D#45
R1 A[16]# LOCK# H4 H_LOCK# (6) F26 D[13]# D[45]# AA23
M1 H_D#14 K22 AA24 H_D#46
(6) H_ADSTB#0 ADSTB[0]# D[14]# D[46]#
H_REQ#[0..4] C1 H_D#15 H23 AB25 H_D#47
(6) H_REQ#[0..4] RESET# H_RESET# (6) D[15]# D[47]#
H_REQ#0 K3 F3 J26 Y26
REQ[0]# RS[0]# H_RS#0 (6) (6) H_DSTBN#0 DSTBN[0]# DSTBN[2]# H_DSTBN#2 (6)
H_REQ#1 H2 F4 H26 AA26
REQ[1]# RS[1]# H_RS#1 (6) (6) H_DSTBP#0 DSTBP[0]# DSTBP[2]# H_DSTBP#2 (6)
H_REQ#2 K2 G3 H25 U22
REQ[2]# RS[2]# H_RS#2 (6) (6) H_DINV#0 DINV[0]# DINV[2]# H_DINV#2 (6)
H_REQ#3 J3 G2
REQ[3]# TRDY# H_TRDY# (6)
H_REQ#4 L1 H_D#[0..63] H_D#[0..63]
REQ[4]# (6) H_D#[0..63] H_D#[0..63] (6)
H_A#[17..35] G6 H_D#16 N22 AE24 H_D#48
(6) H_A#[17..35] HIT# H_HIT# (6) D[16]# D[48]#
H_A#17 Y2 E4 H_D#17 K25 AD24 H_D#49
A[17]# HITM# H_HITM# (6) D[17]# D[49]#
H_A#18 U5 H_D#18 P26 AA21 H_D#50
H_A#19 A[18]# XDP_BPM#0 H_D#19 D[18]# D[50]# H_D#51
R3 A[19]# BPM[0]# AD4 R23 D[19]# D[51]# AB22
H_A#20 W6 AD3 XDP_BPM#1 Layout Note: H_D#20 L23 AB21 H_D#52
A[20]# 1 BPM[1]# D[20]# D[52]#
ADDR GROUP
H_A#21 U4 AD1 XDP_BPM#2 H_D#21 M24 AC26 H_D#53
A[21]# BPM[2]# Place voltage D[21]# D[53]#
XDP/ITP SIGNALS
H_A#22 Y5 AC4 XDP_BPM#3 H_D#22 L22 AD20 H_D#54
A[22]# BPM[3]# D[22]# D[54]#
DATA GRP 1
H_A#23 U1 AC2 XDP_BPM#4 divider within H_D#23 M23 AE22 H_D#55
DATA GRP 3
H_A#24 A[23]# PRDY# XDP_BPM#5 H_D#24 D[23]# D[55]# H_D#56
R4 A[24]# PREQ# AC1 0.5" of GTLREF P25 D[24]# D[56]# AF23
H_A#25 T5 AC5 XDP_TCK H_D#25 P23 AC25 H_D#57
H_A#26 A[25]# TCK XDP_TDI pin H_D#26 D[25]# D[57]# H_D#58
T3 A[26]# TDI AA6 P22 D[26]# D[58]# AE21
H_A#27 W2 AB3 XDP_TDO H_D#27 T24 AD21 H_D#59
H_A#28 A[27]# TDO XDP_TMS +1.05V H_D#28 D[27]# D[59]# H_D#60
W5 A[28]# TMS AB5 R24 D[28]# D[60]# AC22
H_A#29 Y4 AB6 XDP_TRST# H_D#29 L25 AD23 H_D#61
H_A#30 A[29]# TRST# XDP_DBRESET# H_D#30 D[29]# D[61]# H_D#62
U2 A[30]# DBR# C20 XDP_DBRESET# (14,31) T25 D[30]# D[62]# AF22
2
H_A#31 V4 H_D#31 N25 AC23 H_D#63
H_A#32 A[31]# R105 75 R62 D[31]# D[63]#
B W3 A[32]# (6) H_DSTBN#1 L26 DSTBN[1]# DSTBN[3]# AE25 H_DSTBN#3 (6)
B
H_A#33 AA4 THERMAL 2 1 +1.05V 1K/F M26 AF24
A[33]# (6) H_DSTBP#1 DSTBP[1]# DSTBP[3]# H_DSTBP#3 (6)
H_A#34 AB2 N24 AC20
A[34]# (6) H_DINV#1 DINV[1]# DINV[3]# H_DINV#3 (6)
H_A#35 AA3 D21 H_PROCHOT#
A[35]# PROCHOT# H_PROCHOT# (39)
H_THERMDA V_CPU_GTLREF AD26 COMP0
1
T11 V1 ADSTB[1]# THERMDA A24 GTLREF COMP[0] R26
B25 H_THERMDC CPU_TEST1 C23 MISC U26 COMP1
(6) H_ADSTB#1 THERMDC TEST1 COMP[1]
2
A6 CPU_TEST2 D25 AA1 COMP2
(12) H_A20M# A20M# TEST2 COMP[2]
A5 C7 CPU_TEST3 C24 Y1 COMP3
(12) H_FERR# FERR# THERMTRIP# PM_THRMTRIP# (7,12) TEST3 COMP[3]
ICH
C4 R54 CPU_TEST4 AF26
(12) H_IGNNE# IGNNE# TEST4
2K/F CPU_TEST5 AF1 E5
TEST5 DPRSTP# H_DPRSTP# (7,12)
D5 H CLK CPU_TEST6 A26 B5
(12) H_STPCLK# STPCLK# TEST6 DPSLP# H_DPSLP# (12)
1
(12) H_INTR C6 LINT0 DPWR# D24 H_DPWR# (6)
B4 A22 CPU_BSEL0 B22 D6
(12) H_NMI LINT1 BCLK[0] CLK_CPU_BCLK (17) (17) CPU_BSEL0 BSEL[0] PWRGOOD H_PWRGOOD (12)
A3 A21 CPU_BSEL1 B23 D7
(12) H_SMI# SMI# BCLK[1] CLK_CPU_BCLK# (17) (17) CPU_BSEL1 BSEL[1] SLP# H_CPUSLP# (6)
CPU_BSEL2 C21 AE6
(17) CPU_BSEL2 BSEL[2] PSI# PSI# (39)
M4 RSVD[01]
N5 Merom Ball-out Rev 1a
RSVD[02]
T2 RSVD[03] DB1A:change for intel
V3
RESERVED
B2
RSVD[04] schematic
RSVD[05] R124 CPU_TEST3
C3 RSVD[06] PAD T92
D2