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Compal Confidential
Model Name : QILE1 & QILE2
File Name : LA-8131P, LA-8133P
BOM P/N:
A
QILE1: A
4319GG39L01 : SMT MB A8131 QILE1 DIS-N13P
4319GG39L02 : SMT MB A8131 QILE1 DIS GPU-N13M
4319GG39L03 : SMT MB A8131 QILE1 UMA
QILE2:
4319GJ39L01 : SMT MB A8133 QILE2 DIS-N13P
4319GJ39L02 : SMT MB A8133 QILE2 DIS GPU-N13M
4319GJ39L03 : SMT MB A8133 QILE2 UMA

Compal Confidential
B B

M/B Schematics Document
Intel Ivy Bridge Processor with DDRIII + Panther Point PCH
GPU nVIDIA N13M-GE1 / N13P-GL

C
2012-01-11 C

REV:1.0

D D

Security Classification Compal Secret Data
Title
Compal Electronics, Inc.
Issued Date 2011/07/12 Deciphered Date 2012/07/01
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Cover Sheet
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
LA-8133P 1 of 58
Friday, January 13, 2012 Sheet
1 2 3 4 5
A B C D E

ZZZ

LA8131P

DA_PCB
DA80000QL00 nVIDIA N13M-GE1
DDR3*4
VRAM 256M*16/
128M*16/64M*16 Intel
1
nVIDIA N13P-GL Memory Bus 1

DDR3*8 PCI-E X16 Ivy Bridge Dual Channel
VRAM 256M*16/ 1.5V DDR3 1600MHz
DDR3-SO-DIMM X2
rPGA 989 Socket Page 11~12
128M*16/64M*16 Page 24~32
37.5mm * 37.5mm

HDMI Connector Page 4~10
HDMI
Page 34 FDI x8
DMI x4
(UMA) 100MHz 2Channel Speaker
100MHz Page 35
5GB/s
CRT Connector 2.7GT/s
RGB Digital MIC
Page 33 HD Audio Audio Codec
Page 35
Intel CX20671-21Z CODEC

LVDS Connector LVDS
2

Page 32
Panther Point Page 35 Audio combo Jack 2

Page 35
PCI-E FCBGA 989 Sub-Board
Card Reader 25mm*25mm USB 2.0
cable CMOS Camera Page 32
Realtek RTS5229 HM76
SPI ROM USB 3.0
Page 36 SPI
BIOS 8M+4M SATA USB PORT 2.0 x 1(charger)
Page 13 Page 13~21
Realtek Page 39
RTL8111F(Giga) cable
Sub-Board
Page 40 LPC BUS Finger Printer
UPEK TCS5DA6C0 Page 40

RJ45 CONN EC TPM
ENE KBC9012 Page 40
3
Page 40 USB PORT 3.0 x 3 3

Page 41 Page 37
Sub-Board
Track Point G-Sensor
Page 39 Page 36 SATA3.0 HDD CONN Page 36

PCI Express USB(BT)
Click Pad Int.KBD Thermal Sensor SATA ODD CONN Page 36
Mini card Page 39 Page 39 Fintek F75303M Page 39
Slot 1 Page 38 PCI-E(WLAN) m-SATA CONN Page 38
WLAN/WiMAX/BT

PCI Express USB

Mini card SATA
4 Slot 2 Page 38
4

WWAN/mSATA

SIM Card Security Classification Compal Secret Data
Title
Compal Electronics, Inc.
Issued Date 2011/07/12 Deciphered Date 2012/07/01
Page 38 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Block Diagram
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
LA-8133P 2 of 58
Friday, January 13, 2012 Sheet
A B C D E
1 2 3 4 5

Voltage Rails
SIGNAL
STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock

+5VS Full ON HIGH HIGH HIGH HIGH ON ON ON ON
+3VS
power S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF
plane +1.5VS
+VCCP S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF
A +5VALW +CPU_CORE A
S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF
+B +1.5V +VGA_CORE
+3VM
+3VALW +VCC_GFXCORE_AXG
+1.05VM
+1.8VS
State +0.75VS
+1.05VS BOARD ID Table
Board ID PCB Revision
0 0.1
1 0.2
S0
O O O O O 2 0.3
M3 Supported
3 0.4
S3 O 4 0.5
O O O X M3 Supported
5 0.6
S5 S4/AC O 6
O O X X M3 Supported
7
S5 S4/ Battery only
X X X X
B B
S5 S4/AC & Battery
don't exist
X X X X
USB Port Table BOM Structure Table
3 External BTO Item BOM Structure
USB 2.0 Port USB Port Connector CONN@
EC SM Bus1 address EC SM Bus2 address 0 45 LEVEL 45@
UHCI0
1 USB 3.0 Port (Left Side) Unpop @
Device Address Device Address
Smart Battery 0001 011X b Thermal Sensor Fintek F75303M 1001_101xb
2 USB 3.0 Port (Left Side) nVidia DIS@
UHCI1
3 USB 3.0 Port (Left Side) INTEL DD3 M3 M3@
EHCI1
4 SIM Card Slot 3G@
USB3.0 UHCI2
5 Camera Intel UMA UMA@
PCH SM Bus address 6 VRAM Option X76@
UHCI3
7 Intel SBA SBA@
Device Address
DDR DIMM0 1001 000Xb
8 Intel AOAC AOAC@
UHCI4
DDR DIMM2 1001 010Xb
9 USB Port (Right Side) TPM TPM@
10 Mini Card(WLAN/BT) GPU N13M N13M@
EHCI2 UHCI5
11 FPR GPU N13P N13MP
C
12 Mini Card(WWAN) C
UHCI6
13 Blue Tooth

SMBUS Control Table
WLAN Thermal
SOURCE VGA BATT KE9012 SODIMM WWAN Sensor PCH

SMB_EC_CK1
SMB_EC_DA1
KB9012 X V
+3VALW
X X X X X
+3VALW
SMB_EC_CK2
SMB_EC_DA2
KB9012 X X X X X X V
+3VS
+3VALW
SMBCLK
SMBDATA
PCH X X X V
+3VS
V
+3VS
X X
+3VALW
SML0CLK
SML0DATA
PCH
+3VALW
X X X X X X X
SML1CLK
SML1DATA
PCH
+3VALW
V
+3VS
X V
+3VS
X X +3VS
V X
D D

Security Classification Compal Secret Data
Title
Compal Electronics, Inc.
Issued Date 2011/07/12 Deciphered Date 2012/07/01
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Notes List
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
LA-8133P 3 of 58
Friday, January 13, 2012 Sheet
1 2 3 4 5
1 2 3 4 5

A A
JCPU1A CONN@
J22 PEG_COMP R1 1 2 24.9_0402_1% +1.05VS PEG_ICOMPI and RCOMPO signals should be shorted and routed
PEG_ICOMPI
PEG_ICOMPO J21 with - max length = 500 mils - typical impedance = 43 mohms
(15) DMI_CRX_PTX_N0 B27 DMI_RX#[0] PEG_RCOMPO H22 PEG_ICOMPO signals should be routed with - max length = 500 mils
(15) DMI_CRX_PTX_N1 B25 DMI_RX#[1] - typical impedance = 14.5 mohms
(15) DMI_CRX_PTX_N2 A25 DMI_RX#[2] PCIE_CRX_GTX_N[0..15] (22)
(15) DMI_CRX_PTX_N3 B24 K33 PCIE_CRX_GTX_N0
DMI_RX#[3] PEG_RX#[0] PCIE_CRX_GTX_N1
PEG_RX#[1] M35
(15) DMI_CRX_PTX_P0 B28 L34 PCIE_CRX_GTX_N2
DMI_RX[0] PEG_RX#[2] PCIE_CRX_GTX_N3
(15) DMI_CRX_PTX_P1 B26 DMI_RX[1] PEG_RX#[3] J35
(15) DMI_CRX_PTX_P2 A24 J32 PCIE_CRX_GTX_N4

DMI
DMI_RX[2] PEG_RX#[4] PCIE_CRX_GTX_N5
(15) DMI_CRX_PTX_P3 B23 DMI_RX[3] PEG_RX#[5] H34
H31 PCIE_CRX_GTX_N6
PEG_RX#[6] PCIE_CRX_GTX_N7
(15) DMI_CTX_PRX_N0 G21 DMI_TX#[0] PEG_RX#[7] G33
E22 G30 PCIE_CRX_GTX_N8
(15) DMI_CTX_PRX_N1 DMI_TX#[1] PEG_RX#[8]
F21 F35 PCIE_CRX_GTX_N9 PEG Static Lane Reversal - CFG2 is for the 16x
(15) DMI_CTX_PRX_N2 DMI_TX#[2] PEG_RX#[9]
D21 E34 PCIE_CRX_GTX_N10
(15) DMI_CTX_PRX_N3 DMI_TX#[3] PEG_RX#[10]
E32 PCIE_CRX_GTX_N11
PEG_RX#[11] PCIE_CRX_GTX_N12
G22 D33 1: Normal Operation; Lane # definition matches
(15)
(15)
(15)
DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
D22
F20
DMI_TX[0]
DMI_TX[1]
DMI_TX[2]
PEG_RX#[12]
PEG_RX#[13]
PEG_RX#[14]
D31
B33
PCIE_CRX_GTX_N13
PCIE_CRX_GTX_N14
CFG2 * socket pin map definition
PCIE_CRX_GTX_N15

PCI EXPRESS* - GRAPHICS
(15) DMI_CTX_PRX_P3 C21 DMI_TX[3] PEG_RX#[15] C32
PCIE_CRX_GTX_P[0..15] (22) 0:Lane Reversed
J33 PCIE_CRX_GTX_P0
PEG_RX[0] PCIE_CRX_GTX_P1
PEG_RX[1] L35
K34 PCIE_CRX_GTX_P2
PEG_RX[2] PCIE_CRX_GTX_P3
(15) FDI_CTX_PRX_N0 A21 FDI0_TX#[0] PEG_RX[3] H35
H19 H32 PCIE_CRX_GTX_P4
(15) FDI_CTX_PRX_N1 FDI0_TX#[1] PEG_RX[4]
E19 G34 PCIE_CRX_GTX_P5
(15) FDI_CTX_PRX_N2 FDI0_TX#[2] PEG_RX[5]
F18 G31 PCIE_CRX_GTX_P6
(15) FDI_CTX_PRX_N3 FDI0_TX#[3] PEG_RX[6]

Intel(R) FDI
B21 F33 PCIE_CRX_GTX_P7
(15) FDI_CTX_PRX_N4 FDI1_TX#[0] PEG_RX[7]
C20 F30 PCIE_CRX_GTX_P8
(15) FDI_CTX_PRX_N5 FDI1_TX#[1] PEG_RX[8]
D18 E35 PCIE_CRX_GTX_P9
(15) FDI_CTX_PRX_N6 FDI1_TX#[2] PEG_RX[9]
E17 E33 PCIE_CRX_GTX_P10
B (15) FDI_CTX_PRX_N7 FDI1_TX#[3] PEG_RX[10] B
F32 PCIE_CRX_GTX_P11
PEG_RX[11] PCIE_CRX_GTX_P12
PEG_RX[12] D34
A22 E31 PCIE_CRX_GTX_P13
(15) FDI_CTX_PRX_P0 FDI0_TX[0] PEG_RX[13]
G19 C33 PCIE_CRX_GTX_P14
(15) FDI_CTX_PRX_P1 FDI0_TX[1] PEG_RX[14]
E20 B32 PCIE_CRX_GTX_P15
(15) FDI_CTX_PRX_P2 FDI0_TX[2] PEG_RX[15]
(15) FDI_CTX_PRX_P3 G18 FDI0_TX[3] PCIE_CTX_GRX_N[0..15] (22)
B20 M29 PCIE_CTX_GRX_C_N0 C1 1 2 DIS@ 0.1U_0402_10V7K PCIE_CTX_GRX_N0
(15) FDI_CTX_PRX_P4 FDI1_TX[0] PEG_TX#[0]
C19 M32 PCIE_CTX_GRX_C_N1 C2 1 2 DIS@ 0.1U_0402_10V7K PCIE_CTX_GRX_N1
(15) FDI_CTX_PRX_P5 FDI1_TX[1] PEG_TX#[1]
D19 M31 PCIE_CTX_GRX_C_N2 C3 1 2 DIS@ 0.1U_0402_10V7K PCIE_CTX_GRX_N2
(15) FDI_CTX_PRX_P6 FDI1_TX[2] PEG_TX#[2]
F17 L32 PCIE_CTX_GRX_C_N3 C4 1 2 DIS@ 0.1U_0402_10V7K PCIE_CTX_GRX_N3
(15) FDI_CTX_PRX_P7 FDI1_TX[3] PEG_TX#[3]
L29 PCIE_CTX_GRX_C_N4 C5 1 2 DIS@ 0.1U_0402_10V7K PCIE_CTX_GRX_N4
PEG_TX#[4] PCIE_CTX_GRX_C_N5 C6 DIS@ 0.1U_0402_10V7K PCIE_CTX_GRX_N5
(15) FDI_FSYNC0 J18 FDI0_FSYNC PEG_TX#[5] K31 1 2
(15) FDI_FSYNC1 J17 K28 PCIE_CTX_GRX_C_N6 C7 1 2 DIS@ 0.1U_0402_10V7K PCIE_CTX_GRX_N6
FDI1_FSYNC PEG_TX#[6] PCIE_CTX_GRX_C_N7 C8 DIS@ 0.1U_0402_10V7K PCIE_CTX_GRX_N7
PEG_TX#[7] J30 1 2
(15) FDI_INT H20 J28 PCIE_CTX_GRX_C_N8 C9 1 2 DIS@ 0.1U_0402_10V7K PCIE_CTX_GRX_N8
FDI_INT PEG_TX#[8] PCIE_CTX_GRX_C_N9 C10 DIS@ 0.1U_0402_10V7K PCIE_CTX_GRX_N9
PEG_TX#[9] H29 1 2
(15) FDI_LSYNC0 J19 G27 PCIE_CTX_GRX_C_N10 C11 1 2 DIS@ 0.1U_0402_10V7K PCIE_CTX_GRX_N10
FDI0_LSYNC PEG_TX#[10] PCIE_CTX_GRX_C_N11 C12 DIS@ 0.1U_0402_10V7K PCIE_CTX_GRX_N11
(15) FDI_LSYNC1 H17 FDI1_LSYNC PEG_TX#[11] E29 1 2
F27 PCIE_CTX_GRX_C_N12 C13 1 2 DIS@ 0.1U_0402_10V7K PCIE_CTX_GRX_N12
PEG_TX#[12] PCIE_CTX_GRX_C_N13 C14 DIS@ 0.1U_0402_10V7K PCIE_CTX_GRX_N13
PEG_TX#[13] D28 1 2
+1.05VS F26 PCIE_CTX_GRX_C_N14 C15 1 2 DIS@ 0.1U_0402_10V7K PCIE_CTX_GRX_N14
PEG_TX#[14] PCIE_CTX_GRX_C_N15 C16 DIS@ 0.1U_0402_10V7K PCIE_CTX_GRX_N15
PEG_TX#[15] E25 1 2
R2 1 2 24.9_0402_1% EDP_COMP A18 eDP_COMPIO PCIE_CTX_GRX_P[0..15] (22)
A17 M28 PCIE_CTX_GRX_C_P0 C17 1 2 DIS@ 0.1U_0402_10V7K PCIE_CTX_GRX_P0
R3 @ eDP_ICOMPO PEG_TX[0]
1 2 10K_0402_5% B16 eDP_HPD# PEG_TX[1] M33 PCIE_CTX_GRX_C_P1 C18 1 2 DIS@ 0.1U_0402_10V7K PCIE_CTX_GRX_P1
M30 PCIE_CTX_GRX_C_P2 C19 1 2 DIS@ 0.1U_0402_10V7K PCIE_CTX_GRX_P2
PEG_TX[2] PCIE_CTX_GRX_C_P3 C20 DIS@ 0.1U_0402_10V7K PCIE_CTX_GRX_P3
PEG_TX[3] L31 1 2
C15 L28 PCIE_CTX_GRX_C_P4 C21 1 2 DIS@ 0.1U_0402_10V7K PCIE_CTX_GRX_P4
eDP_AUX PEG_TX[4] PCIE_CTX_GRX_C_P5 C22 DIS@ 0.1U_0402_10V7K PCIE_CTX_GRX_P5
D15 eDP_AUX# PEG_TX[5] K30 1 2
K27 PCIE_CTX_GRX_C_P6 C23 1 2 DIS@ 0.1U_0402_10V7K PCIE_CTX_GRX_P6
eDP
PEG_TX[6] PCIE_CTX_GRX_C_P7 C24 DIS@ 0.1U_0402_10V7K PCIE_CTX_GRX_P7
PEG_TX[7] J29 1 2
eDP_COMPIO and ICOMPO signals C17 J27 PCIE_CTX_GRX_C_P8 C25 1 2 DIS@ 0.1U_0402_10V7K PCIE_CTX_GRX_P8
eDP_TX[0] PEG_TX[8] PCIE_CTX_GRX_C_P9 C26 DIS@ 0.1U_0402_10V7K PCIE_CTX_GRX_P9
F16 H28 1 2
should be shorted near balls C16
eDP_TX[1] PEG_TX[9]
G28 PCIE_CTX_GRX_C_P10 C27 1 2 DIS@ 0.1U_0402_10V7K PCIE_CTX_GRX_P10
eDP_TX[2] PEG_TX[10] PCIE_CTX_GRX_C_P11 C28 DIS@ 0.1U_0402_10V7K PCIE_CTX_GRX_P11
C and routed with typical G15 eDP_TX[3] PEG_TX[11] E28 1 2 C
F28 PCIE_CTX_GRX_C_P12 C29 1 2 DIS@ 0.1U_0402_10V7K PCIE_CTX_GRX_P12
impedance <25 mohms C18
PEG_TX[12]
D27 PCIE_CTX_GRX_C_P13 C30 1 2 DIS@ 0.1U_0402_10V7K PCIE_CTX_GRX_P13
eDP_TX#[0] PEG_TX[13] PCIE_CTX_GRX_C_P14 C31 DIS@ 0.1U_0402_10V7K PCIE_CTX_GRX_P14
E16 eDP_TX#[1] PEG_TX[14] E26 1 2
D16 D25 PCIE_CTX_GRX_C_P15 C32 1 2 DIS@ 0.1U_0402_10V7K PCIE_CTX_GRX_P15
eDP_TX#[2] PEG_TX[15]
F15 eDP_TX#[3]

TYCO_2013620-2_IVY BRIDGE

Nvidia support PCIE Gen2

D D

Security Classification Compal Secret Data
Title
Compal Electronics, Inc.
Issued Date 2011/07/12 Deciphered Date 2012/07/01
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL PROCESSOR(1/7) DMI,FDI,PEGRev
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CON