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A B C D E
1 1
Compal Confidential
2 2
JAWD0 Schematics Document
AMD Griffin Processor with RS780M+SB700
3 2008-07-01 3
REV:1.0
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008/03/25 Deciphered Date 2008/12/20 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS, MB A4391
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401575
Date: Tuesday, August 19, 2008 Sheet 1 of 45
A B C D E
A B C D E
Compal Confidential
Fan Control AMD S1G2 Processor
Model Name : JAWD0 page 36 Memory BUS(DDRII) 200pin DDRII-SO-DIMM X2
uPGA-638 Package Dual Channel BANK 0, 1, 2, 3 page 8,9
page 4,5,6,7 1.8V DDRII 533/667
1 1
CRT Hyper Transport Link
page 18 16 x 16
Thermal Sensor Clock Generator
LVDS ATI RS780
ADM1032 ICS9LPRS488B
page 18 page 5 page 15
uFCBGA-1299
PCI-Express 1x
page 10,11,12,13 page 16 page 30 page 29 page 29
USB CMOS Bluetooth New Mini
MINI Card x1 LAN(GbE) A link Express2 conn Card
Card Reader Camera Conn card
RT8111C X3/4 conn
WLAN
page 29 page 27
JMB385 26
page USB port 0,7,2 USB port 5 USB port 6 USB port 11 USB port 8,10
port 1,2 port 3 port 4
2
ATI SB700 3.3V 48MHz USB
2
RJ45 5 in 1 socket 3.3V 24.576MHz/48Mhz HD Audio
page 25
page 28
BGA-676
S-ATA
page 19,20,21,22,23
MDC 1.5 HDA Codec Analog
Conn 33 ALC268 34 internal
page page
MIC
SATA HDD CDROM LPC BUS
Conn. page 24
Conn. 24
page
port 0 port 2 Audio AMP
page 35
ENE KB926
3 page 31 3
Phone Jack x3
RTC CKT. PWR/B Conn. page 35
page 32
page 19 Touch Pad Int.KBD
page 32 page 32
Power On/Off CKT. LED/B Conn.
page 32 EC I/O Buffer BIOS
page 33
page 32 page 32
DC/DC Interface CKT. Hall SW/B
Conn. 2
USB port
page 38 page 29
Power Circuit DC/DC
4
page 39,40,41 4
42,43,44,45
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008/03/25 Deciphered Date 2008/12/20 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS, MB A4391
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401575
Date: Tuesday, August 19, 2008 Sheet 2 of 45
A B C D E
A B C D E
SIGNAL
STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
Voltage Rails
Full ON HIGH HIGH HIGH HIGH ON ON ON ON
Power Plane Description S1 S3 S5 S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW
VIN Adapter power supply (19V) N/A N/A N/A S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF
B+ AC or battery power rail for power circuit. N/A N/A N/A
1
S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF 1
+CPU_CORE Core voltage for CPU ON OFF OFF
+0.9VS 0.9V switched power rail for DDR terminator ON OFF OFF S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF
+1.05VS 1.05V switched power rail ON OFF OFF
+1.25VS 1.25V switched power rail ON OFF OFF
+1.5VS 1.5V switched power rail ON OFF OFF Board ID / SKU ID Table for AD channel
+1.8V 1.8V power rail for DDR ON ON OFF Vcc 3.3V +/- 5%
+1.8VS 1.8V switched power rail ON OFF OFF Ra/Rc/Re 100K +/- 5%
+2.5VS 2.5V switched power rail ON OFF OFF Board ID Rb / Rd / Rf V AD_BID min V AD_BID typ V AD_BID max
+3VALW 3.3V always on power rail ON ON ON* 0 0 0 V 0 V 0 V
+3V 3.3V power rail for SB ON ON X 1 8.2K +/- 5% 0.216 V 0.250 V 0.289 V
+3V_LAN 3.3V power rail for LAN ON ON X 2 18K +/- 5% 0.436 V 0.503 V 0.538 V
+3VS 3.3V switched power rail ON OFF OFF 3 33K +/- 5% 0.712 V 0.819 V 0.875 V
+5VALW 5V always on power rail ON ON ON* 4 56K +/- 5% 1.036 V 1.185 V 1.264 V
+5VS 5V switched power rail ON OFF OFF 5 100K +/- 5% 1.453 V 1.650 V 1.759 V
+VSB VSB always on power rail ON ON ON* 6 200K +/- 5% 1.935 V 2.200 V 2.341 V
+RTCVCC RTC power ON ON ON 7 NC 2.500 V 3.300 V 3.300 V
2 2
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
BOARD ID Table BTO Option Table
External PCI Devices Board ID PCB Revision BTO Item BOM Structure
Device IDSEL# REQ#/GNT# Interrupts
0 0.1
1
2
3
4
5
6
7
EC SM Bus1 address EC SM Bus2 address PROJECT ID Table
3 3
Device Address Device Address Board ID PROJECT
Smart Battery 0001 011X b ADI ADM1032 1001 100X b 0 JALB0
EEPROM(24C16/02) 1010 000X b 1
2
3
4
SB700 5 JAWD0
SM Bus 0 address 6
7 JALC0
Device Address
Clock Generator 1101 001Xb
(ICS9LPRS365)
DDR DIMM0 1001 000Xb
DDR DIMM2 1001 010Xb
Minicard
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008/03/25 Deciphered Date 2008/12/20 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS, MB A4391
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401575
Date: Tuesday, August 19, 2008 Sheet 3 of 45
A B C D E
A B C D E
1 1
+1.2V_HT
VLDT CAP.
250 mil
1 1 1 1 1 1
C455 C133 C131 C451 C138 C444
H_CADIP[0..15] H_CADOP[0..15] 4.7U_0805_10V4Z 4.7U_0805_10V4Z 0.22U_0603_16V4Z 0.22U_0603_16V4Z 180P_0402_50V8J 180P_0402_50V8J
10 H_CADIP[0..15] H_CADOP[0..15] 10
H_CADIN[0..15] H_CADON[0..15] 2 2 2 2 2 2
10 H_CADIN[0..15] H_CADON[0..15] 10
Near CPU Socket
+1.2V_HT +1.2V_HT
JCPU1A
2 2
VLDT=500mA D1 VLDT_A0 HT LINK VLDT_B0 AE2 1 2
D2 AE3 C134 4.7U_0805_10V4Z
VLDT_A1 VLDT_B1
D3 VLDT_A2 VLDT_B2 AE4
D4 VLDT_A3 VLDT_B3 AE5
H_CADIP0 E3 AD1 H_CADOP0
H_CADIN0 L0_CADIN_H0 L0_CADOUT_H0 H_CADON0
E2 L0_CADIN_L0 L0_CADOUT_L0 AC1
H_CADIP1 E1 AC2 H_CADOP1
H_CADIN1 L0_CADIN_H1 L0_CADOUT_H1 H_CADON1
F1 L0_CADIN_L1 L0_CADOUT_L1 AC3
H_CADIP2 G3 AB1 H_CADOP2
H_CADIN2 L0_CADIN_H2 L0_CADOUT_H2 H_CADON2
G2 L0_CADIN_L2 L0_CADOUT_L2 AA1
H_CADIP3 G1 AA2 H_CADOP3
H_CADIN3 L0_CADIN_H3 L0_CADOUT_H3 H_CADON3
H1 L0_CADIN_L3 L0_CADOUT_L3 AA3
H_CADIP4 J1 W2 H_CADOP4
H_CADIN4 L0_CADIN_H4 L0_CADOUT_H4 H_CADON4
K1 L0_CADIN_L4 L0_CADOUT_L4 W3
H_CADIP5 L3 V1 H_CADOP5
H_CADIN5 L0_CADIN_H5 L0_CADOUT_H5 H_CADON5
L2 L0_CADIN_L5 L0_CADOUT_L5 U1
H_CADIP6 L1 U2 H_CADOP6
H_CADIN6 L0_CADIN_H6 L0_CADOUT_H6 H_CADON6
M1 L0_CADIN_L6 L0_CADOUT_L6 U3
H_CADIP7 N3 T1 H_CADOP7
H_CADIN7 L0_CADIN_H7 L0_CADOUT_H7 H_CADON7
N2 L0_CADIN_L7 L0_CADOUT_L7 R1
H_CADIP8 E5 AD4 H_CADOP8
H_CADIN8 L0_CADIN_H8 L0_CADOUT_H8 H_CADON8
F5 L0_CADIN_L8 L0_CADOUT_L8 AD3
H_CADIP9 F3 AD5 H_CADOP9
H_CADIN9 L0_CADIN_H9 L0_CADOUT_H9 H_CADON9
F4 L0_CADIN_L9 L0_CADOUT_L9 AC5
H_CADIP10 G5 AB4 H_CADOP10
H_CADIN10 L0_CADIN_H10 L0_CADOUT_H10 H_CADON10
H5 L0_CADIN_L10 L0_CADOUT_L10 AB3
H_CADIP11 H3 AB5 H_CADOP11
H_CADIN11 L0_CADIN_H11 L0_CADOUT_H11 H_CADON11
H4 L0_CADIN_L11 L0_CADOUT_L11 AA5
H_CADIP12 K3 Y5 H_CADOP12
H_CADIN12 L0_CADIN_H12 L0_CADOUT_H12 H_CADON12
K4 L0_CADIN_L12 L0_CADOUT_L12 W5
H_CADIP13 L5 V4 H_CADOP13
3 H_CADIN13 L0_CADIN_H13 L0_CADOUT_H13 H_CADON13 3
M5 L0_CADIN_L13 L0_CADOUT_L13 V3
H_CADIP14 M3 V5 H_CADOP14
H_CADIN14 L0_CADIN_H14 L0_CADOUT_H14 H_CADON14
M4 L0_CADIN_L14 L0_CADOUT_L14 U5
H_CADIP15 N5 T4 H_CADOP15
H_CADIN15 L0_CADIN_H15 L0_CADOUT_H15 H_CADON15
P5 L0_CADIN_L15 L0_CADOUT_L15 T3
10 H_CLKIP0 J3 L0_CLKIN_H0 L0_CLKOUT_H0 Y1 H_CLKOP0 10
10 H_CLKIN0 J2 L0_CLKIN_L0 L0_CLKOUT_L0 W1 H_CLKON0 10
10 H_CLKIP1 J5 L0_CLKIN_H1 L0_CLKOUT_H1 Y4 H_CLKOP1 10
10 H_CLKIN1 K5 L0_CLKIN_L1 L0_CLKOUT_L1 Y3 H_CLKON1 10
10 H_CTLIP0 N1 L0_CTLIN_H0 L0_CTLOUT_H0 R2 H_CTLOP0 10
10 H_CTLIN0 P1 L0_CTLIN_L0 L0_CTLOUT_L0 R3 H_CTLON0 10
10 H_CTLIP1 P3 L0_CTLIN_H1 L0_CTLOUT_H1 T5 H_CTLOP1 10
10 H_CTLIN1 P4 L0_CTLIN_L1 L0_CTLOUT_L1 R5 H_CTLON1 10
6090022100G_B
Athlon 64 S1
Processor Socket
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008/03/25 Deciphered Date 2008/12/20 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS, MB A4391
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401575 D
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, August 19, 2008 Sheet 4 of 45
A B C D E
A B C D E
PLACE CLOSE TO PROCESSOR
WITHIN 1.5 INCH
DDRA_CLK0
1
Processor DDR2 Memory Interface
C219
1.5P_0402_50V8C JCPU1C
2 9 DDRB_SDQ[63..0]
DDRA_CLK0# MEM:DATA
DDRA_SDQ[63..0] 8
DDRB_SDQ0 C11 G12 DDRA_SDQ0
1 +1.8V DDRA_CLK1 DDRB_SDQ1 MB_DATA0 MA_DATA0 DDRA_SDQ1 1
A11 MB_DATA1 MA_DATA1 F12
1 DDRB_SDQ2 A14 H14 DDRA_SDQ2
DDRB_SDQ3 MB_DATA2 MA_DATA2 DDRA_SDQ3
B14 MB_DATA3 MA_DATA3 G14
2
C162 DDRB_SDQ4 G11 H11 DDRA_SDQ4
R77 1.5P_0402_50V8C DDRB_SDQ5 MB_DATA4 MA_DATA4 DDRA_SDQ5
E11 MB_DATA5 MA_DATA5 H12
1K_0402_1% DDRA_CLK1# 2 DDRB_SDQ6 DDRA_SDQ6
D12 MB_DATA6 MA_DATA6 C13
DDRB_SDQ7 A13 E13 DDRA_SDQ7
DDRB_SDQ8 MB_DATA7 MA_DATA7 DDRA_SDQ8
A15 H15
1
+MCH_REF DDRB_CLK0 DDRB_SDQ9 MB_DATA8 MA_DATA8 DDRA_SDQ9
A16 MB_DATA9 MA_DATA9 E15
1000P_0402_25V8J
0.1U_0402_16V4Z
1 DDRB_SDQ10 A19 E17 DDRA_SDQ10
MB_DATA10 MA_DATA10
2
1 1 DDRB_SDQ11 A20 H17 DDRA_SDQ11
MB_DATA11 MA_DATA11
C164
C168
R75 C483 DDRB_SDQ12 C14 E14 DDRA_SDQ12
1K_0402_1% 1.5P_0402_50V8C DDRB_SDQ13 MB_DATA12 MA_DATA12 DDRA_SDQ13
D14 MB_DATA13 MA_DATA13 F14
DDRB_CLK0# 2 DDRB_SDQ14 DDRA_SDQ14
C18 MB_DATA14 MA_DATA14 C17
2 2 DDRB_SDQ15 DDRA_SDQ15
D18 G17
1
DDRB_CLK1 DDRB_SDQ16 MB_DATA15 MA_DATA15 DDRA_SDQ16
D20 MB_DATA16 MA_DATA16 G18
1 DDRB_SDQ17 A21 C19 DDRA_SDQ17
DDRB_SDQ18 MB_DATA17 MA_DATA17 DDRA_SDQ18
D24 MB_DATA18 MA_DATA18 D22
C413 DDRB_SDQ19 C25 E20 DDRA_SDQ19
1.5P_0402_50V8C DDRB_SDQ20 MB_DATA19 MA_DATA19 DDRA_SDQ20
B20 MB_DATA20 MA_DATA20 E18
DDRB_CLK1# 2 DDRB_SDQ21 DDRA_SDQ21
C20 MB_DATA21 MA_DATA21 F18
DDRB_SDQ22 B24 B22 DDRA_SDQ22
DDRB_SDQ23 MB_DATA22 MA_DATA22 DDRA_SDQ23
C24 MB_DATA23 MA_DATA23 C23
DDRB_SDQ24 E23 F20 DDRA_SDQ24
DDRB_SDQ25 MB_DATA24 MA_DATA24 DDRA_SDQ25
E24 MB_DATA25 MA_DATA25 F22
DDRB_SDQ26 G25 H24 DDRA_SDQ26
DDRB_SDQ27 MB_DATA26 MA_DATA26 DDRA_SDQ27
G26 MB_DATA27 MA_DATA27 J19
DDRB_SDQ28 C26 E21 DDRA_SDQ28
DDRB_SDQ29 MB_DATA28 MA_DATA28 DDRA_SDQ29
D26 MB_DATA29 MA_DATA29 E22
DDRB_SDQ30 G23 H20 DDRA_SDQ30
+0.9V +0.9V DDRB_SDQ31 MB_DATA30 MA_DATA30 DDRA_SDQ31
G24 MB_DATA31 MA_DATA31 H22
JCPU1B DDRB_SDQ32 AA24 Y24 DDRA_SDQ32
2 DDRB_SDQ33 MB_DATA32 MA_DATA32 DDRA_SDQ33 2
AA23 MB_DATA33 MA_DATA33 AB24
D10 W10 DDRB_SDQ34 AD24 AB22 DDRA_SDQ34
VTT1 MEM:CMD/CTRL/CLK VTT5 DDRB_SDQ35 MB_DATA34 MA_DATA34 DDRA_SDQ35
Place them close to CPU within 1" C10 VTT2 VTT6 AC10 AE24 MB_DATA35 MA_DATA35 AA21
B10 AB10 DDRB_SDQ36 AA26 W22 DDRA_SDQ36
VTT3 VTT7 DDRB_SDQ37 MB_DATA36 MA_DATA36 DDRA_SDQ37
AD10 VTT4 VTT8 AA10 AA25 MB_DATA37 MA_DATA37 W21
R347 39.2_0402_1% A10 DDRB_SDQ38 AD26 Y22 DDRA_SDQ38
VTT9 DDRB_SDQ39 MB_DATA38 MA_DATA38 DDRA_SDQ39
1 2 AF10 MEMZP AE25 MB_DATA39 MA_DATA39 AA22
+1.8V 1 2 AE10 Y10 1 R257 2 0_0402_5% +0.9V DDRB_SDQ40 AC22 Y20 DDRA_SDQ40
R338 39.2_0402_1% MEMZN VTT_SENSE @ DDRB_SDQ41 MB_DATA40 MA_DATA40 DDRA_SDQ41
AD22 MB_DATA41 MA_DATA41 AA20
H16 W17 +MCH_REF DDRB_SDQ42 AE20