Compal_LA-8641P_(IdeaPad_Y485).pdf part of Compal Compal LA-8641P (IdeaPad Y485) Compal_LA-8641P_(IdeaPad_Y485).pdf, Compal Compal_LA-8641P_(IdeaPad

Text preview for : Compal_LA-8641P_(IdeaPad_Y485).pdf part of Compal Compal LA-8641P (IdeaPad Y485) Compal Compal_LA-8641P_(IdeaPad_Y485).pdf

Back to : Compal_LA-8641P_(IdeaPad_ | Home

A B C D E

1 1

Compal Confidential
2 2

QAWYA M/B Schematics Document
AMD Fs1r2 Processor with DDRIII + Husdon M3 FCH
AMD VGA ThamesXTX

3 2011-12-05 3

REV:0.2

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/07/21 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Page
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA8641P
Date: Thursday, January 05, 2012 Sheet 1 of 55
A B C D E
A B C D E

Compal confidential
File Name : Y485

AMD Thames XTX

1
VRAM PCIE x 16 Gen2 1

128x16 Memory BUS(DDRIII) 204pin DDRIII-SO-DIMM X2
GDDR5 x 8 AMD FS1r2 APU Dual Channel BANK 0, 1, 2 page 10,11
page 17,~26
1.5V DDRIII 1600
DP Port0 Trinity
LVDS
translator
uPGA 722 pin
RTD2132S HDMI Conn. DP Port2 35mm x 35mm
page 27 page 30
DP Port1 page 5,~9

4 * x1 PCI-E 2.0 x4 UMI Gen. 1 2Channel Speaker
LVDS Conn. 2.5GT/s per lane page 36
page 28 GPP3 GPP1 GPP0

WLAN LAN(Gbe) Array Digital MIC
REKTEK page 28
2
RTL8111E/
RTL8111F
page 32
AZALIA Audio Codec 2

Card Reader page 31 Hudson M3 RealTek Audio Jacks
ALC269-VC Stereo
JBM389C page 36
uFCBGA-656 HeadPhone Output
Microphone Input
SD/MMC/MS/XD
Audio Board Page41 RJ45 CONN 24.5mm x 24.5mm 14*USB2.0/ page 41
page 33
4*USB3.0,10*USB2.0

FCH CRT (VGA DAC)
CMOS Camera page 28
CRT Conn.
page 29
page 12~16 6*SATA serial BlueTooth CONN page 39
USB PORT 3.0 x2(Left) page 40
PCI Express USB(reserve for WiMAX)

Mini card Slot 1 PCI-E(WLAN) LPC BUS USB PORT 2.0 x2(Right) page 41
WLAN page 31

SPI ROM WLAN page 31
3

PCI Express page 13
EC 3

SATA(SSD) ENE KB9012
Mini card Slot 2 page 37 USB PORT 3.0 x1 with USB charger
page 31 (Right Option) page 41

Sub-borad SATA0
Int.KBD SATA3.0 HDD (SSD) page 31
page 38
POWER BOARD
SATA1
Touch Pad SATA3.0 HDD CONN
page 35
Function Board page 38
SATA2
SATA ODD CONN
page 35
Audio Board
Thermal Sensor
page 34
4 4

Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/07/21 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
MB Block Diagram
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, January 05, 2012 Sheet 2 of 55
A B C D E
A B C D E

Voltage Rails
SIGNAL
STATE SLP_S3# SLP_S5# +VALW +V +VS Clock
+5VS
+3VS Full ON HIGH HIGH ON ON ON ON
+2.5VS
S1(Power On Suspend) HIGH HIGH ON ON ON LOW
power +1.5VS
plane +1.2VS S3 (Suspend to RAM) HIGH HIGH ON ON OFF OFF
1
+1.1VS LOW 1
+5VALW +1.5V S4 (Suspend to Disk) HIGH ON OFF OFF OFF
+0.75VS
+B +1.5V_APU
+APU_CORE S5 (Soft OFF) LOW LOW ON OFF OFF OFF
+3VALW
+APU_CORE_NB
+VGA_CORE
State +1.1VALW
+3.3VGS BOARD ID Table Board ID / SKU ID Table for AD channel
+1.8VGS
+1.5VGS
Board ID PCB Revision
0 ID BRD ID Ra Rb Vab
+1.0VGS
1 0 R10 MP x 0 0V
2 Ra = R310
3 0.1 1 R03 PVT 100K 8.2K 0.25V Rb = R311
S0 4
O O O O 2 R02 DVT 100K 18K 0.5V
5
6 3 R01 EVT 100K 33K 0.82V
S3 7
O O O X
2 2
S5 S4/AC
O O X X USB Port Table
4 External BOM Structure Table
S5 S4/ Battery only USB 2.0 USB 3.0 Port
O X X X USB Port BOM Structure BTO Item
0 USB Port (Right Side) PX@ VGA circuit
S5 S4/AC & Battery
don't exist X X X X 1 USB Port (Right Side/option) PX4@ Power xpress 4.0 circuit
2 Mini Card(WLAN) CHG@ USB charger part
3 Camera NOCHG@ No USB charger part
elbaT lortnoC SUBMS 4 BT@ Blue Tooth part
Blue Tooth
lamrehT CMOS Camera part
NALW rosneS 5 CMOS@
ECRUOS AGV TTAB 2109BK NAWW MMIDOS HCF UPA 2312DTR RTL8111E LAN part
6 8111E@
1KC_CE_BMS 7 8111F@ RTL8111F LAN part
1AD_CE_BMS
2109BK
WLAV3+
X V
WLAV3+
X X X X X X X 8 LAN_E@ RTL8111E X76
SUS_2KC_CE_BMS 9 LAN_F@ RTL8111F X76
SUS_2AD_CE_BMS
2109BK
WLAV3+
X X X X X X X V
V5.1+
X 0 10 USB Port (Left Side) X76@ X76 Level part for VRAM
0KLCS_HCF 1 11 USB Port (Left Side) S1G@ X76 P/N for Samsun VRAM 1G
HCF X X X V V X X X X XHCI X76 P/N for Samsun VRAM 2G
3 0ATADS_HCF SV3+ SV3+ SV3+ 2 12 USB Port (Right Side/option) S2G@ 3

3 13 H1G@ X76 P/N for Hynix VRAM 1G
2KC_CE_BMS
2109BK V X X X X V V H2G@ X76 P/N for Hynix VRAM 2G
2AD_CE_BMS SV3+ X X USB OC MAPPING 1403@ EMC1403 thermal part
)retfihs VL( EMC2103 thermal part
2103@
OC# USB Port HDMI part
HDMI@
Address 0 USB20 port10,port11 USB30 port0,port1 KBL@ K/B Light part
EC SM Bus1 address EC SM Bus2 address 1 USB20 port0 ME@ ME part
2 USB20 port1,port12 USB30 port2 USBR3@ Right port 3.0
Device Device Address
3 USBR2@ Right port 2.0
Smart Battery 0001 011X b Thermal Sensor 1001_101xb
@ Unpop
SB-TSI(default) 1001_100xb
SSD@ SSD
VGA(thermal) 1000_001xb APU PCIE PORT LIST FCH PCIE PORT LIST
PCH SM Bus address RTD2132S 1010_1000b Port Device Port Device

Device Address
1 LAN 1
DDR DIMM0 1001 000Xb
2 WLAN 2
4 DDR DIMM2 1001 010Xb
3 3 4

4 Card Reader 4

Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/07/21 Deciphered Date 2012/12/31 Title
Notes List
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA8641P
Date: Thursday, January 05, 2012 Sheet 3 of 55
A B C D E
5 4 3 2 1

Without BACO option :
Power-Up/Down Sequence PE_GPIO0 : Low -> Reset dGPU ; High ->Normal operation
PE_GPIO1 : Low -> dGPU Power OFF ; High -> dGPU Power ON
"Thames" has the following requirements with regards to power-supply sequencing
to avoid damaging the ASIC: BACO option :
All the ASIC supplies, except for VDDR3, must fully reach their respective PE_GPIO0 : High ->Normal operation (dGPU is not reset on BACO mode)
PE_GPIO1 : Low -> dGPU Power OFF ; High -> dGPU Power ON (always High)
nominal voltages within 20 ms of the start of the ramp-up sequence, though a
shorter ramp-up duration is preferred. There is no timing requirement on the dGPU Power Pins Voltage PX 3.0 BACO Mode Max current
D ramp up of VDDR3 relative to other power rails. PCIE_PVDD, PCIE_VDDR, TSVDD, VDDR4, VDD_CT, 1.8V OFF ON 1679mA D

The external pull-up resistors on the DDC/AUX signals (if applicable) should
ramp up before or after both VDDC and VDD_CT have ramped up.
DPE_PVDD, DP[F:E]_VDD18, DP[D:A]_PVDD,
DP[D:A]_VDD18, AVDD, VDD1DI, A2VDDQ, VDD2DI,
VDDC and VDD_CT should not ramp up simultaneously. For example, VDDC
should reach 90% before VDD_CT starts to ramp up (or vice versa). For BACO
DPLL_PVDD, MPV18, and SPV18
DP[F:E]_VDD10, DP[D:A]_VDD10, DPLL_VDDC, and 1.0V OFF ON 775mA
enabled designs, VDDC must ramp up before VDD_CT at system power up. SPV10
For power down, reversing the ramp-up sequence is recommended
PCIE_VDDC 1.0V OFF ON 1.1A
VDDR3 3.3V OFF ON 60mA
BIF_VDDC (current consumption = [email protected], in Same as OFF ON 70mA
BACO mode) VDDC Same as
PCIE_VDDC
VDDR1 1.5V OFF OFF 1.2A
VDDR3(3.3VGS) VDDC/VDDCI TBD OFF OFF 28

PCIE_VDDC(1.0V)
PX4.0
VDDR1(1.5VGS)
C PE_GPIO0(PXS_RST#) PE_EN C
BACO Switch
VDDC/VDDCI(1.12V)
iGPU dGPU
BIF_VDDC

PE_GPIO1(PXS_PWREN)

VDD_CT(1.8V)
PX_mode

PERSTb +3.3VALW MOS
+3.3VGS
1
REFCLK B+ Regulator
+1.5VGS
+1.5V +1.0VGS
LDO
2 3
Straps Reset
+B Regulator
+VGA_CORE
+5VLAW +1.8VGS
Straps Valid Regulator
5 4
PWRGOOD

B B
Global ASIC Reset
PX5.0
T4+16clock
PE_GPIO0(PXS_RST#)
+VGA_CORE
iGPU dGPU
BIF_VDDC

PE_GPIO1(PXS_PWREN)

+3.3VALW +3.3VGS Short PX_MODE and PX_PWREN
MOS
1
B+ Regulator
+1.5VGS
+1.5V +1.0VGS
LDO
2 3

A
+B Regulator
+VGA_CORE A
+5VLAW +1.8VGS
Regulator
5 4

Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/07/21 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VGA Notes List
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA8641P
Date: Thursday, January 05, 2012 Sheet 4 of 55
5 4 3 2 1
A B C D E

<16> PCIE_CRX_GTX_P[0..15] PCIE_CTX_GRX_P[0..15] <16>

<16> PCIE_CRX_GTX_N[0..15] PCIE_CTX_GRX_N[0..15] <16>

JCPU1A
PCI EXPRESS
PCIE_CRX_GTX_P0 AB8 AB2 PCIE_CTX_C_GRX_P0 C1 PX@ 1 2 0.1U_0402_16V7K PCIE_CTX_GRX_P0
PCIE_CRX_GTX_N0 AB7 P_GFX_RXP0 P_GFX_TXP0 AB1 PCIE_CTX_C_GRX_N0 C2 PX@ 1 2 0.1U_0402_16V7K PCIE_CTX_GRX_N0
PCIE_CRX_GTX_P1 AA9 P_GFX_RXN0 P_GFX_TXN0 AA3 PCIE_CTX_C_GRX_P1 C3 PX@ 1 2 0.1U_0402_16V7K PCIE_CTX_GRX_P1
PCIE_CRX_GTX_N1 AA8 P_GFX_RXP1 P_GFX_TXP1 AA2 PCIE_CTX_C_GRX_N1 C4 PX@ 1 2 0.1U_0402_16V7K PCIE_CTX_GRX_N1
PCIE_CRX_GTX_P2 AA5 P_GFX_RXN1 P_GFX_TXN1 Y5 PCIE_CTX_C_GRX_P2 C5 PX@ 1 2 0.1U_0402_16V7K PCIE_CTX_GRX_P2
PCIE_CRX_GTX_N2 AA6 P_GFX_RXP2 P_GFX_TXP2 Y4 PCIE_CTX_C_GRX_N2 C6 PX@ 1 2 0.1U_0402_16V7K PCIE_CTX_GRX_N2
1 PCIE_CRX_GTX_P3 Y8 P_GFX_RXN2 P_GFX_TXN2 Y2 PCIE_CTX_C_GRX_P3 C7 PX@ 1 2 0.1U_0402_16V7K PCIE_CTX_GRX_P3 1
PCIE_CRX_GTX_N3 Y7 P_GFX_RXP3 P_GFX_TXP3 Y1 PCIE_CTX_C_GRX_N3 C8 PX@ 1 2 0.1U_0402_16V7K PCIE_CTX_GRX_N3
PCIE_CRX_GTX_P4 W9 P_GFX_RXN3 P_GFX_TXN3 W3 PCIE_CTX_C_GRX_P4 C9 PX@ 1 2 0.1U_0402_16V7K PCIE_CTX_GRX_P4
PCIE_CRX_GTX_N4 W8 P_GFX_RXP4 P_GFX_TXP4 W2 PCIE_CTX_C_GRX_N4 C10 PX@ 1 2 0.1U_0402_16V7K PCIE_CTX_GRX_N4
PCIE_CRX_GTX_P5 W5 P_GFX_RXN4 P_GFX_TXN4 V5 PCIE_CTX_C_GRX_P5 C11 PX@ 1 2 0.1U_0402_16V7K PCIE_CTX_GRX_P5
PCIE_CRX_GTX_N5 W6 P_GFX_RXP5 P_GFX_TXP5 V4 PCIE_CTX_C_GRX_N5 C12 PX@ 1 2 0.1U_0402_16V7K PCIE_CTX_GRX_N5
PCIE_CRX_GTX_P6 V8 P_GFX_RXN5 P_GFX_TXN5 V2 PCIE_CTX_C_GRX_P6 C13 PX@ 1 2 0.1U_0402_16V7K PCIE_CTX_GRX_P6
PCIE_CRX_GTX_N6 V7 P_GFX_RXP6 P_GFX_TXP6 V1 PCIE_CTX_C_GRX_N6 C14 PX@ 1 2 0.1U_0402_16V7K PCIE_CTX_GRX_N6

GRAPHICS
PCIE_CRX_GTX_P7 U9 P_GFX_RXN6 P_GFX_TXN6 U3 PCIE_CTX_C_GRX_P7 C15 PX@ 1 2 0.1U_0402_16V7K PCIE_CTX_GRX_P7
PCIE_CRX_GTX_N7 U8 P_GFX_RXP7 P_GFX_TXP7 U2 PCIE_CTX_C_GRX_N7 C16 PX@ 1 2 0.1U_0402_16V7K PCIE_CTX_GRX_N7
PCIE_CRX_GTX_P8 U5 P_GFX_RXN7 P_GFX_TXN7 T5 PCIE_CTX_C_GRX_P8 C17 PX@ 1 2 0.1U_0402_16V7K PCIE_CTX_GRX_P8
PCIE_CRX_GTX_N8 U6 P_GFX_RXP8 P_GFX_TXP8 T4 PCIE_CTX_C_GRX_N8 C18 PX@ 1 2 0.1U_0402_16V7K PCIE_CTX_GRX_N8
PCIE_CRX_GTX_P9 T8 P_GFX_RXN8 P_GFX_TXN8 T2 PCIE_CTX_C_GRX_P9 C19 PX@ 1 2 0.1U_0402_16V7K PCIE_CTX_GRX_P9
PCIE_CRX_GTX_N9 T7 P_GFX_RXP9 P_GFX_TXP9 T1 PCIE_CTX_C_GRX_N9 C20 PX@ 1 2 0.1U_0402_16V7K PCIE_CTX_GRX_N9
PCIE_CRX_GTX_P10 R9 P_GFX_RXN9 P_GFX_TXN9 R3 PCIE_CTX_C_GRX_P10 C21 PX@ 1 2 0.1U_0402_16V7K PCIE_CTX_GRX_P10
PCIE_CRX_GTX_N10 R8 P_GFX_RXP10 P_GFX_TXP10 R2 PCIE_CTX_C_GRX_N10 C22 PX@ 1 2 0.1U_0402_16V7K PCIE_CTX_GRX_N10
PCIE_CRX_GTX_P11 R5 P_GFX_RXN10 P_GFX_TXN10 P5 PCIE_CTX_C_GRX_P11 C23 PX@ 1 2 0.1U_0402_16V7K PCIE_CTX_GRX_P11
PCIE_CRX_GTX_N11 R6 P_GFX_RXP11 P_GFX_TXP11 P4 PCIE_CTX_C_GRX_N11 C24 PX@ 1 2 0.1U_0402_16V7K PCIE_CTX_GRX_N11
PCIE_CRX_GTX_P12 P8 P_GFX_RXN11 P_GFX_TXN11 P2 PCIE_CTX_C_GRX_P12 C25 PX@ 1 2 0.1U_0402_16V7K PCIE_CTX_GRX_P12
PCIE_CRX_GTX_N12 P7 P_GFX_RXP12 P_GFX_TXP12 P1 PCIE_CTX_C_GRX_N12 C26 PX@ 1 2 0.1U_0402_16V7K PCIE_CTX_GRX_N12
PCIE_CRX_GTX_P13 N9 P_GFX_RXN12 P_GFX_TXN12 N3 PCIE_CTX_C_GRX_P13 C27 PX@ 1 2 0.1U_0402_16V7K PCIE_CTX_GRX_P13
PCIE_CRX_GTX_N13 N8 P_GFX_RXP13 P_GFX_TXP13 N2 PCIE_CTX_C_GRX_N13 C28 PX@ 1 2 0.1U_0402_16V7K PCIE_CTX_GRX_N13
PCIE_CRX_GTX_P14 N5 P_GFX_RXN13 P_GFX_TXN13 M5 PCIE_CTX_C_GRX_P14 C29 PX@ 1 2 0.1U_0402_16V7K PCIE_CTX_GRX_P14
PCIE_CRX_GTX_N14 N6 P_GFX_RXP14 P_GFX_TXP14 M4 PCIE_CTX_C_GRX_N14 C30 PX@ 1 2 0.1U_0402_16V7K PCIE_CTX_GRX_N14
PCIE_CRX_GTX_P15 M8 P_GFX_RXN14 P_GFX_TXN14 M2 PCIE_CTX_C_GRX_P15 C31 PX@ 1 2 0.1U_0402_16V7K PCIE_CTX_GRX_P15
PCIE_CRX_GTX_N15 M7 P_GFX_RXP15 P_GFX_TXP15 M1 PCIE_CTX_C_GRX_N15 C32 PX@ 1 2 0.1U_0402_16V7K PCIE_CTX_GRX_N15
P_GFX_RXN15 P_GFX_TXN15
AE5 AD5 PCIE_CTX_C_DRX_P0 C33 1 2 0.1U_0402_16V7K
<31> PCIE_CRX_DTX_P0 AE6 P_GPP_RXP0 P_GPP_TXP0 AD4 PCIE_CTX_C_DRX_N0 1 2 PCIE_CTX_DRX_P0 <31>
C34 0.1U_0402_16V7K LAN
<31> PCIE_CRX_DTX_N0 AD8 P_GPP_RXN0 P_GPP_TXN0 AD2 PCIE_CTX_C_DRX_P1 1 2 PCIE_CTX_DRX_N0 <31>
C35 0.1U_0402_16V7K
<30> PCIE_CRX_DTX_P1 AD7 P_GPP_RXP1 P_GPP_TXP1 AD1 1 2 PCIE_CTX_DRX_P1 <30>
PCIE_CTX_C_DRX_N1 C36 0.1U_0402_16V7K WLAN
<30> PCIE_CRX_DTX_N1 AC9 P_GPP_RXN1 P_GPP_TXN1 AC3 PCIE_CTX_DRX_N1 <30>
2 P_GPP_RXP2 P_GPP_TXP2 2
GPP

AC8 AC2
AC5 P_GPP_RXN2 P_GPP_TXN2 AB5 PCIE_CTX_C_DRX_P3 C461 1 2 0.1U_0402_16V7K
<40> PCIE_CRX_DTX_P3 AC6 P_GPP_RXP3 P_GPP_TXP3 AB4 PCIE_CTX_DRX_P3 <40>
PCIE_CTX_C_DRX_N3 C462 1 2 0.1U_0402_16V7K Card reader
<40> PCIE_CRX_DTX_N3