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1 1




2



Compal confidential 2




Schematics Document
Mobile Yonah uFCPGA with Intel
Calistoga_PM+ICH7-M core logic
3
2005-11-24 3



REV:0.5




4 4




Security Classification
2005/03/10
Compal Secret Data
2006/03/10 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Sheet
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-2821P 0.5
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, November 25, 2005 Sheet 1 of 52
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A B C D E




Compal confidential
File Name : LA-2821P
AngelFire 3.0
1 1
Accelerometer Fan Control
page 4
LIS3LV02DQ Mobile Yonah Thermal Sensor Clock Generator Accelerometer
page 27
uFCPGA-478 CPU ADM1032AR ICS954306 LIS3LV02DQ
page 4,5,6 page 4 page 15 page 27

FSB
H_A#(3..31) 533/667MHz H_D#(0..63)
DDR2 -400/533/667 DDR2-SO-DIMM X2
BANK 0, 1, 2, 3 page 13,14
MXM III connector PCI-E x 16
page 18
Intel Calistoga MCH Dual Channel
945PM USB conn x2
CRT / TV-OUT PCBGA 1466 (Docking) page 35
page 7,8,9,10,11,12
page 16
USB2.0 HUB / FingerPrinter AES2501
2
FP Conn page 30 USBx1 page 30 2




LCD CONN USB2.0
USB conn x2
page 17 DMI page 30 New Card USBx1
page 24


PCI-E BUS BT Conn
page 30


PCI BUS USB conn x2 MDC1.5
AC-LINK/Azalia
(Sub Board) page 29 page 34

Intel ICH7-M
Audio CKT AMP & Audio Jack
CardBus Controller mBGA-652 AD1981HD page 28 MAX9710ETPpage 29
10/100/1000 LAN Mini-Card
LED BCM5753M page 27 TI PCI7612 page 19,20,21,22
page 32 page 25,26 page 23,24 SATA HDD Connector
3
SPI SATA Master 3
page 20 Docking CONN.
SPI ROM PATA Slave
*RJ-45(LED*2)
RTC CKT. 1394 port Slot 0/Smart Card 6in1 Slot PATA ODD Connector *RJ-11(Pass Through)
page 20
RJ45/11 CONN page 23 page 24 page 23
SST25LF080A
page 23 page 20 *CRT
page 26
*COMPOSITE Video Out
LPC BUS *TVOUT
*DVI
Power OK CKT. *LINE IN
page 37 *LINE OUT
*PCI-E x2
Security Module SMSC Super I/O Flash ROM *Serial Port
Power On/Off CKT. SMSC KBC 1021 LPC47N217 31 SST49LF008A *Parallel Port
page 32 page page 32 *PS/2 x2
page 34 page 33 *USB x2
*DC JACK
Int.KBD COM1 LPT
4 DC/DC Interface CKT. Touch Pad CONN. ( Docking ) ( Docking ) page 34 4
page 34 page 34 page 35 page 35
page 36

TrackPoint CONN.
page 34

Power Circuit DC/DC
Security Classification
2005/03/10
Compal Secret Data
2006/03/10 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
Page 38,39,40,41,42,43,44,45,46,47 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Block Diagram
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-2821P 0.5
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, November 25, 2005 Sheet 2 of 52
A B C D E
5 4 3 2 1




Symbol Note :
Voltage Rails
Power Plane Description S0-S1 S3 S5
: means Digital Ground

VIN Adapter power supply (18.5V) N/A N/A N/A

D
B+ AC or battery power rail for power circuit N/A N/A N/A : means Analog Ground D

+CPU_CORE Core voltage for CPU ON OFF OFF
+VCCP 1.05V power rail for Processor I/O and MCH/ICH core power ON OFF OFF
L Note: Layout Related Memo
+0.9VS 0.9V switched power rail for DDRII Vtt ON OFF OFF

: Layout Note related Area Mark.
+1.5VS 1.5V switched power rail for PCI-E interface ON OFF OFF
+1.8V 1.8V power rail for DDRII ON ON OFF
: Question Area Mark.(Wait check)
+1.8VS 1.8V switched power rail ON OFF OFF
+2.5VS 2.5V switched power rail for MCH video PLL ON OFF OFF
9/15 : Modified Area Mark.
+2.5VALW 3.3V always on power rail ON ON ON*
+3VALW 3.3V always on power rail ON ON ON*
: C-BOM impact
+3VS 3.3V switched power rail ON OFF OFF
+5VALW 5V always on power rail ON ON ON*
: Modified Area Mark(Compare with EAL60).
+5VS 5V switched power rail ON OFF OFF
+RTC_VCC RTC power ON ON ON
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
@ : means just reserve , no build
* SPI@ : means just build when SPI I/F BIOS function reserve.
C C
* FWH@ : means just build when FWH I/F BIOS function reserve.
* NOXDP@ : means just build when XDP function disable.
Internal PCI Devices XDP@ : means just build when XDP function enable. When this time, docking PCI express will not work.
DEVICE Bus PCI Device ID IDSEL # * TPM1.2@ : means just build when TPM1.2 function enable.
* TPM@ : means just build when TPM function enable.
LAN 1 D8 AD24
* SC@ : means just build when SmartCard function enable.
Azalia 0 D27 AD11
* SATA@ : means just build when SATA I/F HDD enable.
PCI-E 0 D28 AD12
NOSATA@ : means just build when SATA I/F HDD disable.
USB1.1/2.0 0 D29 AD13
* NC@ : means just build when New Card function enable.
PCI to PCI (DMI to PCI) 0 D30 AD14
NONC@ : means just build when New Card function disable.
AC97 MODEM 0 D30 AD14
* MDC1.5@ : means just build when MDC1.5 function enable.
AC97 Audio 0 D30 AD14
* 7612@ : means just build when TI PCI7612 chip selected.
PATA/SATA 0 D31 AD15
7611@ : means just build when TI PCI7611MLS chip selected.
LPC I/F 0 D31 AD15
250@ : means just build when SMsC LPC47N250 chip selected.
SMBUS 0 D31 AD15
* 1021@ : means just build when SMsC KBC1021 chip selected.
CPU I/F 0 D31 AD15
* 1981HD@ : means just build when AD1981HD chip selected.
B DMA 0 D31 AD15 B
45@ : means need be mounted when 45 level assy or rework stage.
PMU 0 D31 AD15
* ACCEL@ : means just build when Accelerometer chip LIS3LV02DQ selected.
* NODP@ : means just build when No DP design Clock Gen. selected.
External PCI Devices DP@ : means just build when DP design Clock Gen. selected.
LPNO@ : means just build when No LP design ICS Clock Gen. selected.
DEVICE PCI Device ID IDSEL # REQ/GNT # PIRQ
* LP@ : means just build when LP design ICS Clock Gen. selected.
Mini-PCI D4 AD20 0 F * DB@ : means just build when Mini-PCI E Debug Card function enable.
CARD BUS D6 AD22 2 CDEG
* : means define for SMT build when this stage



I2C / SMBUS ADDRESSING

DEVICE HEX ADDRESS
DDR SO-DIMM 0 A0 10100000
DDR SO-DIMM 1 A4 10100100
A A


CLOCK GENERATOR (EXT.) D2 11010010
USB HUB 5C 01011100

Security Classification
2005/03/10
Compal Secret Data
2006/03/10 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-2821P 0.5
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, November 25, 2005 Sheet 3 of 52
5 4 3 2 1
5 4 3 2 1




+3VS
7 H_A#[3..31]
JP8A
H_D#[0..63] 7 5/10
R443
H_A#3 J4 E22 H_D#0 XDP_DBRESET#_R 1 2 @ 1K_0402_5%
H_A#4
H_A#5
L4
A3#
A4#
YONAH D0#
D1# F24 H_D#1
H_D#2
ITP-XDP Connector +VCCP
M3 A5# D2# E26
H_A#6 K5 H22 H_D#3
H_A#7 A6# D3# H_D#4 This shall place near CPU
M1 A7# D4# F23
H_A#8 N2 G25 H_D#5 JP31 XDP_TDI R524 1 2 56_0402_5%
H_A#9 A8# D5# H_D#6
J1 E25 1 2
D H_A#10 A9# D6# H_D#7 XDP_BPM#5 GND0 GND1 XDP_TMS R523 1 56_0402_1% D
N3 E23 3 4 2
H_A#11 A10# D7# H_D#8 XDP_BPM#4 OBSFN_A0 OBSFN_C0
P5 K24 5 6
H_A#12 A11# D8# H_D#9 OBSFN_A1 OBSFN_C1 XDP_TDO R525 1 56_0402_5%
P2 G24 7 8 2
H_A#13 A12# D9# H_D#10 XDP_BPM#3 GND2 GND3
L1 J24 9 10
H_A#14 A13# D10# H_D#11 XDP_BPM#2 OBSDATA_A0 OBSDATA_C0 XDP_BPM#5 R526 1 56_0402_5%
P4 J23 11 12 2
H_A#15 A14# D11# H_D#12 OBSDATA_A1 OBSDATA_C1
P1 H26 13 14
H_A#16 A15# D12# H_D#13 XDP_BPM#1 GND4 GND5 XDP_TRST# R521 1 56_0402_5%
R1 F26 15 16 2
H_A#17 A16# D13# H_D#14 XDP_BPM#0 OBSDATA_A2 OBSDATA_C2
Y2 K22 17 18
H_A#18 A17# D14# H_D#15 OBSDATA_A3 OBSDATA_C3 XDP_TCK R522 1 56_0402_5%
U5 H25 19 20 2
H_A#19 A18# D15# H_D#16 GND6 GND7
R3 N22 21 22
H_A#20 A19# D16# H_D#17 OBSFN_B0 OBSFN_D0
W6 K25 23 24
H_A#21 A20# D17# H_D#18 OBSFN_B1 OBSFN_D1
U4 P26 25 26
H_A#22 A21# D18# H_D#19 GND8 GND9
Y5 R23 27 28
H_A#23 A22# D19# H_D#20 OBSDATA_B0 OBSDATA_D0
U2 L25 29 30
H_A#24 A23# D20# H_D#21 OBSDATA_B1 OBSDATA_D1
R4 L22 31 32
H_A#25 A24# D21# H_D#22 GND10 GND11
T5
A25# ADDR GROUP DATA GROUP D22#
L23 33
OBSDATA_B2 OBSDATA_D2
34
H_A#26 T3 M23 H_D#23 35 36
H_A#27 A26# D23# H_D#24 R442 OBSDATA_B3 OBSDATA_D3
W3 P25 37 38
H_A#28 A27# D24# H_D#25 H_PWRGOOD 2 GND12 GND13
W5
A28# D25#
P22 1H_PWRGOOD_R 39
PWRGOOD/HOOK0 ITPCLK/HOOK4
40 CLK_CPU_XDP CLK_CPU_XDP 15
H_A#29 Y4 P23 H_D#26 1K_0402_5% 41 42 CLK_CPU_XDP# CLK_CPU_XDP# 15
A29# D26# HOOK1 ITPCLK#/HOOK5
H_A#30 W2
A30# D27#
T24 H_D#27 +VCCP 43
VCC_OBS_AB VCC_OBS_CD
44 +VCCP 1K_0402_1%
H_A#31 Y1 R24 H_D#28 2 1 45 46 H_RESET#_R 1 R441 2 H_RESET#
7 H_REQ#[0..4] A31# D28# HOOK2 RESET#/HOOK6
L26 H_D#29 C539 0.1U_0402_16V4Z 47 48 XDP_DBRESET#_R 2 R444 1 XDP_DBRESET#
H_REQ#0 D29# H_D#30 HOOK3 DBR#/HOOK7 200_0402_1%
K3 T25 49 50
H_REQ#1 REQ0# D30# H_D#31 ICH_SMBDATA GND14 GND15 XDP_TDO
H2 N24 51 52
H_REQ#2 REQ1# D31# H_D#32 ICH_SMBCLK SDA TD0 XDP_TRST#
K2 AA23 53 54
H_REQ#3 REQ2# D32# H_D#33 SCL TRST# XDP_TDI
J3 AB24 55 56
H_REQ#4 REQ3# D33# H_D#34 XDP_TCK TCK1 TDI XDP_TMS
L5 V24 57 58
REQ4# D34# H_D#35 TCK0 TMS XDP_PRE
D35#
V26 59
GND16 GND17
60 1 R191 2 0_0402_5%
H_ADSTB#0 L2 W25 H_D#36
7 H_ADSTB#0 ADSTB0# D36#
H_ADSTB#1 V4 U23 H_D#37 SAMTE_BSH-030-01-L-D-A
7 H_ADSTB#1 ADSTB1# D37#
U25 H_D#38
C D38# H_D#39 C
U22
D39# H_D#40
AB25
D40# H_D#41
W22
D41# H_D#42
Y23
CLK_CPU_BCLK D42# H_D#43
15 CLK_CPU_BCLK A22 AA26
CLK_CPU_BCLK# BCLK0 D43# H_D#44
15 CLK_CPU_BCLK# A21
BCLK1 HOST CLK D44#
Y26
Y22 H_D#45
D45#
D46#
AC26
AA24
H_D#46
H_D#47
Thermal Sensor ADM1032AR-2
H_ADS# D47# H_D#48
7 H_ADS# H1 AC22
H_BNR# ADS# D48# H_D#49 +3VS
7 H_BNR# E2 AC23
H_BPRI# BNR# D49# H_D#50
7 H_BPRI# G5 AB22