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TE5 Block Diagram 01
A A
USB-11
LCD/CCD Con. P24
EXT_LVDS
DDRIII-SODIMM1
DDRIII-SODIMM2 Sandy Bridge(UMA+VGA) VGA EXT_CRT
PCI-E x16 daughter board CRT Con.
P13,14 N12M-GE/N12P-GV/N12P-LP P24
DDR SYSTEM MEMORY
PCI-E P24
Dual Channel DDR III P15,16,17,18,19,20,21 EXT_HDMI
HDMI Level Shift
P23 HDMI Con. P23
rPGA 989
P3,4, 5, 6,
VRAM DDR3-64M*16
SATA - HDD Re-Driver VRAM DDR3-128M*16
P28 P28
FDI
DMI
DMI(x4)
SATA - ODD
P28 SATA 0
FDI USB-11
DMI INT_LVDS LCD/CCD Con. P24
SATA 4 PCI-E
B B
SATA
Graphics Interfaces
INT_CRT daughter board
P24 CRT Con. P24
INT_HDMI HDMI Level Shift
P23 HDMI Con. P23
USB 2.0 Con. daughter board USB-8
CougarPoint
USB-5 PCIE-3
SIM CARD. USB
P25 USB-3 3G P25
PCH
USB-4
Card Reader Con. P7,8, 9, 10, 11,12
PCIE-6
P31
USB-13 WLAN
RTC P25
USB 2.0 Con. USB-9
P26
BATTERY PCIE-7
C
Giga/10/100 Lan C
P8 P30
PCI-E
PCIE-2
Azalia IHDA
USB 3.0 P27
NVRAM
LPC
LPC
Audio Codec EC
P29 P32
POWER SYSTEM
ISL88731C (Charge) P35
RT8210B (System 5V/3V) P36
FAN K/B Con. HALL Sensor SPI Flash Touch Pad /B Power /B P37
RT8207L (DDR 1.5V)
MDC Con. MIC JACK HP SPK Con. Con. Con.
RT8238A (+VTT) P38
P29 P29 P29 P29 P3 P33 P24 P32 P33 P33
TPS51461 (+VCCSA) P39
D D
ISL95835 (+VCC_CORE) P40
G966A (+1.8V) P41
ISL95870A (+GPU_CORE) P42
Quanta Computer Inc.
PROJECT : TE5
Size Document Number Rev
1A
Block Diagram
Date: Wednesday, January 05, 2011 Sheet 1 of 44
1 2 3 4 5 6 7 8
CONTROL Power States
02
Table of Contents POWER PLANE VOLTAGE SIGNAL ACTIVE IN
PAGE DESCRIPTION
VIN 10V~+19V S0~S5
1 Schematic Block Diagram +VCCRTC +3.0V~+3.3V S0~S5
2 Front Page
+3V +3.3V MAIN_ON S0
3-6 Processor
7-12 PCH +3V_S5 +3.3V S5_ON S0~S5
8 RTC
A +3V_HDP +3.3V MAIN_ON S0 A
13-14 DDRIII SO-DIMM
15-21 VGA +3VPCU +3.3V AC/DC Insert enable S0
23 HDMI comm part
+5V +5V MAIN_ON S0
24 LCD Panel
CRT & CRT BUS SWITCH +5V_S5 +5V S5_ON S0~S5
CCD
+5VPCU +5V AC/DC Insert enable S0~S5
HALL SENSOR&BACK LIGHT SWITCH
25 MINI Card (Wi-Fi & WIMAX) WIMAX_P +3.3V WMAX_P for WLAN
MINI Card 2nd
+1.8V +1.8V MAIN_ON S0
MINI Card 3nd
26 USB 2.0 +1.5V +1.5V MAIN_ON S0
27 USB 3.0
+1.5V_SUS +1.5V SUSON S0~S3
28 SATA ODD
Main SATA HDD & 2nd SATA HDD +VCC_CORE VRON S0
29 Codec (CX20587)
+VTT +1.05V MAIN_ON S0
30 Atheros LAN
31 3 IN 1 Card reader +1.05V +1.05V MAIN_ON S0
32 EC NPCE791L
+VAXG MPWROK S0
33 INT KeyBoard & K/B LED Power
TP board
B B
Power SW
HOLE
34 LED / EMI
35 Charger (ISL88731C) GND PLANE PAGE
36 System 5V/3V (RT8210B)
8769AGND
37 DDR1.5V(RT8207L)/1.05VSUS 32
38 +VTT/+1.05V (RT8238A) Audio_GND
29
39 +VCCAS(TPS51461)
Shield_GND
40 +VCC_CORE(ISL95835HRTZ) 29
41 +1.8V (G966A)/Discharge
GND ALL
42 +GPU_CORE(ISL95870AHRUZ)
ISL95870A_AGND 29
C C
D D
Quanta Computer Inc.
PROJECT : TE5
Size Document Number Rev
1A
POWER STAGE AND BOI-FUNCTION
Date: Wednesday, January 05, 2011 Sheet 2 of 44
1 2 3 4 5 6 7 8
5 4 3 2 1
Sandy Bridge Processor (DMI,PEG,FDI)
U15A
PEG_COMP
Sandy Bridge Processor (CLK,MISC,JTAG)
U15B
03
PEG_ICOMPI J22
PEG_ICOMPO J21
{7} DMI_TXN0 B27 DMI_RX#[0] PEG_RCOMPO H22 BCLK A28 CLK_CPU_BCLKP_R R417 *SHORT_4 CLK_CPU_BCLKP {9}
MISC
CLOCKS
{7} DMI_TXN1 B25 DMI_RX#[1] PEG_RXN[0..15] {15} {8} H_SNB_IVB# C26 PROC_SELECT# BCLK# A27 CLK_CPU_BCLKN_R R418 *SHORT_4 CLK_CPU_BCLKN {9}
{7} DMI_TXN2 A25 DMI_RX#[2]
B24 K33 PEG_RXN0
{7} DMI_TXN3 DMI_RX#[3] PEG_RX#[0]
M35 PEG_RXN1 SKTOCC# AN34
PEG_RX#[1] TP19 SKTOCC#
B28 L34 PEG_RXN2 A16 CLK_DPLL_SSCLKP_R R78 1K_4
{7} DMI_TXP0 DMI_RX[0] PEG_RX#[2] DPLL_REF_CLK
B26 J35 PEG_RXN3 A15 CLK_DPLL_SSCLKN_R R84 1K_4
{7} DMI_TXP1 DMI_RX[1] PEG_RX#[3] DPLL_REF_CLK# +VTT
DMI
A24 J32 PEG_RXN4
{7} DMI_TXP2 DMI_RX[2] PEG_RX#[4] PEG_RXN5
{7} DMI_TXP3 B23 H34
DMI_RX[3] PEG_RX#[5] PEG_RXN6 TP_CATERR#
H31 TP18 AL33
D PEG_RX#[6] PEG_RXN7 CATERR# D
{7} DMI_RXN0 G21 G33
DMI_TX#[0] PEG_RX#[7] PEG_RXN8
{7} DMI_RXN1 E22 G30
DMI_TX#[1] PEG_RX#[8]
THERMAL
F21 F35 PEG_RXN9
{7} DMI_RXN2 DMI_TX#[2] PEG_RX#[9] PEG_RXN10
{7} DMI_RXN3 D21 E34 {32} EC_PECI AN33 R8 CPU_DRAMRST# {22}
DMI_TX#[3] PEG_RX#[10] PEG_RXN11 PECI SM_DRAMRST#
E32
DDR3
MISC
PEG_RX#[11] PEG_RXN12
{7} DMI_RXP0 G22 D33
DMI_TX[0] PEG_RX#[12] PEG_RXN13
{7} DMI_RXP1 D22 D31
DMI_TX[1] PEG_RX#[13]
PCI EXPRESS* - GRAPHICS
F20 B33 PEG_RXN14 {32,40} H_PROCHOT# R104 56_4 H_PROCHOT#_R AL32 AK1 SM_RCOMP_0 R95 140/F_4
{7} DMI_RXP2 DMI_TX[2] PEG_RX#[14] PEG_RXN15 PROCHOT# SM_RCOMP[0] SM_RCOMP_1 R52
C21 C32 A5 25.5/F_4
{7} DMI_RXP3 DMI_TX[3] PEG_RX#[15] PEG_RXP[0..15] {15} SM_RCOMP[1]
A4 SM_RCOMP_2 R53 200/F_4
U:C2A
PEG_RXP0 SM_RCOMP[2]
J33
PEG_RX[0] PEG_RXP1 PM_THRMTRIP#
L35 AN32
PEG_RX[1] PEG_RXP2 THERMTRIP#
K34
PEG_RX[2] PEG_RXP3
A21 H35
FDI0_TX#[0] PEG_RX[3] PEG_RXP4
H19 H32
FDI0_TX#[1] PEG_RX[4] PEG_RXP5
E19 G34
FDI0_TX#[2] PEG_RX[5] PEG_RXP6
F18 G31 AP29 XDP_PRDY#_R TP83
Intel(R) FDI
FDI0_TX#[3] PEG_RX[6] PEG_RXP7 PRDY#
B21 F33 AP27 XDP_PREQ# TP87
FDI1_TX#[0] PEG_RX[7] PEG_RXP8 PREQ#
C20 F30 PEG_TXN[0..15] {15}
FDI1_TX#[1] PEG_RX[8] PEG_RXP9
D18 E35 AR26 XDP_TCLK
FDI1_TX#[2] PEG_RX[9] TCK
PWR MANAGEMENT
E17 E33 PEG_RXP10 AR27 XDP_TMS
JTAG & BPM
FDI1_TX#[3] PEG_RX[10] PEG_RXP11 PM_SYNC_R TMS
F32 {7} PM_SYNC R100 *SHORT_4 AM34 AP30 XDP_TRST#
PEG_RX[11] PEG_RXP12 PM_SYNC TRST#
D34
PEG_RX[12] PEG_RXP13
A22 E31 AR28 XDP_TDI_R TP78
FDI0_TX[0] PEG_RX[13] PEG_RXP14 TDI
G19 C33 AP26 XDP_TDO_R TP77
FDI0_TX[1] PEG_RX[14] PEG_RXP15 R92 *SHORT_4 H_PWRGOOD_R TDO
E20 B32 {10} H_PWRGOOD AP33
FDI0_TX[2] PEG_RX[15] UNCOREPWRGOOD
G18
FDI0_TX[3] PEG_TXN0_C C213 [email protected]/10V_4X PEG_TXN0 R96 10K_4
B20 M29
FDI1_TX[0] PEG_TX#[0] PEG_TXN1_C C220 [email protected]/10V_4X PEG_TXN1 XDP_DBR#_R R430 *SHORT_4
C19 M32 AL35 XDP_DBRST# {7}
FDI1_TX[1] PEG_TX#[1] PEG_TXN2_C C222 [email protected]/10V_4X PEG_TXN2 PM_DRAM_PWRGD_R DBR#
D19 M31 {22} PM_DRAM_PWRGD_R V8
FDI1_TX[2] PEG_TX#[2] PEG_TXN3_C C224 [email protected]/10V_4X PEG_TXN3 SM_DRAMPWROK
F17 L32
FDI1_TX[3] PEG_TX#[3] PEG_TXN4_C PEG_TXN4
L29 C225 [email protected]/10V_4X AT28 XDP_BPM0_R TP85
PEG_TX#[4] PEG_TXN5_C PEG_TXN5 BPM#[0]
FDI_FSYNC0 J18 K31 C229 [email protected]/10V_4X +VTT R98 *75/F_4 AR29 XDP_BPM1_R TP81
FDI0_FSYNC PEG_TX#[5] PEG_TXN6_C PEG_TXN6 BPM#[1]
FDI_FSYNC1 J17 K28 C231 [email protected]/10V_4X AR30 XDP_BPM2_R TP79
FDI1_FSYNC PEG_TX#[6] PEG_TXN7_C PEG_TXN7 CPU_PLTRST# *43_4 CPU_PLTRST#_R BPM#[2]
J30 C232 [email protected]/10V_4X R103 AR33 AT30 XDP_BPM3_R TP84
PEG_TX#[7] PEG_TXN8_C PEG_TXN8 RESET# BPM#[3]
FDI_INT H20 J28 C236 [email protected]/10V_4X AP32 XDP_BPM4_R TP75
FDI_INT PEG_TX#[8] PEG_TXN9_C PEG_TXN9 BPM#[4]
H29 C256 [email protected]/10V_4X AR31 XDP_BPM5_R TP80
PEG_TX#[9] PEG_TXN10_C PEG_TXN10 BPM#[5]
FDI_LSYNC0 J19 G27 C259 [email protected]/10V_4X AT31 XDP_BPM6_R TP82
FDI0_LSYNC PEG_TX#[10] PEG_TXN11_C PEG_TXN11 BPM#[6]
FDI_LSYNC1 H17 E29 C260 [email protected]/10V_4X AR32 XDP_BPM7_R TP76
FDI1_LSYNC PEG_TX#[11] PEG_TXN12_C C270 [email protected]/10V_4X PEG_TXN12 BPM#[7]
C F27 C
PEG_TX#[12] PEG_TXN13_C C274 [email protected]/10V_4X PEG_TXN13