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1
NASA STANDARD
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1
SPACECRAFT COMPUTER (NSSC-SI)
4
4
2
PRINCIPLES OF OPERATION
6
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I
Uncl A S
0252763
'- I;I"; 1 ENGRG NOTICE LTR
Initial Release
DESCRIPTION
- a-
YAIC
, 2 / 1 5 / 77
nrr$$u*LU
Errata Sheets 5/15/79
The attached pages are replacements or additions to the
NSSC-I1 Principles of Operation.
CONTR NO.
NAS8-32808 INTE R NAT1ONA L BUS1NESS MACHIN ES CORP.
FEDERAL SYSTEMS DIVISION
PREPARATION GAITHERSBURG, MARYLAND
NASA Standard Spacecraft
Computer I1 (NSSC-11) Principles
of Operation
SIZE CODE IDENT NO, DWG NO.
7935402
I SCALE WT SHEET
i TABLE OF CONTENTS (CONTINUED)
d
f Section Paragraph Title PaRe
7.4.4 Branch on Index High 88
7.4.5 Branch on Index Low o r Equal 89
7.4.6 Execute 89
7.4.6.1 Execute Exceptions 91
i
4 92
.
! VI11 STATUS SWITCHING
8.1 Program S t a t e s . 92
8.1.1 Problem S t a t e 92
8.1.2 Wait S t a t e 93
8.2 Protection 94
8.2.1 Area I d e n t i f i c a t i o n 94
8.2.2 P r o t e c t i o n Action 94
83
. Program S t a t u s Word 94
8.4 I n s t r u c t i o n Format 96
8.5 Instructions 97
8.5.1 Load P W S 98
8.5.2 S e t Program Mask 99
8.5.3 S e t System Nask 99
8.5.4 Supervisor Call 99
8.5.5 S e t Storage Key 100
8.5.6 Test and S e t 100
8.5.7 S t a r t Input Output 101
8.5.8 T i m e r Read and S e t 103
8.5.9 Diagnose 104
86
. Status-Switching Exceptions 104
INTERRUPTIONS 106
9.1 I n t e r r u p t i o n Action 106
9.1.1 I n s t r u c t i o n Execution 106A
9.1.2 Source I d e n t i f i c a t i o n 107
9.1.3 Location Determination 108
9.2 Input/Output I n t e r r u p t i o n 108
9.3 Program I n t e r r u p t i o n 109
9.3.1 Operation Exception 110
9.3.2 Privileged-Operaticri Exception 110
9.3.3 Execute Exception 110
9.3.4 P r o t e c t i o n Exception 110
9.3.5 Addressing Exception 110
9.3.6 S p e c i f i c a t i o n Exception 111
9.3.7 Data Exception 111
9.3.8 Fixed-Point-Overflow Exception 111
9.3.9 F i xe d-P o i n t - D i v i tl e Ex ce p t i o n 111
9.3.10 Exponent-Overflow Exception l l lA
9.3.11 Exponent-Underf low Exception l l lA
3.3.12 S i gn i f i can c e E xcc p t i 011 l l lA
9.3.13 Floating-Point-Divide Exception l l lA t
9.3.14 Buffered. 110 Exception 112 c
c'
9.3.15 Supervisor-Call I n t e r r u p t i o n 112
-
c.
..
... . ._ - - . ___ . ~. . - ._. . -
TABLE OF CONTENTS
Paranraph -Title Pane
NSSC-I1 ARCHITECTURE i
11
. NSSC-I1 Instruction Set 1
1.2 Exceptions 1
1.2.1 Input/Output 1
1.2.2 Timer 1
1.2.3 Storage Protect 2
1.2.4 Execution Times 2
102.5 \
Unpredictable Reeulte 2
1.2.6 Addrearing Exception 2
102.7 Addressing 2
SYSTEM STRUCTURE
2.1 Main Storage
2.2 Ad dreea ing
2.3 Information Processing
24
. Storage Protection
CPU 6
3.1 Central Proceeeing Unit Function8 6 \
3 3.2 General Regietare 7
3*3 Arithmetic and Logical Unit 7
303.1 Fixed Point Arithmetic 7
3.4 Decimal Numbere 8
35
. Logical Operations 9
3.6 Program Execution 10
3.6.1 Inatruction Format 10
3.602 Addrees Generation .lo
3.6.2.1 Base Addrese (B) 12
3.6.2.2 Index (X) 12
3623
... Diaplacament (D) 12
3.603 Sequential Inrtruction Execution 13
3.6.3.1 Branching 14
3.6.4 Program Statue Word 14
...
3.605
'3 6 5 1
3.6.5.2
Interruption
External Interrupts
Program Interrupts
15
16
17
3.6.5.3 Input/Output fnterruption 19
3.606 Machlne States 19
3.6.6.1 Running or Waiting State 19
306.6.2 Maeked or Interruptible State 19
3.6.6.3 Supervisor or Problem State 19
3.7 Syrtm I/O 19
3.7.1 Direct 1/0 20
307.2 . Buffered 1/0 20
TABLE OF CONTENTS (CONTINUED)
Section PrrasraDb -
Title Pam
373
.. Direct Memory Accere (DMA) 20
3.7.4 Input /h t @era tione
tpu 20
307.5 Buffered 1/0 Statue Word 22
3.7.6 Service Interrupt 22
377
.. T8E 1/0 Devices 23
3*8 Soft stop 28
3.9 Teat Support Equipment 28
3.9.1 Function Code 28
3.9.2 Syrtem Reset 30
Iv FfXED-POINT ARITHMETIC 31
41
. Data Format 31
4.2 Number Repreeantation 32
4.3 Condition Code 33
4a 4 Inotruction Format . 33
4.5 Inrtructionr , 34
4.5*1 Load 36
4.5.2 Lord Halfword 36
4.5.3 Lord and Tart 37
4.5.4 Load Complament 1
37
4.5.5 Load Poritive 38
465.6 Load Negative 38
4.5.7 Load Multiple 39
405.8 Add 39
4.5.9 Add Halfword 40
4,SalO Add Logical 41
4.5.11 Subtract 42
404.12 Subtract Halfword 42
4.5.13 Subtract Logical 43
4.5.14 Compare 44
4.5.15 Compare Halfword 45
4o5.16 Multiply 45
405.17 Multiply Halfword 46
4.5.16 Divide 47
4.5.19 Convart to Binary 48
4.5.20 Oonvert to Decimal 49
405.21 Store 49
405.22 Store Halfword 50
4.5.23 Store Multiple 50
4.5.24 Shift Left Single 51
4.5.25 Shift Right Single 52
4.5.26 Shift Left Double 53
4.5027 Shift Right Double 53
4.6 Flxad-Point Arithmetic Exceptions 54
iii
TABLE OF CONTENTS (CONTIXUED)
0
9wi0n Ew!a?mh Title
V DECIMAL ARITHMETIC 56
Sal Data Format 56
Salal Packad Decimal Number 56
Sa1.2 Zoned Decimal Number 56
Sa2 Nunbar Representation 56
5.3 Inatructione 5T
5a3.1 Pack 57
5.3.2 Unpack 58
5a3.3 M o w with Offeat 59
VI LOGICAL OPERATION 60
61
. Data Format 60
6ala1 Fixed-Length Logical Infornution 60
6ala2 Variable-Length Logical Information 61
6.2 Condition Coda 62
6a3 Iartruction Format 62
6a4 Inrtructlonr 64
6.4a1 Mova 65
6.4a2 Move Numrricr 66
6a4a3 Move Zonea C6
6.4.4 Compara Logical 67
6a4aS And 68
6,4,6 or 69
6a4.7 Exclurive Or 70
6a4.0 T u t Under Mark 71
6a4.9 Inrart Choractar ?2
6a4a10 Store Character 72
6.4.11 Lord Addreir 72
6.4.12 Trarlate 73
6.4.13 Tranrlate and Teot 74
6.4a14 Shift Left Single 75
6a4a15 ' Shift Right Single 75
6a4.16 Shift Left Double 76
6a4.17 Shift Right Double 76
6.5 Logical Operation Exceptionr 77
VI1 BRANCHING 79
7.1 Normal Sequential Oparation . 79
7alal Saquential Operation Excoptionr 80
7a2 Dacielon-Making 02
7a 3 Inrtruction Fornrcrtr 02
7a4 Branching Inrtructiona 84
7a4a1 Branch on Condition a4
744a2 Branch and Link 87
7.4.3 Branch on Count 07
TABLE OF CONTENTS (CONTINUED)
Paranra~b -
Title Pane
744
.. Branch on Index High 88
7.4.5 Branch on Index Low or Equal 89
746
.. Execute 89
7461
... Execute Exception6 91
STATUS SWITCHING 92
8.1 Program Statee 92
8.1.1 Problem State 92
8.1.2 Wait State 93
8.2 Protection 94
8.2.1 k o a Identification 94
8.2.2 Protection Action 94
8.3 Program Status Word 94
8.4 Iartruction Format 96
8.5 Inetructionr 97
8mSel Load PSW 98
8.5.2 Sot Program Mark 99
8.5.3 Sot Syrtem Mark 99
8.5.4 Suporvieor Call 99
895
.. Sat Storage Key 100
8.5.6 Teet and Set IGO
8.567 Start Input Output 101
858
.. Tlmer Read and Set 103
8.569 Diagnose 104
8.6 stAtU6-sWitChing Exceptions 104
INTERKUPTXONS 106
9.1 Interruption Action 106
9.1.1 Itutruction Execution 106
912
.. Source Identification 107
913
.. Location Detarmlaation 108
9.2 Iaput /&A t .Interruption
tpu 108
93
. Program Interruption 109
9.3.1 Oporation Exception 110
9.3.2 Privileged-Operation Excoption 110
9.3.3 Execute Exception 110
9.3A Ptotoction Exception 110
9.3.5 Mdreering Exception 110
,9s3m6 Specification Exception 111
93'
..) Data Exception 111
9.3.8 Fixed-Pointdverflaw Exception 111
939
.. Fixed-Point-Divide Exception 111
9.3.10 Buffarad f / O Exception 112
9.3.11 Supervieor-Call Interruption 112
t
&._ _.-__. . .... _. . _.__ ... .._-_ -..-
.-.. .-,. *-.-.-..(I ..*.
-,. ... . ...
.-
<.
e-
TABLE OF CONTENT8 (CONTINUED)
9a4 Erternrl Interruption 112
9a4.l Tfmor 113
9.4.2 Intarrupt Key 113
94.3 Intrrval Tlmer 113
9*5 Machine-Chack Interruption 114
.:%
:*
X SHORT PRECISION OPTION 115
10.1 Data Format 115
loa2 Number Representation 116
loa3 Condition Code 116
10.4 Inntruction Format 117
10.5 Inrtructioni 119
10.5.1 ADD Halfword 121
10.5.2 ADD Short 121
10.5.3 Branch Unconditional 122
1OaSa4 Compare Halfword 123
10.5as Compare ~ogicalShort 124
10a5o6 Compare Short 125
10.5a7 Divide Short 126
1OeSa8 Load Mdrers Short 127
1OaSa9 Load Complement Short 127
.
10,s a 10
10.9 11
10 5 a 12
Load Full to Short Regintar
Load Halfword
Load Negativr Short
128
129
129
loa5a 13 Load Poiitive Short 130
10oSa14 Load Short ' 131
10*5.15 Load and Teat 131
10.5 a 16 Load and Test Short 132
10 5 a 17 Mu1 tiply Halfword 133
10.5 18 Multiply Short 133
1005.19 Normallee 134
1OaSa20 AND Short 135
10. 5 a 21 OR Short . 136
10a5.22 Shift Left Arithmatic Short 137
10e 5 a 23 Shift Left Logical Short 138
10.5 a 24 Shift Right Arithmetic Short 139
lOaSa25 Shift Right Logical Short 140
10a 5 a 26 Subtract Halfword 140
10a5.27 Subtract Short 141
10.9 a28 Tort Bitr 142
10a5a29 Exclurive OR Short 143
loa6 Short Precirion Exceptionr 144
-
section - .PrragrrPh Title
- *
XI DOUBLE PRECISION FIXED-POINT
AMTIPIETIC OPTION 146
11e 1 Data Format 146
11e 2 Nunbar Rrprarantrtlon 146
11 e 3 Condition Code 147
11e 4 Inrtruction Forput 148
11e 5 Inrtructionr 149
11 5 Lord Double 149
11 e 5 Load Complement Double 150
11e 5 Add Double 150
11 e 5 Subtract Doublr 151
11e 5 Comprrr Doublr 152
11e 5 Store Doublr 153
11e 6 Double Prrcirlon Fixed-Point 153
Arithmetic Excrptionr
XI1 FLOATING-POINT ARITIWTIC
12 e1 Data Formrt 155
12 e2 Numbor Rrprrrrntrtlon 156
12e3 Normlitrtion 157
12e4 Condition Coda u7
12eS Inetructlon Format 1%
12 e6 Inrtructlonr 159
12e6e1 Lord 160
12e6.2 Lord and Tart 16Z
12e6e3 Load Complrmrnt 162
12e6.4 Lord Poritlvr 162
12.6.5 Load Negatlvr 162
12,666 Add N o m l i t r d 163
12e6.7 Add Unnonnrlitrd 164
12.6.8 Subtract Normalired 165
12e6.9 Subtract Unnormlirad 166
12e6.10 Comprrr 166
12e 6 e 11 Ulva 167
12 e 6 e 12 Mu1 tlply 168
12e6e13 Mvidr 169
12 e6 e 14 Storr 171
12.7 Florting-Point Arithmatic 171
Excop tionr
PREFACE
Thio document is t h e Machine Referance Manual f o r t h e NSSC-11. It p r o v i d e s
i
a d e o c r i p t i o n of t h e ryetem o t r u c t u r e , t h e a r i t h m e t i c , l o g i c a l , branching,
s t a t u s a s i t c h i n g , f / O o p e r a t i o n o , and t h e i n t e r r u p t and timer syrtcunr.
The NSSC-11 i o a 1 6 - b i t , f i x e d p o i n t , microprogram c o n t r o l l e d , g e n e r a l pur-
pore computer.
i
The NSSC-I1 a r c h i t e c t u r e is t h e rame as t h e IBM System/360 a r c h i t e c t u r e .
The b a s i c NSSC-I1 s u p p o r t s 83 of t h e 87 i n s t r u c t i o n s i n t h e IBM System/360
Standard I n s t r u c t i o n S e t ; t h e b a s i c NSSC-I1 a l s o s u p p o r t s t h r e e unique
i n s t r u c t i o n r which c o n t r o l t h e t i m e r s , I / O , and s t o r a g e p r o t e c t i o n . The
f i r s t n i n e s e c t i o n s of t h i s document delrcribe t h e b a s i c NSSC-11.
A s h o r t p r e c i s i o n o p t i o n l e a v a i l a b l e f o r t h e NSSC-11. This o p t i o n con-
sirto of 53 a d d i t i o n a l f n e t r u c t i o n s which d e a l p r i m a r i l y w i t h 16-bit \
operands. Them i n e t r u c t i o n r g e n e r a l l y e x e c u t e f a e t e r t h a n t h e i r counter- ,
p a r t 6 i n t h e b a e i c NSSC-I1 i n e t r u c t i o n set, which o p e r a t e on 32-bit operands.
An a d d i t i o n a l i n s t r u c t i o n format is included i n t h i r o p t i o n which i n c r e a s e s
e x e c u t i o n rpeed and reduces main s t o r a g e r e q u i r m o n t s . The s h o r t p r a c i o i o n
o p t i o n is d e s c r i b e d in S e c t i o n X,
A double p r e c i r i o n f i x e d p o i n t o p t i o n is also a v a i l a b l e f o r t h e NSSC-If.
This o p t i o n c o n r l o t e of 10 a d d i t i o n a l i n a t r u c t i o n s which o p e r a t e w i t h
64-bit f i x e d p o i n t operands. This o p t i o n is d e r c r i b e d i n Section X I .
A f l o a t i n g p o i n t o p t i o n is a l s o a v a i l a b l e f o r t h e NSSC-11, This option
cansirtr of 22 a d d i t i o n a l i n r t r u c t i o n s which are ueed t o perform c a l c u l a -
tione on oprrandr w i t h a wide range of magnitude and y i e l d r e e u l t e s c a l a d
t o p r e s e r v e p r e c i s i o n . T h i s o p t i o n is d e s c r i b e d i n S e c t i o n X I I ,
The following NSSC-I1 documents contain essentially the same information a e
provided in t h e correrponding Syetem/360 documentatim r e f e r e n c e d herein:
NSSC-I1 h e e m b l e r Language, IBM Number 7935401
NSSC-I1 Linkage E d i t o r , B Number 7935413
IM
viii
SECTION I
NSSC-I1 ARCHITECTURE
1.1 NSSC-11 INSTRUCTION ___
SET
The NSSC-I1 is compatible with the IBM System/360 Problem State Standard
Instruction Set. Problem programs written for the S/360 Standard
Instruction Set will execute properly without change on the NSSC-XI.
There are171valid NSSC-I1 instructions. Eighty-three of them are from the
87-member S/360 Standard Instruction Set. Omitted from the NSSC-I1 set
are HZ09 SIO, TCH, and TfO.
Three additional iaotructione, also described below, ars:
Mnemonic OP Code Format
Timer Read and Set TMRS A4 RS
Start I/O Sf0 As Rs
Set Storage Key SSK 08 RR
Note that although mnemonic SI0 i r ured for Start I/O, and is the only NsSc-111
f/O inotruction, it is not the same inrtruction (and doer not have the eame 1
op code) ar the 360 SIO. Op codes A4 and AS are unuaed in 360. SSK does
have the lame op coda 06 360 SSK, but perfoxnu a different function, am I
dercribed below.
1.2 EXCEPTIONS
The NSSC-I1 is a Supervisor State compatible with the IBM Syrtem/360
with the following exceptions:
1a 2 1 INPUT/OUTPUT
The 1/0 portion of the NSSC-I1 provides the means of communication between
the system f / O and test support equipment (TSE) with the CPU and the main
store (MS). In the 16 bit NSSC-I1 the 1/0 is implemented as a 16 bit
parallel channel providing direct I/O, buffered I/O, external interrupt,
and direct memory access (DMA). The 16 bit channel is SP-1 hardware com-
-
patible. There is only one 1/0 instruction the SI0 (Start 1/01
instruction which controls direct I / O . All other 1/0 i r device controlled.
1.2.2 TIMER
The NSSC-I1 has A real time clock and an interval timer, each containing both
hardware and microprogramrued elements. Both are accessed by using the TMRS
instruction. The S/360 interval timer in memory location 80 is not supported.
-1-
The i n t e r v a l timer (INTIMER) i s 1 6 b i t s and is decremented every 112.64
microseconds. It h a s a maximum of 7 . 3 8 seconds. Underflow of t h e
i n t e r v a l timer causes a timer e x t e r n a l i n t e r r u p t (which can be masked;
see paragraph 3.6.5.1, E x t e r n a l I n t e r r u p t . )
The r e a l t i m e c l o c k (RTC) i s 3 2 b i t s and i s incremented e v e r y 112.64
microseconds. It h a s a maximum of 5 d a y s , 14 h o u r s , 23 minutes, and
5.116 seconds. I t causes no i n t e r r u p t on overflow.
1.2.3 . STORAGE PROTECT
The s i z e of t h e s t o r a g e p r o t e c t blocks i n t h e NSSC-I1 i s 1 0 2 4 b y t e s
( 5 1 2 halfwords) and t h e operand of t h e SSK (Set Storage Key) i n s t r u c -
t i o n s u p p o r t s one b i t f o r CPU and Buffered I f 0 p r o t e c t i o n and a second
b i t f o r DMA p r o t e c t i o n . The 4 o r 5 b i t p r o t e c t i o n key of S / 3 6 0 i s n o t
supported. The i n s t r u c t i o n ISK ( I n s e r t Storage Key) does n o t e x i s t on
t h e NSSC-11.
1.2.4 EXECUTION TIMES
The i n s t r u c t i o n execution t i m e i s n o t t h e same f o r t h e N S C C - I 1 and any \
I B M 360.
1.2.5 UNPREDICTABLE RESULTS
These occur due t o a d d r e s s i n g e r r o r s , e t c . , on t h e IBH 360 series and w i l l 1,
n o t n e c e s s a r i l y b e t h e same u n p r e d i c t a b l e r e s u l t s on 'the NSSC-11. j
1.2.6 ADDRESSING EXCEPTION
Execution of most i n s t r u c t i o n s r e s i d i n g i n t h e l a s t fullword of memory
w i l l y i e l d u n p r e d i c t a b l e r e s u l t s , u n l e s s memory s i z e i s 6 4 / K b y t e s .
1.2.7 ADDRESSING
A l l effective address computation i s l i m i t e d t o 20 b i t s except f o r t h e LA
(Load Address) i n s t r u c t i o n , which i s 24 b i t s . E f f e c t i v e addresses larger
than 6 5 , 5 3 5 w i l l be t r u n c a t e d t o 20 b i t s (modulo 1 , 0 4 8 , 5 7 5 ) and w i l l n o t
cause an a d d r e s s i n g exception u n l e s s t h e modolo 1 , 0 4 8 , 5 7 5 a d d r e s s exceeds
t h e a v a i l a b l e main memory. I f t h e N S S C - 1 1 has 1 , 9 4 8 , 5 7 5 b y t e s of main
memory, an addressing exception cannot occus.
-2-
SECTION I1
SYSTEM STRUCTURE
2.1 M A I N STORAGE
The NSSC-I1 h a s a maximum c a p a c i t y of one mega--byte; however, t h e c u r r e n t
c a p a c i t y i s 112K-bytes of Simplex memory o r SOK-bytes of F a u l t Tolerant
memory. The programmer should b e aware of t h e s i z e of t h e NSSC-I1 being
programmed. The system t r a n s m i t s inormation between main s t o r a g e and
t h e CPU i n u n i t s of e i g h t b i t s , o r a m u l t i p l e of e i g h t b i t s a t a time.
Each e i g h t b i t u n i t of information i s c a l l e d a b y t e , t h e b a s i c b u i l d i n g
block of a l l formats.
Bytes may b e handled s e p a r a t e l y o r grouped t o g e t h e r i n f i e l d s . A h a l f -
word is a group of two consecutive b y t e s and i s t h e b a s i c b u i l d i n g b l o c k
of i n s t r u c t i o n s . A word i s a group of f o u r consecutive b y t e s ; a double
word i s a f i e l d c o n s i s t i n g of two words (Figure I ) . The l o c a t i o n of any
f i e l d o r . g r o u p of b y t e s i s s p e c i f i e d by t h e address of i t s l e f t m o s t b y t e .
The l e n g t h of f i e l d s i s e i t h e r implied by t h e o p e r a t i o n t o be performed
o r s t a t e d e x p l i c i t l y as p a r t of t h e i n s t r u c t i o n . When t h e l e n g t h i s i m -
p l i e d , t h e information i s s a i d t o have a f i x e d l e n g t h , which can b e
e i t h e r one, two, f o u r , o r e i g h t b y t e s .
When t h e l e n g t h of a f i e l d is n o t implied by t h e o p e r a t i o n code, b u t i s \
s t a t e d e x p l i c i t l y , t h e information i s s a i d t o have v a r i a b l e f i e l d l e n g t h .
This l e n g t h can be v a r i e d i n one-byte increments.
Within any program format o r any f i x e d l e n g t h operand f o r n a t , t h e b i t s
making up t h e format are c o n s e c u t i v e l y numbered from l e f t t o r i g h t
s t a r t i n g w i t h t h e number 0.
Byte
[l 1 0;0 0 0 11
0 7
Hal fword
J K
1 1 01 0 0 0 1 1 101 0 0 1
0 7 E 15
Word
1 0 15 1b I 3 14 J1
I
i j
N S S C I I1
1 1 0 1 0 1 0 1 1 1 1 0 0 0 l 0 l t l 0 0 0 1 0 i i 0 0 0 0 1 1 0 1 1 0 0 0 0 ~ 1 1 0 0 1 0 0 1 1 1 0 0 1 0 0 1 ~ l 0 0 0 0 0 0
Figure 1. Sample Information Formats
-3-
.
2.2 ADDRESSING
, Byte l o c a t i o n s i n s t o r a g e are c o n s e c u t i v e l y numbered s L a r t i n g w i t h 0 ;
each number is considered t h e address of t h e corresponding b y t e . A
3
14
group of b y t e s i n s t o r a g e i s addressed by t h e l e f t m o s t b y t e of t h e
q1
group. The number of b y t e s i n t h e group i s e i t h e r implied o r e x p l i c i t l y
d e f i n e d by t h e o p e r a t i o n . The a d d r e s s i n g arrangement uses a 20 b i t
;
i
binary address. This set of main s t o r a g e addresses i n c l u d e s some
d l o c a t i o n s reserved f o r s p e c i a l purposes.
4
I
S t o r a g e a d d r e s s i n g wraps around from t h e maximum b y t e a d d r e s s
t o address 0. V a r i a b l e l e n g t h operands may be l o c a t e d p a r t i a l l y i n t h e
l a s t and p a r t i a l l y i n t h e f i r s t l o c a t i o n of s t o r a g e , and a r e processed
w i t h o u t any s p e c i a l i n d i c a t i o n of c r o s s i n g t h e maximum a d d r e s s boundary,
e x c e p t , perhaps, s t o r a g e p r o t e c t i o n .
I
When only a p a r t of t h e maximum s t o r a g e c a p a c i t y i s a v a i l a b l e i n a given
i n s t a l l a t i o n , t h e a v a i l a b l e s t o r a g e i s normally contiguously address-
a b l e , s t a r t i n g a t a d d r e s s 0. An a d d r e s s i n g exception i s recognized when
any p a r t of a n operand i s l o c a t e d beyond t h e maximum a v a i l a b l e c a p a c i t y
of an i n s t a l l a t i o n . Except f o r a few i n s t r u c t i o n s , t h e a d d r e s s i n g
e x c e p t i o n i s recogn'ized only when t h e d a t a are a c t u a l l y used and n o t
when t h e o p e r a t i o n is completed b e f o r e using t h e d a t a . The addressing
e x c e p t i o n causes a program i n t e r r u p t i o n .
2.3 INFORNATION PROCESSING !
Fixed l e n g t h f i e l d s , such as halfwords and double words, must be l o c a t e d
i n main s t o r a g e on an i n t e g r a l boundary f o r t h a t u n i t of information.
A boundary i s c a l l e d i n t e g r a l f o r a u n i t of information when i t s
s t o r a g e address i s a m u l t i p l e of t h e l e n g t h of 'the u n i t i n b y t e s . For
example, words ( f o u r b y t e s ) must be l o c a t e d i n s t o r a g e s o t h a t t h e i r
a d d r e s s is a m u l t i p l e of t h e number 4 . A halfword (two b y t e s ) m u s t
have an address t h a t i s a m u l t i p l e of t h e number 2 , and double word
(eight bytes) m u s t have an a d d r e s s that i s a multiple of t h e number 8.
S t o r a g e a d d r e s s e s are expressed i n b i n a r y form. I n b i n a r y , i n t e g r a l
boundaries f o r halfwords, words, and double words can b e s p e c i f i e d
only by t h e b i n a r y addresses i n which one, two, o r t h r e e of t h e low
o r d e r b i t s , r e s p e c t i v e l y , a r e z e r o (Figure 2 ) . For example, t h e
i n t e g r a l boundary f o r a word i s a b i n a r y a d d r e s s i n which t h e two
low o r d e r p o s i t i o n s are z e r o .
C
c:
-4-
, a
1 . .. .~ . . . . . . . . . . . -. ........ ._
V a r i a b l e l e n g t h f i e l d r are n o t l i m i t e d t o i n t e g r a l b o u n d a r i w , and my
o t a r t on any b y t e l o c a t i o n .
.
L
Wad Word Wad
L I
D d l o Wad Daublo W a d
t
Figure 2. Integrr1,Boundrria for Halfwords, Words, and
Doublr Words
2.4 STORAGE PROTECTION
Memory i s p r o t e c t e d ( f o r s t o r i n g only) i n b l o c k s of 1 K = 1024 b y t e r .
There is no f e t c h p r o t e c t i o n . A two b i t p r o t e c t key is a s s o c i a t e d w i t h
each block. The f i r s t b i t on p r o t e c t s t h e block a g a i n s t s t o r e s by t h e
CPU; t h e eecond b i t on p r o t e c t s t h e b l o c k a g a i n s t e t o r e s by Direct
Memory Access (DMA). The key i e set by t h e SSK i n s t r u c t i o n b u t cannot
be r e a d ( r r f e r t o paragraph 8.5.SD SSK, and paragraph 3 . 7 . 3 , DMA).
A i n t e r r u p t w i l l set t h e s t o r a g e p r o t e c t key f o r t h e f i r e t b l o c k
n
to 01, This w i l l allow t h a CPU t o s t o r e in t h r f i r s t b l o c k and pre-
vent DMA from s t o r i n g i n t h a f i r s t block. All o t h e r s t o r a g e p r o t e c t
kayo are u n a l t e r e d by i n t e r r u p t s .
t
SECTION I11
CPU
3.1 CENTRAL PROCESSING UNIT FUNCTIONS
The Central Processing Unit (CPU) (Figuie 3) contains the facilities
for addressing main storage, for fetching or storing information, for
arithmetic and logical processing of data, for sequencing instructions
in the desired order, and for initiating the communication between
storage and external devices.
The system control section provides the normal CPU control that guides
the CPU through the functims necessary to execute the instructions.
Storoge Address
> MAIN STORAGE
A !
r-"-% Instrvctions
I I v \f
I Computer I
I System I Fixed-Point Voriable-
Flo,itiny Point
I Control 1 Operations Ficld-Cength
Operotions Oper,ition
I
I I A A
I I
L,--J
y '
I
1
Figure 3. Basic Concept of Central Processing Unit Functions
. . ..
3.2 REGISTERS
The CPU can a d d r e s s i n f o r m a t i o n i n 1 6 g e n e r a l r e g i s t e r s . The g e n e r a l
r e g i s t e r s can be used as index r e g i s t e r s , i n a d d r e s s a r i t h m e t i c and
i n d e x i n g , and as accumulators i n f i x e d p o i n t a r i t h m e t i c and l o g i c a l
o p e r a t i o n s . The r e g i s t e r s have a c a p a c i t y o f one word (32 b i t s ) . The
g e n e r a l r e g i s t e r s are i d e n t i f i e d by numbers 0-15 and a r e s p e c i f i e d by
i a f o u r b i t R f i e l d i n a n i n s t r u c t i o n . Some i n s t r u c t i o n s p r o v i d e f o r
'.
i a d d r e s s i n g m u l t i p l e g e n e r a l r e g i s t e r s by having s e v e r a l R f i e l d s .
4
t
For some o p e r a t i o n s , two a d j a c e n t g e n e r a l r e g i s t e r s a r e coupled to-
g e t h e r , p r o v i d i n g a two word c a p a c i t y . I n t h e s e o p e r a t i o n s , t h e addressed
r e g i s t e r c o n t a i n s t h e h i g h o r d e r operand b i t s and must have an even
ri- . a d d r e s s ; and t h e implied r e g i s t e r , c o n t a i n i n g t h e low o r d e r operand b i t s ,
f
'3
has t h e n e x t h i g h e r a d d r e s s .
The C P U can address information i n 4 f l o a t i n g p o i n t r e g i s t e r s . The r e g i s -
ters have a c a p a c i t y of one word ( 3 2 b i t s ) . The f l o a t i n g p o i n t r e g i s t e r s
a r e i d e n t i f i e d by the numbers 0-2-4-6 a n d are s p e c i f i e d b y t h e f o u r b i t
K f i e l d i n an i n s t r u c t i o n . The f l o a t i n g p o i n t r e g i s t e r s cannot be used a s
index r e g i s t e r s .
3.3 ARITHPfETIC AED LOGICAL U N I T
The a r i t h m e t i c and l o g i c a l u n i t can p r o c e s s b i n a r y i n t e g e r s of f i x e d
l e n g t h and l o g i c a l i n f o r m a t i o n of e i t h e r f i x e d o r v a r i a b l e l e n g t h .
3.3.1 FIXED POINT ARITHMETIC
The b a s i c a r i t h m e t i c operand i s t h e 32 b i t f i x e d p o i n t b i n a r y word.
S i x t e e n b i t halfword operands may b e s p e c i f i e d i n most: o p e r a t i o n s f o r
improved performance o r s t o r a g e u t i l i z a t i o n ( s e e F i g u r e 4 ) . To pre-.
serve p r e c i s i o n , some p r o d u c t s and a l l dividends are 64 b i t s long.
S Integer -
S. Integer
Figure 4. Fixed-point Number Formats
Because t h e 32 b i t word s i z e r e a d i l y accomqodates a 1 6 - b i t a d d r e s s , f i x e d
p o i n t a r i t h m e t i c can be used both f o r i n t e g e r operand a r i t h m e t i c and
f o r a d d r e s s a r i t h m e t i c . This combined usage p r o v i d e s economy and per-
mits t h e e n t i r e f i x e d p o i n t i n s t r u c t i o n set and s e v e r a l l o g i c a l opera-
i
tions t o b e used i n a d d r e s s computation. Thus, m u l t i p l i c a t i o n , s h i f t i n g , F.
and l o g i c a l manipulation of a d d r e s s components a r e p o s s i b l e . c
-7-
....... - . .._......... .. ._.- . . . . ..--...-
., .- . . ,,,-7 . I.-- -
;
, 7y*-c- c* -4-<*
...... . . . . . . . . ......... . . . . . . .---
-.-- ...
... -.-
MditiOnS, subtractions, multiplications, divisions, and comparisons
are performed upon one operand in a register and another operand either
in a register or from storage. Multiple precision operation is made
convenient by the twos-complement notation and by recognition of the
I
carry from one word to another. A word in one register or a double
word in a pair of adjacent registers may be shifted left or right.
A pair of conversion instructions
DECIMAL --
--
CONVERT TO BINARY and CONVERT TO
provides transition between decimal and binary radix (number
base) without the use of tables. Multiple register loading and storing
instructions facilitate subroutine switching.
3.4 DECIMAL NUMBERS
Decimal numbers are represented by four bit binary coded decimal d i g i t s
packed two to a byte (see Figure 5 . They appear in fields of variable
)
1ength.and are accompanied by a sign in the right-most four bits of the
low order byte. Operand fields may be located on any byte boundary,
. .
Digit Code Sign Code
0 0000 + 1010
1
2
0001
0010
-
+
1011
1100
3
4
0011
0100
-
+
1101
1110
5 0101 '+ 1111
6 0110
7 0111
8 1060
9 1001
Figure 5. Bit Codes for Digits and Signs
and may have a length up to 31 digits and sign. Operands participating
in an operation may have different lengths. Packing of digit8 within
a byte (Figure 6) and of variable length fields within storage results
i n efficient use of storage, in increased arithmetic performance, and in
an improved rate of data tranemission between storage and files.
Highh-ordrr Byto
I.
. ..- Lw-ordsr Byto
... .-.Digit Digit Digit Diol? Sign
Flgun 6. Packed D c I Numkr Format
oim
-8-
Docima1,numberr may a l r o appear i n a zoned format ar a rubrrrt of t h e
e i g h t b i t alphanumeric character e e t (Figure 7 ) . This r e p r e s e n t a t i o n
i r r e q u i r e d f o r character ret e e n s i t i v e 1/0 d e v i c e r . A zoned format n u -
' b a r carrier i t s s i g n i n t h e l e f t - m o r t f o u r b i t e of t h e low o r d e r b y t e *
Figuro 7. Zoned D o c i d Number Format
I n r t r u c t i o n a are provided f o r packing and unpacking decimal numbers
r o t h a t they may b e changed from t h e zoned t o t h e packed format and
vice versa.
3.5 LOGICAL OPERATIONS
L o g i c a l i n f o r m a t i o n is handled ae f i x e d o r v a r i a b l e l e n g t h d a t a . It
i r o u b j e c t t o euch o p e r a t i o n s as comparison, t r a n s l a t i o n , b i t t e s t i n g ,
and b i t r e t t i n g .
When used as a f i x e d l e n g t h operand, l o g i c a l information can c o n e i e t of
e i t h e r one, f o u r , o r e i g h t b y t e s and I8 proceseed in t h e g e n e r a l r e g i s t e r s
(Figure 8).
A l a r g e p o r t i o n of l o g i c a l i n f o r m a t i o n c o n r i e t s of a l p h a b e t i c o r numeric
c h a r a c t e r codes, c a l l e d alphameric d a t a , and ie used f o r communication
w i t h c h a r a c t e r B e t s e n s i t i v e 1/0 d e v i c e s . This information h a s t h e
.
v a r i a b l e - f i e l d - l e n g t h format and can c o n s i e t of up t o 256 b y t e s
(Figure 9 ) It ie proceescd a t o r a g e t o r t o r a g e , l e f t t o r i g h t , an
r i a h t b i t b y t e a t a time.
Fisrd-Lrngth Logical Operand (Onr, Four, or Eight Bytra)
I Logier1 Data
I
Figure 8. f iwd-Length Logical Information
--
Varirblr-Length Logical Operand (Up to 266 Bytea)
- - - - --
Figure 8. Variablr-Length Logical Information
-9-
.
3.6 PROGRAM EXECUTION
The CPU program COnSi6tEJ of instructions, index words, and control
words specifying the operations to be performed. This information
residee in main storage and general registers, and may ba operated
upon ar data.
361
.. INSTRUCTION FORMAT
The length of an instruction format can be one, two, or three halfwords.
It l e related to the rider of storage addresses necessary for the
Operation. An iasbruction consisting of only one halfword causes no
reference to main storage. A two halfword instruction provides one
storage address specification; a three halfword instruction provides
two storage address rpecifications. All instructions must be located
storage on integral boundaries for haY.fwords. .Figure 10 shows five
baric instruction formats.
The five basic Instruction formats are denoted by the format codes RR, r
Bx, m, SI, and SS. The format codes express, in general term, the
operation to be performed. RR denotes a register-to-register operation; i
Rx, a register-and-indexed storage operation; RS , a register-and-rtorage 1
operation; SI, a storage and ipmrediate-operand operation; and SS, a (
I
1
storage-to-storage operation. An immediate operand is one contained I
wlthin the Instruction. I
For purpores of describing the execution of instructions, operands are
designated as first and second operands and, in the case of branch-on-
Index instructions, third operands. These name8 refer to the manner in
which the operands participate. The operand to which a field in an
inrtruction format applies is generally denoted by the number following
the code name of the field, for example, R1, B1, L2, D2.
In each format, the firat inetructlon halfword c o n s i s t s of two parte.
The firrt byte containe the operation code (op code). The length and
f o m t of an instruction are specified by the firet two bits of the
operation code,
3.6.2 ADDRESS GENERATION
For addteesing purposes, operands can be grouped in three claeees:
explicitly addressed operands in main storage; immediate operands placed
u part of the instruction e t r e a in w i n storage; and operands located
i n the general regirters.
-10-
* .
Iw Fornot
RS
1
I
INSTRUCTION LENGTH RECORDING
BIT POSITIONS INSTRUCTION INSTRUCTION
(0.11 LENGTH FORMAT
00 One hrlfword RR
01 Two halfword, RX
10 Two halfword' RS or SI
11 ?reo halfword' 88
NOTE: NSSC-II instructions above the standard System/360 set may
not adhere to this instruction length format convention.
Flguro 10. Fivr Buic lnatrucdon Formats
-11-
To p e r m i t t h e ready r e l o c a t i o n of 2rogram segments and t o p r o v i d e f o r
t h e f l e x i b l e s p e c i f i c a t i o n s of i n p u t , o u t p u t , and working areas, a l l
i n s t r u c t i o n s r e f e r r i n g t o main s t o r a g e have been g i v e n t h e c a p a c i t y
of employing a f u l l a d d r e s s .
The a d d r e s s used t o r e f e r t o main s t o r a g e i s generated from t h e f o l -
lowing t h r e e b i n a r y numbers.
3.6.2.1 Base Address (B)
Base Address (B) i s a 2 0 - b i t number contained i n a g e n e r a l r e g i s t e r
s p e c i f i e d by t h e program i n t h e B f i e l d of t h e i n s t r u c t i o n . The B
f i e l d i s i n c l u d e d i n every a d d r e s s s p e c i f i c a t i o n . The b a s e a d d r e s s can
b e used as a means of s t a t i c r e l o c a t i o n of programs and d a t a . I n a r r a y -
t y p e c a l c u l a t i o n s , i t c a n s p e c i f y t h e l o c a t i o n of a n a r r a y and, i n
record-type p r o c e s s i n g , i t can i d e n t i f y t h e record. The b a s e a d d r e s s
p r o v i d e s f o r a d d r e s s i n g t h e e n t i r e main s t o r a g e . The base a d d r e s s may
a l s o be used for i n d e x i n g purposes.
3.6.2.2 Index (X)
Index (X) is a 20-bit number contained i n a g e n e r a l r e g i s t e r s p e c i f i e d
by t h e program i n t h e X f i e l d of t h e i n s t r u c t i o n . It is i n c l u d e d only
i n t h e a d d r e s s s p e c i f i e d by t h e RX i n s t r u c t i o n format. The RX format
i n s t r u c t i o n s permit double indexing: i . e . , t h e index can b e . u s e d t o
p r o v i d e t h e a d d r e s s of an element w i t h i n an a r r a y .
3.6.2.3 Displacement (D)
Displacerncnt (D) i s . a 12-bit number contained i n t h e i n s t r u c t i o n format
and i s i n c l u d e d i n every a d d r e s s computation. The displacement provides
f o r r e l a t i v e a d d r e s s i n g up t o 4095 b y t e s beyond t h e element o r b a s e
a d d r e s s . I n a r r a y t y p e c a l c u l a t i o n s t h e displacement can be used t o
s p e c i f y one of many i t e n s a s s o c i a t e d w i t h a n element. I n t h e proces-
s i n g of r e c o r d s , t h e displacement can be used t o i d e n t i f y items w i t h i n
a record.
I n forming t h e a d d r e s s , t h e b a s e a d d r e s s and index a r e t r e a t e d as
unsigned 20-bit p o s i t i v e binary i n t e g e r s . The d i S i J l acement i s s i m i l a r l y
t r e a t e d a s a 1 2 - - b i t p o s i t i v e b i n a r y i n t e g e r . The Clirce arc' a d d e d a s
20 b i t b i n a r y numbers, i g n o r i n g overflow. Since every address i n c l u d e s
a b a s e , he s u m i s a l w a y s 20 b i t s long. T h e address b i t s a r e numbered
12-31 corrc:sponding t o t h e numbering o f t h e base address and i n d e x
b i t s i n t h e general r e g i s t e r ,
-12-
...--. , . . . ...
.. .- _.
' .'.
Y.
The program may have z e r o s i n t h e b a s e a d d r e s s , i n d e x , o r displacement
f i e l d s . A z e r o i s used t o i n d i c a t e t h e absence of t h e corresponding
a d d r e s s component. A base o r index of zero i m p l i e s t h a t a z e r o q u a n t i t y
is t o b e used in forming t h e a d d r e s s , r e g a r d l e s s of t h e c o n t e n t s of
g e n e r a l r e g i s t e r 0. A displacement of zero h a s no s p e c i a l signifj-cance.
X n i t i a l i z a t i o n , m o d i f i c a t i o n , and t e s t i n g of b a s e a d d r e s s e s and indexes
can b e c a r r i e d o u t by f i x e d p o i n t i n s t r u c t i o n s , . o r by BRANCH AND L I N K ,
BRANCH ON COUNT, o r BRANCH-ON-INDEX i n s t r u c t i o n s .
A s a n a i d i n d e s c r i b i n g t h e l o g i c of t h e i n s t r u c t i o n format, examples
of two i n s t r u c t i o n s and t h e i r r e l a t e d i n s t r u c t i o n formats f o l l o w .
Add 7 9
Execution of t h e ADD i n s t r u c t i o n adds t h e c o n t e n t s of g e n e r a l r e g i s t e r
9 t o t h e c o n t e n t s of g e n e r a l r e g i s t e r 7 and t h e sum of t h e a d d i t i o n i s
, .! p l a c e d i n g e n e r a l r e g h t e r 7.
R X Format
Store
? 8
3
11 I2
10
I IS 16
14
1920
300 I
11
Execution of t h e s t o r e i n s t r u c t i o n s t o r e s t h e c o n t e n t s of g e n e r a l
r e g i s t e r 3 a t a main s t o r a g e l o c a t i o n addressed by t h e sum of 300 and
t h e low o r d e r 20 b i t s of g e n e r a l r e g i s t e r s 1 4 and 10.
3.6.3 SEQUENTIAL INSTRUCTION EXECUTION
Normally, t h e o p e r a t i o n of t h e CPU is c o n t r o l l e d by i n s t r u c t i o n s taken
i n sequence. An i n s t r u c t i o n i s f e t c h e d from a l o c a t i o n s p e c i f i e d by
t h e i n s t r u c t i o n a d d r e s s i n t h e c u r r e n t PSW. The i n s t r u c t i o n a d d r e s s i s
i n c r e a s e d by t h e number of b y t e s i n t h e i n s t r u c t i o n f e t c h e d t o a d d r e s s
t h e n e x t i n s t r u c t i o n i n se