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5 4 3 2 1
2010.04.07 MV SChematic
D
TABLE OF CONTENTS D
MB
P02 : SYSTEM BLOCK DIAGRAM P24 : Audio (JACK+AMP+SPK+Mute)
P03 : CLOCK MAP P25 : LAN(RTL8103EL)
P04 : POWER DELIVERY CHART P26 : Mini PCIe & RJ11 & BT
P05 : POWER SEQUENCY DIAGRAM P27 : USBX2/USB DB/SATA CONN.
P06 : POWER SEQUENCE CHART P28 : Card Reader
P07 : SMBUS&I2C MAP P29 : HDMI & CRT
P08 : S1G4 HT I/F & PWR P30 : LVDS&Webcam
P09 : S1G4 CTRL & DEBUG P31 : PWR_Charger MAX8731AETI
P10 : S1G4 DDRIII MEMORY I/F P32 : 5V/3.3V SN0608098RHBT
P11 : RS880M-PCIE/HT LINK/SPMEM P33 : Vcore MAX17480
P12 : RS880M-SYSTEM I/F P34 : +V1.1S TPS51117 & VDDR
C C
P13 : RS880M-POWER P35 : +V1.8S RT8253ALGS & VDDA
P14 : SB820M-PCIE/CPU/LPC/STRAP P36 : PWR_Others power plane
P15 : SB820M-GPIO/USB/AZ//SATA P37 : +VCCNB & 1.5VDDR3 +0_75V
P16 : SB820M-POWER & DECOUPLING P38 : ATVDD TPS51217 & +VPCIE
P17 : DDR3(SO-DIMM_0/1) P39 : Stitch CAP
P18 : VGA_S3 (PCI-E) 1/3
Daughter Board
P19 : VGA (IO)/(STRAP) 2/3
P20 : VGA_S3 (POWER) 3/3 P40 -- Power Board / USB Board / SW Board
P21 : VRAM (DDR3)
P22 : EC+KBC (IT8502E) & ROM
P23 : Audio (CODEC_ALC270A)
B B
P. Leader Check by Design by
A A
Hon Hai Precision Industry Co. Ltd.
Foxconn eMS Inc.
HNBD R&D phone: +886-2-2799-6111
Title
TABLE OF CONTENTS
Size Document Number Rev
Custom Safina MV
Page Modified: Wednesday, April 07, 2010 19:11:12 (UTC/GMT) Sheet 1 of 39
5 4 3 2 1
1 2 3 4 5 6 7 8
VRAMx4
64Mx16 GPU SO-DIMM 0
DDR3 ATI PCIe X16 800/1066/1333 MHZ 800/1066/1333 MHZ
P21 Park XT DDR(III)
64bit P17
A AMD A
P18-20
Discrete GPU Option P29 S1G4 800/1066/1333 MHZ
SO-DIMM 1
800/1066/1333 MHZ
DDR(III)
HDMI
HDMI P17
Conn. P8-10
P29
LVDS LAN Transformer
LVDS
RealTek DELTA RJ45
Conn. HT
P30 RTL8103EL (10/100) LFE8456A-R
P25
CRT Buffer
CRT PCIe
Conn. Level Shifter
P29 ESD P29
North Bridge Option
B
RS880M DDR3 B
Side Port BlueTooth Module
PCIe
P11-13 P26
Int. Speaker x2 CODEC 128MB
P24 HDA
RealTek
Option Analog Mic x1 ALC270A-GR P11 Card Reader 5-IN-1
P23
WLAN or WLAN+BT With Pre-Amp P23 A-Link RealTek Combo
Half Size Mini-Card USB2.0 RTS5159 P28 Connector
Ext. Mic In Jack P24
Option
Headphone Jack P24
USB2.0 HDA
USB 2.0 (2 amp) x2 South Bridge MDC Modem RJ11
P26
USB 2.0 (2 amp) x1 P27 SB820M
P27 SATA : HDD P27
Option
Int CLK Gen
SATA
P14-16
VGA Webcam (F2.8 lens)
Seti 100B; SATA : ODD P27
OmniVision OV7670; LPC
C
Micron MI-366; P30 C
KBMX Keyboard
FAN PWM P22
P8 Embedded
Battery Pack System PS/2 Touch PAD
Lid Controller P22
P31 Switch P40 GPIO
Power ITE IT8502E SMBus CPU Thermal Sensor
Adapter Charger Button P40 GMT G786P81U
19V MAX8731AETI P9
P31
P31 KBC ROM SPI
2MB P27 GPU Thermal Sensor
P27 SMBus
GMT G781_1
D D
P20
Hon Hai Precision Industry Co. Ltd.
Foxconn eMS Inc.
HNBD R&D phone: +886-2-2799-6111
Title
SYSTEM BLOCK DIAGRAM
Size Document Number Rev
Custom Safina MV
Page Modified: Wednesday, April 07, 2010 18:49:16 (UTC/GMT) Sheet 2 of 39
1 2 3 4 5 6 7 8
5 4 3 2 1
D
INTERNAL CLOCK MODE D
SDDR_A_CLK_DDR0
SDDR_A_CLK_DDR#0
SDDR_A_CLK_DDR1
SDDR_A_CLK_DDR#1
A_SODIMM
800/1066/1333MHZ
SPM_CLKP SIDE PORT
SPM_CLKN MEMORY CHIP
SDDR_B_CLK_DDR0
SDDR_B_CLK_DDR#0 AMD 400MHZ
A-LINK
SDDR_B_CLK_DDR1
SDDR_B_CLK_DDR#1 RS880M
B_SODIMM
800/1066/1333MHZ
SIG4 CPU REFCLKP/N GPP_REFCLK
CLK_NB_REF#_R
CLK_HT_REF#_R
CLK_NBLINK#_R
CLK_NB_REF_R
CLK_HT_REF_R
CLK_NBLINK_R
CLK_CPU#_R
CLK_CPU_R
100MHZ
100MHZ
100MHZ
200MHZ
C C
NB_DISP_CLKP/N
NB_HT_CLKP/N
PCIE_RCLKP/N
CPU_HT_CLKP/N
PCI_CLK1
STRAPS PCICLK1
Stopped CLK
SETTING, Park_XT or M93_XT
PCI_CLK2
UNUSED PCICLK2
Stopped CLK
CLOCKS PCI_CLK3
PCICLK3 CLK_PEG_REF_R
Stopped CLK CLK_PEG_REF#_R
PCI_CLK4 SLT_GFX_CLKP/N
PCICLK4 100MHZ
Stopped CLK
CLK_REQG# in SB
CLK_PCI_KBC LPCCLK0
KBC
33MHZ
B B
AMD SB820M CLK_PCIE_MINI_R
WLAN
CLK_PCIE_MINI#_R
HD AUDIO
HDA_BITCLK AZ_BITCLK CLOCK GENERATOR GPP_CLK1P/N
24MHZ 100MHZ
HD MDC
CLK_REQ1 in SB
CLK_PCIE_LAN_R
CLK_PCIE_LAN#_R LAN
CLK_48M_CARD_R GPP_CLK3P/N
Card Reader 14M_25M_48M_OSC 100MHZ
48MHZ CLK_REQ3 in SB
FOR MASTER FOR RTC FOR SATA
25M Hz 32.768K Hz 25M Hz DNI
A A
Hon Hai Precision Industry Co. Ltd.
Foxconn eMS Inc.
HNBD R&D phone: +886-2-2799-6111
Title
CLOCK MAP
Size Document Number Rev
Custom Safina MV
Page Modified: Wednesday, April 07, 2010 18:49:17 (UTC/GMT) Sheet 3 of 39
5 4 3 2 1
5 4 3 2 1
+V5A +V5A/7A/5.6A
in S0~S5
+VBAT
Adaptor
19.5V +V5A +V5S/4A/4A
in S0~S1
TI SN0608098 SI7716ADN-T1-GE3
90W/65W RUN_ON_LOAD
+V5A/+V3.3AL +V3.3AL +V3.3AL/6A/4.8A in S0~S5
For System Power
+V3.3A/6A/4.8A
+V3.3AL +V1.1A/600mA/600mA
APL5930
SI7716ADN-T1-GE3 in S0~S5
+V3.3A
3.3A/4.7A
D D
EC_ALW_EN EC_ALW_EN
EN1(+V5A) +V5AL
+V3.3A +V3.3S/4A/4A in S0~S1
+V5AL EN2(+V3.3AL) SI7716ADN-T1-GE3
VDDA_CPU/600mA/600mA
RUN_ON_LOAD APL5930
+V3.3S
+V3.3A_RTC ENLDO(5V LDO)
+V3.3S_DELAY/0.5A/0.5A
in S0~S1
SI7716ADN-T1-GE3
PWR_Charger
ACPRES CHARGE BUMP +V12A +V12S
Battery Charger in S0~S1
FDN340P_NL For system power enable.
Switch Mode SLP_S3#_3R
ADAPT_OC_IINP
MAX8731AETI
TI +V1.1A/10A/8A in S0~S5
ENDCHG
TPS51117
For +V1.1S
VRM&V1.8S_PWRGD
EN PGOOD +V1.1S/10A/8A +VLDT/4A/3.2A in S0~S1
PAD
+VLDT/4A/3.2A
C
MPS NB634 +V1.8S/3A/2.4A C
in S0~S1
BT+
For +V1.8S
SLP_S3#_3R V1.8S_PWRGD
EN PGOOD
+V1.8S_GPU
in S0~S1
SI7716ADN-T1-GE3
+VCC_CORE/38A/30A in S0~S1
MAXIM
MAX17480 in S0~S1
Battery Pack +VDDNB_CPU/4A/4A
FOR +VCC_CORE
3S2P/3S3P
VDDA_PWRGD PWRGD
SHDN# VRM_PWRGD
47/55/62/93W
+VDDR_NB/2A/2A in S0~S1
MPS NB634
For +VDDR_NB PGOOD
VDDA_PWRGD EN
+V1.5/10A/8A in S0~S3
B B
TI
TPS51117RGYRG4 +V1.5 +V1.5S/5A/4A +VPCIE/2.5A/2A in S0~S1
APL5930
SLP_S3#_3R For +V1.5 DDR3
S3
SI7716ADN-T1-GE3 1.1V 1.0V
+V1.8S_PWRGD
SLP_S5#_3R G2997F6U SLP_S3#_3R
S5
For +V0.75S
+V1.5S_GPU in S0~S1
SI7716ADN-T1-GE3
+V0.75S/1A/1A
in S0~S1
TI
TPS51217DSCR
For +VCCNB +VCC_NB/10A/8A in S0~S1
VRM_PWRGD
TI
TPS51217DSCR
A For +VDD_CORE +VDD_CORE/10A/8A in S0~S1 A
Hon Hai Precision Industry Co. Ltd.
Foxconn eMS Inc.
Switching HNBD R&D phone: +886-2-2799-6111
Linear Power Rail Control signal
Title
POWER DELIVERY CHART
Size Document Number Rev
Custom Safina MV
Page Modified: Wednesday, April 07, 2010 18:49:16 (UTC/GMT) Sheet 4 of 39
5 4 3 2 1
5 4 3 2 1
D D
+V3.3AL +V3.3A +V1.1A
2 +1.1VEN
SWITCH
PQ31 APL5930
+V3.3AL
+V5A
EC SN0608098RHBT
1
ITE8502 EC_ALW_EN
EC_PWRBTN# 3
+V1.5
SLP_S5#
4 TPS51117
C
SB820M 4 & G2997F6U +V0.75S
C
SLP_S3#
+V1.8S
4 4
NB634
+V5A +V5S PWRGD V1.8S_PWRGD
SWITCH
SLP_S3# PQ42 6
CPU_VDDA_RUN
+V3.3A +V3.3S
5 APL5930 +VCC_CORE +V1.5 +V1.5S
PQ39 LDO VDDA_PWRGD
7 8
EN MAX 17480
+VDDNB_CPU SWITCH
PWRGD
8 PQ17
Power on Sequence required:
SB820M: VRM_PWRGD
1, +V3.3A ramp before +V1.1A +VDDR_CPU
2, +V3.3S ramp before +V1.8S 8 +V1.1S
3, +V1.8S ramp before +V1.1S NB634
B 4, +V3.3S ramp before +V1.1S B
TPS51117 VLDT
RS880M: 9 VRM_PWRGD
1, 0 <(+V3.3S) - (+V1.8S) < 2.1
2, +V1.8S ramp before +V1.1S
3. +V1.1S ramp before VCC_NB VCC_NB
9 VRM_PWRGD
TPS51217
A A
Hon Hai Precision Industry Co. Ltd.
Foxconn eMS Inc.
HNBD R&D phone: +886-2-2799-6111
Title
POWER SEQUENCY DIAGRAM
Size Document Number Rev
Custom Safina MV
Page Modified: Wednesday, April 07, 2010 18:49:16 (UTC/GMT) Sheet 5 of 39
5 4 3 2 1
5 4 3 2 1
LDT_RST#
(SB to CPU)
LDT_PG
(SB to CPU) >1 mS Req.
CPU_CLKP/N running
D D
>1 mS Req.
running
>1 mS Req. VCC_NB(all NB power) valid before NB_PWRGD.
NB_PWRGD
(SB to NB)
SLP_S3#_3R V1.1A_PWRGD
SB_PWRGD V1.8S_PWRGD VRM_PWRGD
(VRM_PWRGD to SB)
0.95V - 1.1V RC=~22ms VCC_NB should not ramp before +V1.1S
+VCC_NB
1.1V
+VLDT
GROUP B
VRM_PWRGD AND V1.8S_PWRGD
+V1.1S
VRM_PWRGD
(from +VCC_CORE IC)
0.9V(DDR3-1066) 1.05V(DDR3-1333) RC=0
+VDDR_CPU
0.8V - 1.1V RC=0
+VCC_CORE
0.9V RC=0
+VDDNB_CPU
C C
VDDA_PWRGD
GROUP A
2.5V
+VDDA_CPU
V1.8S_PWRGD
RC=0
+V1.8S
+V5S/+V3.3S
+V12S
to S3
SLP_S3#_3R (SB to EC)
CPU MEM CTL &
DDR3 SODIMM PWRS +V0.75S +V0.75S only will be shut down in S3 mode
M_VREF
+V1.5
SLP_S5#_3R (SB to EC)
B B
Power button from EC to SB
EC_PWRBTN#
CPU_THM/SB/SB_SCL1/2 20mS
delay
SB_KB/SPI/LPC ROM PWRS RSMRST# (EC to SB)
+V12A/+V5A/+V3.3A/+V1.1A
ALW RAILS When IMC, always on at all time( always PWR)
EC_ALW_EN (from EC)
Power button pressed
PWR_SWIN#
KBC is ready
AC not present scenario = LOW AC present= high
ACPRES
(ACIN detect)
KBC is powered by
+V3.3AL +V5AL/+V3.3AL
M31ALDO
(from DCIN)
Battery inserted/AC IN
Power on Sequence required: +VBAT
SB820: +VCC_RTC
A A
1, +V3.3A ramp before +V1.1A
2, +V3.3S ramp before +V1.8S
3, +V1.8S ramp before +V1.1S
5, +V3.3A ramping down time > 300us
6, 50uS <= All power rails except +V3.3A <= 40mS
Hon Hai Precision Industry Co. Ltd.
7, 100uS <= +V3.3A <= 40mS
Foxconn eMS Inc.
HNBD R&D phone: +886-2-2799-6111
RS880M:
1, 0 <(+V3.3S) - (+V1.8S) < 2.1 Title
2, +V1.8S ramp before +V1.1S