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5 4 3 2 1
BOM Option Table
HM55_CP (ZRD) SYSTEM BLOCK DIAGRAM
Reference Description
IV@ for UMA only SKU
SW@ for Switchable Graphic only SKU AMD GPU 64Mb x 16 IO x 4 pcs
Arrandale Channel A 64Mb x 16 IO x 8 pcs
D
Robson_XT & D
rPGA 989 Park_XT Channel B 128Mb x 16 IO x 8 pcs
( 512M ) P19, 20
Dual Channel DDR III P4, 5, 6, 7 PCI-E x16 EXT_HDMI
DDRIII-SODIMM1 Capilano-Pro &
800/1066 MHZ IMC GFX Madison-Pro
DDRIII-SODIMM2 EXT_CRT
P14,15 ( 1G or 2G ) CRT Con.
EXT_LVDS P24
P16, 17, 18, 21, 22, 23
FDI DMI
X'TAL CK505 DMI(x4)
14.318MHz CLOCK USB-8
LVDS/CCD/MIC
INT_CRT
GENERATOR P3 FDI DMI Con.
INT_LVDS Int. MIC P24
CLK
Display
SATA 0
SATA - HDD
C C
P29
SATA
HDMI Con.
SATA - ODD SATA 1 INT_HDMI TI SN75DP139
P29 LS P25
P25
PCIE-6
PCI-E x1
USB Port USB-1 MINI CARD
USB Ibex Peak-M USB-13
P34 WLAN
P28
USB-9/11 PCH
USB/B Con. P34 P8, 9, 10, 11, 12, 13
(USB Port x2) PCIE-1 BRM 57780
RJ45
USB-4
GIGA LAN P26
Bluetooth Con. X'TAL P27
32.768KHz
P34
X'TAL
B 25MHz B
Cardreader AU6437-GBL USB-12 X'TAL 25MHz
P32
Cardreader control
P32
P8 BATTERY RTC
Azalia SPI SPI ROM
IHDA ISL88731A UP6111AQDD ISL62881HRZ-T
P8
LPC Batery Charger P38 +1.05V P42 +VGFX_AXG P46
LPC RT8206B RT8207A TPS54418RTE x2
3V/5V P39 +1.5V_SUS P43 +1.8V/+1V P47
Int. MIC ALC272X NPCE781 X'TAL
AUDIO CODEC P30 EC P37 32.768KHz ISL62882 MAX8792ETD+T Discharger
CPU core P40 +VGPU_CORE P44 P47
A
UP6111AQDD ISL62872 Thermal Protection A
GMT +1.1V_VTT P41 +VGPU_IO P45 P48
MIC JACK Power SW/B Touch Pad
G1442P81U Board Con. Board Con.
P31
AMP P35 P33 P33 P35
Quanta Computer Inc.
W25X16VSS1G EM-6781-T3 Fan Driver PROJECT : ZRD
HP JACK Speaker K/B Con. HALL SENSOR (PWM Type) Size Document Number Rev
P31 P31 P35
SPI FLASH P37 P24 P35 1C
Block Diagram
Date: Wednesday, July 21, 2010 Sheet 1 of 46
5 4 3 2 1
1 2 3 4 5 6 7 8
GPU PWR CTRL Option 1 (Default/ VDDR3 before VDDC)
+3.3V VIN VIN +1.5V +1.5V_SUS +1.8V +5V
VDDR3 +3V_D VDDC PG_GPUIO_EN VDDCI PG_1V_EN +1V (DP PLL PWR) PG_1.5V_EN VDDR1 PG_1.5V_EN VDDR4 PG_1.5V_EN BJT dGPU_PWROK MOS
dGPU_VRON dGPU_PWR_EN#
MOS (AO3413) ISL6264 ISL62872 G9334ADJ & MOS MOS (AO4710) MOS (AO6402) AO3413
P22 P44 P45 P47 P43 P43 P22 P22
A +3_D (0.5A) +VGPU_CORE (20A) +VGPU_IO (4.5A) +1V (3A) +1.5V_GPU (10A) +1.8V_GPU (3A) +5_GPU A
GPU PWR CTRL Option 2 (VDDR3 after VDDR1)
VIN VIN +1.5V +1.5V_SUS +3.3V +1.8V +5V
VDDC PG_GPUIO_EN VDDCI PG_1V_EN +1V (DP PLL PWR) PG_1.5V_EN VDDR1 +1.5V_GPU VDDR3 +3V_D VDDR4 PG_1.5V_EN BJT dGPU_PWROK MOS
dGPU_VRON dGPU_PWR_EN#
ISL6264 ISL62872 G9334ADJ & MOS MOS (AO4710) MOS (AO3413) MOS (AO6402) AO3413
P44 P45 P47 P43 P22 P43 P22 P22
+VGPU_CORE (20A) +VGPU_IO (4.5A) +1V (3A) +1.5V_GPU (10A) +3_D (0.5A) +1.8V_GPU (3A) +5_GPU
Thermal Follow Chart
Power States
CONTROL
POWER PLANE VOLTAGE DESCRIPTION ACTIVE IN
SIGNAL
B VIN +10V~+19V MAIN POWER ALWAYS ALWAYS B
+VCCRTC +3V~+3.3V RTC POWER ALWAYS ALWAYS NTC
Thermal
+3VPCU +3.3V EC POWER ALWAYS ALWAYS
Protection
+5VPCU +5V CHARGE POWER ALWAYS ALWAYS
+15V +15V CHARGE PUMP POWER ALWAYS ALWAYS
+3V_S5 +3.3V LAN/BT/CIR POWER S5_ON S0-S5 CPU 3V/5 V
H_ORICHOT# PM_THRMTRIP# SYS_SHDN#
CORE PWR
CPU WIRE-AND SYS PWR
+5V_S5 +5V USB POWER S5_ON S0-S5 H/W Throttling
+5V +5V HDD/ODD/Codec/TP/CRT/HDMI POWER MAINON S0
+3V +3.3V PCH/GPU/Peripheral component POWER MAINON S0
SML1ALERT#
+1.5VSUS +1.5V CPU/SODIMM CORE POWER SUSON S0-S3
PCH FAN Driver FAN
+0.75V_DDR_VTT +0.75V SODIMM Termination POWER MAINON S0
+VGFX_AXG variation Internal GPU POWER GFX_ON S0
SM-Bus
+1.8V +1.8V CPU/PCH/Braidwood POWER MAINON S0
C C
+1.5V +1.5V MINI CARD/NEW CARD POWER MAINON S0
EC
+1.1V_VTT +1.05V or +1.1V CPU VTT POWER MAINON S0 CPUFAN#
+1.05V +1.05V PCH CORE POWER MAINON S0
+VCC_CORE variation CPU CORE POWER VRON S0
LCDVCC +3.3V LCD POWER LVDS_VDDEN S0
+5V_GPU +5V SWITCHABLE PWM IC POWER dGPU_PWR_EN# Discrete enable
+GPU_CORE +0.9V~+1.1V GPU CORE POWER +3V_D Discrete enable
+GPU_IO +0.9V~+1.1V GPU I/O POWER PG_GPUIO_EN Discrete enable
+1.5V_GPU +1.5V VRAM CORE POWER PG_1.5V_EN Discrete enable
+1.8V_GPU +1.8V GPU_CRE/LVDS/PLL POWER +1.5V_GPU Discrete enable
+1V +1V DP/PEG POWER PG_1V_EN Discrete enable
D D
Quanta Computer Inc.
PROJECT : ZRD
Size Document Number Rev
1C
PWR Status & GPU PWR CRL & THRM
Date: Wednesday, July 21, 2010 Sheet 2 of 46
1 2 3 4 5 6 7 8
5 4 3 2 1
6/21 add R586 for 3V CLK gen
D
Un-stuff L54 D
U31 Change P/N
150mA(30mil)
+1.5V L54 *PBY160808T-181Y-N/2A/180ohm_6 +1.5V_CLK 80mA(20mil)
+VDDIO_CLK L53 PBY160808T/2A/180ohm_6 +1.05V
C434 C740 C437
C734 C435 C731 C732
.1u/16V_4 .1u/16V_4 .1u/16V_4
.1u/16V_4 .1u/16V_4 10u/Y5V_8 10u/Y5V_8
R586 U31
0_6 Place each 0.1uF cap as close as
1 VDD_DOT possible to each VDD IO pin. Place
17 VDD_SRC VDD_SRC_I/O 15 the 10uF caps on the VDD_IO plane.
24 VDD_CPU VDD_CPU_I/O 18
20mil 5 VDD_27
+3V L29 BLM18AG601SN1D/200mA/600ohm_6 +3V_CLK 29 3
VDD_REF DOT_96 CLK_BUF_DREFCLK [10]
DOT_96# 4 CLK_BUF_DREFCLK# [10]
CLK_SDATA 31
C432 C464 C442 CLK_SCLK SDA R561 *33_4
32 SCL 27M 6 27M_CLK [17]
7 R562 *33_4 27M_CLK_SS [17]
4.7u/10V_8 .1u/16V_4 .1u/16V_4 27M_SS C467 *10p/50V_4
R564 33_4 CPU_SEL 30 10
[10] CLK_ICH_14M REF_0/CPU_SEL SRC_1/SATA CLK_BUF_DREFSSCLK [10]
SRC_1#/SATA# 11 CLK_BUF_DREFSSCLK# [10]
C735 33p/50V_4 13 REV: B Switch CLK_BUF_DREFSSCLK and
SRC_2 CLK_BUF_PCIE_3GPLL [10]
C SRC_2# 14 CLK_BUF_PCIE_3GPLL# [10] CLK_BUF_PCIE_3GPLL C
XTAL_IN 28
Y6 XTAL_IN +3V
14.318MHz XTAL_OUT 27 16 R287 10K_4
XTAL_OUT *CPU_STOP#
C733 33p/50V_4 2 20
VSS_DOT CPU_1 TP19
8 VSS_27 CPU_1# 19 TP20
9 VSS_SATA CPU_0 23 CLK_BUF_BCLK [10]
12 VSS_SRC CPU_0# 22 CLK_BUF_BCLK# [10]
21 VSS_CPU
IDT: AL003197000 (ICS9LRS3197AKLFT) 26 25 CK_PWRGD_R REALTEK AL000890000
VSS_REF CKPWRGD/PD#
33
Realtek: AL000875002 (RTM875N-632-VB-GRT) GND
Silego: AL8SP585000 (SLG8SP585VTR) SLG AL000595000
SLG8LV585V
+3V
CPU_CLK select SMBus
B
+1.05V
CLK Enable +3V B
R555
R558
2
R560 2.2K_4 1K/F_4
*10K_4
3 1 CLK_SDATA CLK_SDATA [14,15,28]
[10] ICH_SMBDATA
CK_PWRGD_R
CPU_SEL Q20
3
2N7002K Q21
2N7002K
R559 C737
+3V [39] VR_PWRGD_CK505# 2 R556
10K_4 *10p/50V/COG_4 100K/F_4
1
R554
2
2.2K_4
0 1
3 1 CLK_SCLK CLK_SCLK [14,15,28]
[10] ICH_SMBCLK
A CPU_SEL CPU0/1=133MHz CPU0/1=100MHz Q19 A
(default) 2N7002K
Quanta Computer Inc.
PROJECT : ZRD
Size Document Number Rev
1C
Clock Generator
Date: Wednesday, July 21, 2010 Sheet 3 of 46
5 4 3 2 1
5 4 3 2 1
AUBURNDALE/CLARKSFIELD PROCESSOR (DMI,PEG,FDI) AUBURNDALE/CLARKSFIELD PROCESSOR (CLK,MISC,JTAG)
DPLL_REF_SSCLK and DPLL_REF_SSCLK# can be connected to GND on Arrandale
directly if motherboard only supports discrete graphics. If motherboard supports
Processor Compensation Signals integrated graphics but without eDP, these pins can also be connected to GND directly.
U24A U24B
B26 R424 49.9/F_4 R439 20/F_4 H_COMP3 AT23
PEG_ICOMPI COMP3
PEG_ICOMPO A26 BCLK A16 CLK_CPU_BCLK [11]
MISC
MISC
A24 B27 R435 20/F_4 H_COMP2 AT24 B16 CLK_CPU_BCLK# [11]
[8] DMI_TXN0 DMI_RX#[0] PEG_RCOMPO COMP2 BCLK#
C23 A25 R426 750/F_4
[8] DMI_TXN1 DMI_RX#[1] PEG_RBIAS
CLOCKS
B22 PEG_RXN[0..15] [16] R131 49.9/F_4 H_COMP1 G16 AR30 T57
[8] DMI_TXN2 DMI_RX#[2] COMP1 BCLK_ITP
A21 K35 PEG_RXN0 AT30 T58 Layout Note: Place
D [8] DMI_TXN3 DMI_RX#[3] PEG_RX#[0] BCLK_ITP# D
J34 PEG_RXN1 R432 49.9/F_4 H_COMP0 AT26
B24
PEG_RX#[1]
J33 PEG_RXN2 COMP0
E16
these resistors
[8] DMI_TXP0 DMI_RX[0] PEG_RX#[2] PEG_CLK CLK_PCIE_3GPLL [10]
[8] DMI_TXP1 D23 DMI_RX[1] PEG_RX#[3] G35 PEG_RXN3
PEG_CLK# D16 CLK_PCIE_3GPLL# [10]
near Processor
DMI
DMI
B23 G32 PEG_RXN4 T14 AH24
[8] DMI_TXP2 DMI_RX[2] PEG_RX#[4] SKTOCC#
A22 F34 PEG_RXN5 A18 DPLL_REF_SSCLK_R R453 *0_4 DPLL_REF_SSCLK [10]
[8] DMI_TXP3 DMI_RX[3] PEG_RX#[5] DPLL_REF_SSCLK
F31 PEG_RXN6 A17 DPLL_REF_SSCLK#_R R457 *0_4 DPLL_REF_SSCLK# [10]
PEG_RX#[6] PEG_RXN7 H_CATERR# DPLL_REF_SSCLK# R458 *Short_4
D24 D35 AK14
[8] DMI_RXN0 DMI_TX#[0] PEG_RX#[7] Use reverse type CATERR#
THERMAL
THERMAL
G24 E33 PEG_RXN8 R452 *Short_4
[8] DMI_RXN1 DMI_TX#[1] PEG_RX#[8]
F23 C33 PEG_RXN9 REV : B R458 & R452
[8]
[8]
DMI_RXN2
DMI_RXN3 H23
DMI_TX#[2]
DMI_TX#[3]
PEG_RX#[9]
PEG_RX#[10] D32 PEG_RXN10
PEG_RXN11
(at GPU side) SM_DRAMRST# F6 DDR3_DRAMRST# [14,15] Change to short pad
PEG_RX#[11] B32 [11] H_PECI AT15 PECI