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27114A EXTERNAL REFERENCE SPECIFICATION
A-2711~-90011-1 Rev A
CONTENTS
1. SCOPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
2. GENERAL .................................................... 2-1
2.1 Description .............. , ........................... 2-1
2.2 Fnvironment .......................................... 2-1
2.3 Installation ......................................... 2-1
3. FRONTPLANE FUNCTIONAL DESCRIPTION ......................... 3-1
3.1 Physical Characteristics of Frontplane Signals ...... 3-1
3.1.1 Cable - differential version ................. 3-1
3.1.2 Cable (single-ended version): ................ 3-1
3.1.3 Drivers and Receivers ........................ 3-2
3.1.~ Bi-directional bus ........................... 3-2
3.2 Signal Definitions .................................. 3-3
3.3 pin out ............................................. 3-5
3.~ Logic sense on frontplane interface ................ 3-18
3 . 5 Da t a Tr an s fer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 -18
3.6 Frontplane Timing .................................. 3-21
3.7 Back-to-Back 2711~ Link ............................ 3-2~
3.7.2 Back-to-Back Data Transfer .................. 3-25
~. BACKPLANE CONTROL DESCRIPTION ............................. ~-1
~.1 Register Definitions ................................ ~-1
~.1.1 Register descriptions: ....................... ~-3
~.1.2 Card Identification .......................... ~-8
~.2 Data path pipeline .................................. ~-8
~.2.1 FIFO and external latches .................... ~-9
~.2.2 State machine ................................ ~-9
~.2.3 SRQ poll response and burst request ......... ~-10
~.2.~ Backplane data handshaking .................. ~-10
~.2.5 Frontplane data handshaking ................. ~-11
~.3 Data Path Loopback ................................. ~-11
~.3.1 Loopback without test hood .................. ~-12
~.3.2 Loopback with test hood ..................... ~-12
~ .~ Interrupts ......................................... ~-1~
~.5 Output to a Peripheral ............................. ~-1~
~.6 Data input from a Peripheral ....................... ~-16
~.7 Dealing with the Data Path Pipeline ................ ~-16
~.8 27114 to 2711~ Connections - Software .............. ~-18
5. PERFORMANCE ISSUES ........................................ 5-1
5.1 Fundamental Limits to Performance ................... 5-1
5.2 Frontplane Limits to Performance .................... 5-2
5.2.1 Cable Length ............... ~ ......... -........ 5-3
5.3 Backplane Performance ............................... 5-4
5.3.1 Data Bursting ................................ 5-4
5.3.1.1 Burst Hardware Variation .............. 5-5
5.3.2 Interaction Between Backplane and Frontplane.5-5
5.4 27114 to 27114 Performance .......................... 5-6
6. PRELIMINARY PROGRAMMING INFORMATION ....................... 6-1
2.1 Description .......................................... 6-1
2.2 Installation ......................................... 6-1
2.3 Driver features ........................................... 6-1
UPDATE HISTORY
Dec 12, 1985
* The correct derinition for backplane interrace registers is
given (in term of BPO, BP1, CBYT and CEND).
* Frontplane pin AI0 now is a safety ground pin and pin BI0 is
the test hood presence pin.
Feb 12, 1986
* Cable offering (single-ended: high and low true)/dirferential.
* General clean up of documentation
Apr 9, 1986
* Extra information on group 0 polling
* Information about series 550 is removed
* More information on grounding and RFI performance
June 26, 1986
* General clean up
Nov 7, 1986
* General clean up
* Clarify data handshake
Jan l.ij, 1986
* General clean up
27114 ERS, Nov 7, 1986
1. SCOPE
This External Reference Specification provides all the
information required to instal~ and operate the AFI (Asynchronous
FIFO Interface) card. It details the pin out and function of the
frontplane interface as well as the backplane interface in terms
of register descriptions.
The intention of this document is to provide sufficient
information such that drivers can be written for high level
language users. This document does not provide full information
on how the card operates internally or how programming is done at
the user level. The 27114 IRS provides information on how the
card operates internally. For user programming information,
please refer to the appropriate driver's ERS.
Eventhough any well written ERS could provide enough information
to guide how to use the described product, it is believed that
the AFI card belongs to an exception group. This ERS alone
probably would be sufficient to provide enough information for
most intended use but wise users should also be intimately
familiar with the hardware via the IRS and specially, the
schematics, the granddaddy of all electrical documents.
It should be noted here that this is not an ERS for the AFI
product but only an ERS for the AFI hardware. Attempt to
interpret this otherwise could mislead to other confusion. A
good example is the parity feature of the AFI card. While there
are hardware circuits available on the AFI assembly to support
the parity feature, the host channel adapter and device adapter
driver/operating systems must also support it to claim that AFI
product has the parity feature. The ERS for AFI product should
be written after close examination of ERS's for both hardware and
software produtcts to see how and what kind of interactions could
be expected.
As of this release, most of the performance testing has been done
to verify that AFI actually could go as high as 5 Mbytes per sec
for cables of length 3 to 12 m long. This figure may also be
misleading if not carefully interpret ted by the product ERS
writer since other system factors could greatly affect it.
Throughout this document, temporary NOTEs will be used. to
describe unresolved issues as of the latest revision date.
Please consult RND' R&D for latest information on those subjects.
1-1
2711~ ERS, Nov 7, 1986
2. GENERAL
2.1 Description
The 27114 card is an extended level 1 CIO card intended for fast
parallel data transfer t~tween CIa channel and an external
peripheral. It interfaces to user's equipment via a 16 data bit
parallel bus. Two additional parity bits are also provided for
suitable future application.
NOTE:
The 8 bit mode can be achieved by having the byte
packing/unpacking done by the CIO channel adapter.
This bus can be configured either as differential or single-ended
(separate in/out only). Pulsed asynchronous handshake is
provided. The 27114A card can be used in any Spectrum host with
CIa channel adapter.
The 27114 is used as a dedicated interface to a single peripheral
device. It is not and cannot be made to be compatible to either
HPIB, SCSI or IPI. The 2711~ is designed to be compatible to
most other HP's parallel cards.
2.2 Environment
POWER CONSUMPTION:
The 27114A card consumes about 2 A at +5 volts. The 2 sigma
value is about 2.25 A.
FUSE:
The 27114A is shipped with a built-in fuse printed circuit trace.
Under abnormal condit jon, this trace will burn out to protect the
main power supply. After the abnormal cause is removed, part
number 2110-0712 fuse (4 A) should be used to replace the
built-in fuse. This part is available directly from CPC.
OPERATING ENVIRONMENT:
The 27114 is intended to be operated over the Hewlett-Packard
CLASS B environmental specifications.
2.3 Installation
The 27114A card is a regular mode card as far as power
consumption is concerned. It draws typically about 10 watts
compared to the normal 12 watt allowance for regular CIa cards.
The installation of this card in any CIa card cage does not
require budgeting of power supply resource.
2-1
2711~ ERS, Nov 7~ 1986
Since the AFI responds to polling via its UAD line and its
channel address is the same as the slot address, it can be
guaranteed to function correctly in group 0 slots only. Note
that other level 2 CIO cards have a programmable (via address
teaching) channel address register which would pull on the
appropriate data line (one of DO through D7) when they respond to
any poll, regardless what address (0 through 15) they are at
(group 1 cards belong to address 8,to 15 but also responds to
poll via DO to D7).
Please refer to the appropriate channel adapter manual for
further information. Section 4.2.3 gives some extra information
on how group 0 polling is necessary for the AFI card.
The configuration switches (SWI switch 1 through 8) must be set
as follow:
SWITCH SWl:
Switches 1 through 6:
For standard cable length (3/12 meter differential, and 3 meter
single-ended), set switches SWl #1,#3,#5 to the ON position. SWI
#2,#4,#6 are don't cares.
The 25 m cable length is not recommended for single-ended cables
due to excessive resistance of the common return current ground
lines.
SWl switches 7 and 8:
These two switches are used to program the parity bit in the ID
(read) register (bit #11). The bit is read as 1 when switch 7 is
closed and switch 8 is open. If switch 7 is open and switch 8 is
closed, a 0 will be read. Note that the generation and checking
of parity is not affected by the setting of these two switches.
ALTERNATE CABLE LENGTH RESISTOR VALUES:
When the 24 m length is selected, a different custom length
cable can be used when resistors R5, R7 and R9 are installed with
the desired values as recommended in section 3.6
LINE CONFIGURATION:
As shipped from the factory, all of the frontplane signals are
differential and can be re-configured as single-ended (high true
logic) as follow: