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8 7 6 5 4 3 2 1
Version 0B
MS-6514 05/21/2001 Update
INTEL (R) Brookdale Chipset
D
Cover Sheet 1 D
Willamette/Northwood 478pin mPGA-B Processor Schematics
Block Diagram 2
CPU:
Clock CY28324 & ATA100 IDE CONNECTORS 3
Willamette/Northwood mPGA-478B Processor
mPGA478-B INTEL CPU Sockets 4-5
INTEL Brookdale MCH845 -- North Bridge 6-7 System Brookdale Chipset:
INTEL MCH845 (North Bridge) +
INTEL ICH2 -- South Bridge 8-9
INTEL ICH2 (South Bridge)
LPC I/O -- LPC47M142 & H/W Monitoring -- HECETA6 10
On Board Chipset:
C AC'97 Codec AD1885 & Amplifier TL072 11 C
BIOS -- FWH
FWH -- BIOS & Manual 12
AC'97 Codec -- AD1885
SDR DIMM-168 13 LPC Super I/O -- LPC47M142
AGP 4X SLOT (1.5V) 14 Clock Generation -- CY28324
H/W Monitoring -- HECETA6 (Option)
PCI SLOT 1 & 2 & 3 15
IO Connectors 16 Expansion Slots:
USB Hub & USB Connectors 17 AGP2.0 SLOT (1.5V) * 1
PCI2.2 SLOT * 3
B Front Panel & ATX Connectors & FAN 18 B
Votlage Regulator 19
Intersil HIP6301V+HIP6601A/02A-- CPU Power ( VRM9.2 ) 20
JUMPER SETTING 21
GPIO SETTTING 22
HISTORY 1 23
A A
MICRO-STAR
MSI H/W Project Leader : Andy Chen
H/W Project Engineer : Prudence Wang
Title
COVER SHEET
Size Document Number Rev
0B
MS-6514
Date: Monday, May 21, 2001 Sheet 1 of 23
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D D
ITP Port
(100MHz)
VCC12 Power VRM 9.2 Willamette/Northwood CK408 Clock
Supply CONN Socket (mPGA478-B) (100MHz)
Scalable Bus
AGP 4X (1.5V) 4X (66MHz) AGP
AGP CONN MCH: Memory
Controller HUB
(133MHz)
DIMM SKTS 1:3
C HUB Interface C
(14.318MHz)
SM Bus
Hardware
Monitor ICH2: I/O PCI (33MHz)
PCI Slots 1:3
A T A 33/ATA66/ATA100 Controller HUB
IDE CONN 1&2
(48MHz)
AC Link AC '97 Audio
AMP
(33MHz)
(33MHz)
USB Port 0:1 Codec
USB Back Panel Line Out
LPC Bus
MIC In
USB Port 2 Line In
USB Front Panel A U X In (Option)
USB Port 6
FWH: Firmware HUB C D -ROM (Option)
USB Front Panel
B
SMC I/O H/W Monitoring B
LPC47M142 Brookdale Chipset HECETA6 (Option)
USB Port 3
USB Port 4:5
USB Back Panel USB HUB
PS2 Mouse & Parallel (1) Floppy Disk
Keyboard Serial (1) Drive CONN
A A
MICRO-STAR
MSI H/W Project Leader : Andy Chen
H/W Project Engineer : Prudence Wang
Title
BLOCK DIAGRAM
Size Document Number Rev
0B
MS-6514
Date: Monday, May 21, 2001 Sheet 2 of 23
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CLOCK GENERATOR BLOCK *Trace less 0.5"
Shut Source Termination Resistors Pull-Down Capacitors
CPUCLK R86 49.9 CPUCLK C102 X_10p /N
U7 CPUCLK# R91 49.9 CPUCLK# C105 X_10p /N
FB29 600 39 41 R83 33 CPUCLK MCHCLK R93 49.9 MCHCLK C108 X_10p /N
VCC3 CPU_VDD CPU0 CPUCLK (4)
40 R88 33 CPUCLK# MCHCLK# R95 49.9 MCHCLK# C110 X_10p /N
+
CB33 CPU0# CPUCLK# (4)
Rubycon CT15 CB40 ITP_CLK R74 49.9 ITP_CLK C95 X_10p /N
0.1u 10u 0.1u 36 38 R92 33 MCHCLK ITP_CLK# R78 49.9 ITP_CLK# C96 X_10p /N
CPU_GND CPU1 37 R94 33 MCHCLK (6)
MCHCLK# MCHCLK# (6)
D for good filtering from 10K~1M CPU1# D
46
MREF_VDD 45 C_STP# R75 33 ITP_CLK
CB55 CPU2/CPU_STP# 44 P_STP# R77 33 ITP_CLK#
ITP_CLK (4) Trace less 0.2" MCH_66 C113 X_10p /N
0.1u CPU2#/PCI_STP# ITP_CLK# (4)
43 49.9ohm for 50ohm M/B impedance ICH_66 C114 X_10p /N
MREF_GND AGPCLK C117 X_10p /N
32 31 1 2 MCH_66 MCH_66 (6)
3V66_VDD 3V66_0 30 RN12 3 4 ICH_66
3V66_1 ICH_66 (9)
CB61 28 33 5 6 AGPCLK
R99 0.1u 29
3V66_GND
3V66_2
3V66_3
27 7 8 AGPCLK (14) CLOCK STRAPPING RESISTORS
X_0 /N ICH_PCLK C97 X_10p /N
6 FS2 R76 33 ICH_PCLK ICH_PCLK (8) FWH_PCLK C98 X_10p /N
FB30 600 VCC3V 9 FS2/PCI_F0 7 FS3 R80 33 FWH_PCLK FS4 R84 10K VCC3V
VCC3 PCI_VDD FS3/PCI_F1 8 FWH_PCLK (12)
MODE FS3 R79 10K VCC3V
+
CB37 Rubycon CT20 CB41 MODE/PCI_F2 PCICLK0 C107 X_10p /N
0.1u 10u 0.1u 5 10 FS4 FS1 R120 X_10K /N VCC3V PCICLK1 C109 X_10p /N
PCI_GND FS4/PCI0 11 R121 1K PCICLK2 C111 X_10p /N
for good filtering from 10K~1M PCI1 R89 33 APIC_CLK
18 12 APIC_CLK (8)
PCI_VDD PCI2 14 7 8 PCICLK0
CB52 PCI3 15 RN11 5 6 PCICLK0 (15)
PCICLK1 PCICLK1 (15) FS0 R110 10K VCC3V SIO_PCLK C112 X_10p /N
0.1u PCI4 33 PCICLK2 R104 X_1K /N APIC_CLK C103 X_10p /N
13 16 3 4 PCICLK2 (15)
PCI_GND PCI5 17 1 2 SIO_PCLK
* Put GND copper under Clock Gen. PCI6 SIO_PCLK (10)
FS2 R73 1K
connect to every GND pin 24
48_VDD 22 FS0 R112 33 ICH_48 MODE R85 1K
* 40 mils Trace on Layer 4 FS0/48MHz ICH_48 (9)
CB60 23 FS1 R118 33 SIO_48 ICH_48 C115 10p
with GND copper around it 0.1u 21 FS1/24_48MHz SIO_48 (10)
SIO_48 C119 10p
48_GND
* put close to every power pin 2 R62 33
C SIO_14 SIO_14 (10) MUL0 R67 10K VCC3V C
REF_VDD 48 MUL0 R71 33 ICH_14 R70 X_1K /N
* Trace Width 7mils. CB66 MUL0/REF0
1 MUL1 R64 33 AC_14 ICH_14 (9)
MUL1/REF1 AC_14 (9)
0.1u 47 R65 33 CODE_14 MUL1 R69 10K VCC3V ICH_14 C92 10p
* Same Group spacing 15mils REF_GND CODE_14 (11) R68 X_1K /N AC_14 C88 10p
34 3 C93 22p CODE_14 C89 10p
* Different Group spacing 30mils CORE_VDD X1 32pF SIO_14 C90 10p
CB58 X2 14M-32pf-HC49S-D
* Different mode spacing 7mils on itself 0.1u 33 4 C94 22p C_STP# R72 X_1K /N VCC3V
CORE_GND X2 P_STP# R81 X_1K /N
(9,10,13) SMBCLK SMBCLK 26 35 R97 475 Iref = 2.32mA
SMBDATA 25 SCLK IREF R105 X_10K /N VCC3V R13, R14 Support CY28324 install.
(9,10,13) SMBDATA R102 X_1K/N SDATA R111 X_0 /N
VCC3 20 CLK_RST# CLK_RST# (18) used only for EMI issue
19 RST# 42 R82 4.7K VCC3V
R103 1K VTT_GD# PWR_DN# VCC3V SMBCLK R66 4.7K
R122 X_220 /N Q12 CYPRESS CY28323/4 SMBDATA R63 4.7K VCC3_SB Trace less 0.2"
VCCP
X_NPN-3904LT1-S-SOT23
/N
PRIMARY IDE BLOCK SECONDARY IDE BLOCK
ATA100 IDE CONNECTORS
IDE2 IDE1
CN-BH-D2x20-1:21-BL-ZBT-S1 D2x20-1:21-WH-SBT
HD_RST# R368 33 1 2 HD_RST# R344 33 1 2
PDD7 3 4 PDD8 PDD[8..15] (9) SDD7 3 4 SDD8 SDD[8..15] (9)
B (9) PDD[0..7] PDD6 5 6 PDD9 (9) SDD[0..7] SDD6 5 6 SDD9
B
PDD5 7 8 PDD10 SDD5 7 8 SDD10
PDD4 9 10 PDD11 SDD4 9 10 SDD11
PDD3 11 12 PDD12 SDD3 11 12 SDD12
PDD2 13 14 PDD13 SDD2 13 14 SDD13
PDD1 15 16 PDD14 SDD1 15 16 SDD14
PDD0 17 18 PDD15 SDD0 17 18 SDD15
19 19
(9) PD_DREQ 21 22 (9) SD_DREQ 21 22
(9) PD_IOW# 23 24 (9) SD_IOW# 23 24
(9) PD_IOR# 25 26 (9) SD_IOR# 25 26
27 28 R362 470 27 28 R337 470
(9) PD_IORDY 29 30 (9) SD_IORDY 29 30
(9) PD_DACK# (9) SD_DACK#
(8) IRQ14 31 32 (8) IRQ15 31 32
(9) PD_A1 33 34 R316 0 PD_DET (9) (9) SD_A1 33 34 R318 0 SD_DET (9)
(9) PD_A0 35 36 PD_A2 (9) (9) SD_A0 35 36 SD_A2 (9)
(9) PD_CS#1 37 38 PD_CS#3 (9) (9) SD_CS#1 37 38 SD_CS#3 (9)
(18) PD_LED 39 40 (18) SD_LED 39 40
R354 C242 R363 C243 R355 C228 R338 C229
47K 220p 10K X_4700p /N 47K 220p 10K X_4700p /N
VCC5 VCC3 VCC5 VCC3
VCC3 R306 1K VCC5
A RESET BLOCK HD_RST# A
R307
4.7K
R308 4.7K Q24 MICRO-STAR
R332 330 R96 330 NPN-3904LT1-S-SOT23 MSI H/W Project Leader : Andy Chen
VCC3 VCC3
H/W Project Engineer : Prudence Wang
PCIRST# 1 2 PCIRST#1 (6,10,12) PCIRST# 3 4 PCIRST#2 (14,15)
PCIRST# R313 4.7K Q25 Title
(8) PCIRST# NPN-3904LT1-S-SOT23
U17A U17B R311 CLOCK CY28324 & ATA100 IDE
DM7407-SOIC14 DM7407-SOIC14 10K Size Document Number Rev
(VCC5_SB) (VCC5_SB) 0B
MS-6514
Date: Monday, May 21, 2001 Sheet 3 of 23
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CPU SIGNAL BLOCK CPU GTL REFERNCE VOLTAGE BLOCK
VCCPS+ (20) VCCP
(6) HA#[3..31] VCCPS- (20)
ITP_CLK# (3) R115
ITP_CLK (3)
ITP_DB #
2/3*Vccp 49.9
R
VID[0..4] (10,20)
GTLREF1
HA#28
HA#18
1
0
9
7
6
5
4
3
2
1
0
9
7
6
5
4
3
2
1
0
HA#3
HA#3
HA#2
HA#2
HA#2
HA#2
HA#2
HA#2
HA#2
HA#2
HA#2
HA#1
HA#1
HA#1
HA#1
HA#1
HA#1
HA#1
HA#1
HA#1
HA#9
HA#7
HA#6
HA#5
HA#4
HA#3
HA#8
VID2
VID0
VID4
VID3
VID1
C136 C128 C118 R116
220p 220p 1u-0805 100
AD26
AC26
AE25
D D
AB1
AE1
AE2
AE3
AE4
AE5
W2
W1
M1
M4
M3
M6
T5
T4
T2
T1
U4
R6
U3
U1
R3
R2
N5
N4
N2
N1
Y1
V3
V2
P6
P4
P3
K1
K4
K2
A5
A4
L2
L3
L6
U10A
A35#
A34#
A33#
A32#
A31#
A30#
A29#
A28#
A27#
A26#
A25#
A24#
A23#
A22#
A21#
A20#
A19#
A18#
A17#
A16#
A15#
A14#
A13#
A12#
A11#
A10#
DBR#
A9#
A8#
A7#
A6#
A5#
A4#
A3#
VCC_SENSE
VID4#
VID3#
VID2#
VID1#
VID0#
VSS_SENSE
ITP_CLK1
ITP_CLK0
(6) HDBI#[0..3] HDBI#0 E21
HDBI#1 G25 DBI0# AA21 GTLREF1 VCCP
HDBI#2 P26 DBI1# GTLREF3 AA6 GTLREF2
HDBI#3 V21 DBI2# GTLREF2 F20
DBI3# GTLREF1 F6 R132
AC3 GTLREF0 2/3*Vccp 49.9
V6 IERR# AB4 BPM#5 GTLREF2
B6 MCERR# BPM5# AA5 BPM#4
(8) FERR# Y4 FERR# BPM4# Y6 C135 C129 C126 R134
(8) STPCLK# AA3 STPCLK# BPM3# AC4 220p 220p 1u-0805 100
W5 BINIT# BPM2# AB5 BPM#1
(8) HINIT# AB2 INIT#