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SX7 SYSTEM DIAGRAM 01
DDRIII-SODIMM1 DDRIII 1066 MHz
AMD Champlain CPU THERMAL
PAGE 6,7 SENSOR
35mm X 35mm
A A
S1G4 Processor PAGE 5 14.318MHz
DDRIII-SODIMM2 DDRIII 1066 MHz
638P (PGA) 25W
PAGE 6,7 PAGE 3,4,5 CPU_CLK
NBGFX_CLK CLOCK GEN
NBGPP_CLK ICS9LPRS476AKLFT-->HP
SBLINK_CLK SLG8SP628VTR-->HP
HT3 RTM880N-796 -->HP
PAGE 2
PCI-E
NORTH BRIDGE M93-S3/ Park-S3 PAGE 24
RS880M
PAGE 29
RTL8151DH 64 Bit,DDR3*4 PAGE 23
B B
(10/100/1000)
PAGE 28 PAGE 33
PAGE 8,9,10,11 PAGE 23
PAGE 17,18,19,20,21,22
ALINK X4 SBSRC_CLK
PAGE 28
SYSTEM CHARGER(bq24740)
PAGE 36,37 0,2,3,5 9 1 4 7 FS1 8 6
PAGE 31 SOUTH BRIDGE
3/5VS5 RT8206B PAGE 29 PAGE 32 PAGE 23 PAGE 32
PAGE 30
PAGE 38
SB820M
+1.1V(RT8029)/+1.1VS5/+1.8V PAGE 31
PAGE 29 PAGE 33 PAGE 33
C PAGE 39 C
PAGE 29 PAGE 12,13.14.15.16
DDR3 (RT8207)/+1.0V_VGA
PAGE 40
VGACORE(1.1V~0.9V)RT8028A
PAGE 41
PAGE 25 PAGE 29
PAGE 32
CPU_CORE ISL6265
PAGE 42
PAGE 27
SMBUS TABLE
SB--SCL0/SD0 Clock gen/ wirless LAN/ New +3V
D card/ DDR3/ DDR3 thermal/ D
Accelerometer/system thermal
PAGE 23 PAGE 28
EC -- AB1A Battery charge/discharge +3VPCU
EC -- AB2A VGA thermal +3V PAGE 28 PAGE 35
Size Document Number Rev
Custom 3A
Block Diagram
Date: Monday, March 15, 2010 Sheet 1 of 43
1 2 3 4 5 6 7 8
5 4 3 2 1
+1.1V L69
*BLM18PG181SN1D(180,1.5A)_6
C742
*22U/6.3V_8
C746
*0.1U/10V_4
C678
*0.1U/10V_4
C694
*0.1U/10V_4
+1.1V_CLKVDDIO
C743
*0.1U/10V_4
C695
*0.1U/10V_4
CLOCKS name
NBGFX_CLKP
NBGFX_CLKN
Discrete
NA
Clock pin function
to NB for VGA reference clock 02
EXT_GFX_CLKP RP21 STUFF to Park-S3 external reference clock -Discrete only
EXT_GFX_CLKN
D
SBLINK_CLKP to NB for AC-LINK reference clock D
600 ohm, 0.5A +3V_CLKVDD SBLINK_CLKN RP26 STUFF
+3V L70 +3V_CLKVDD
*BLM18PG181SN1D(180,1.5A)_6
CLK_VGA_27M_SS R441,R442
C733 C737 C747 C723 C744 C691 C745 C717 CLK_VGA_27M_NSS STUFF To Park-S3 27Mhz - Discrete only
*22U/6.3V_8 *2.2U/6.3V_6 *0.1U/10V_4 *0.1U/10V_4 *0.1U/10V_4 *0.1U/10V_4 *0.1U/10V_4 *0.1U/10V_4
Need check the net name for the short pad
Place within 0.5" R487 *261_4
U32
of CLKGEN
+3V_CLKVDD 4 50 E_CPUCLKP RP25 4 3 *0_4P2R_4
VDDDOT CPUK8_0T E_CPUCLKP 12
16 49 E_CPUCLKN 2 1
VDDSRC CPUK8_0C E_CPUCLKN 12
26 VDDATIG
Place very 35 VDDSB
40 30 NBGFX_CLKP RP22 4 3 *0_4P2R_4
close to 48
VDD_SATA ATIG0T
29 NBGFX_CLKN 2 1
VDDCPU ATIG0C
C/G 55 VDDHTT ATIG1T 28 E_VGA_CLKP RP21 4 3 *0_4P2R_4 E_VGA_CLKP 12
+3V_CLKVDD E_VGA_CLKN
56 VDDREF ATIG1C 27 2 1 E_VGA_CLKN 12 to Park-S3 -Discrete only
L64 +3V_CLK_VDDA 63 Clock for Dis only
*BLM18PG181SN1D(180,1.5A)_6 VDD48
C701 37 E_SBLINK_CLKP RP26 4 3 *0_4P2R_4
SB_SRC0T E_SBLINK_CLKP 12
C697 11 36 E_SBLINK_CLKN 2 1 to NB for AC-LINK reference clock
VDDSRC_IO SB_SRC0C E_SBLINK_CLKN 12
C *2.2U/6.3V_6 *0.1U/10V_4 17 32 E_SBSRC_CLKP RP24 4 3 *0_4P2R_4 C
VDDSRC_IO SB_SRC1T E_SBSRC_CLKP 12
25 31 E_SBSRC_CLKN 2 1 to SB
VDDATIG_IO SB_SRC1C E_SBSRC_CLKN 12
34 VDDSB_IO
+1.1V_CLKVDDIO 47 VDDCPU_IO E_MINI1_CLKP RP20
SRC0T 22 4 3 *0_4P2R_4 E_MINI1_CLKP 12
21 E_MINI1_CLKN 2 1 to WLAN
SRC0C E_MINI1_CLKN 12
1 20 E_NEW_CLKP RP19 4 3 *0_4P2R_4
GND48 SRC1T E_NEW_CLKP 12
C720 *33P/50V_4 CG_XIN 7 19 E_NEW_CLKN 2 1 to New card
GNDDOT SRC1C E_NEW_CLKN 12
10 15 E_LAN_CLKP RP17 4 3 *0_4P2R_4
GNDSRC SRC2T E_LAN_CLKP 12
2
18 14 E_LAN_CLKN 2 1 to LAN
GNDSRC SRC2C E_LAN_CLKN 12
Y8
*14.318MHZ
24
33
GNDATIG QFN64 SRC3T 13
12
GNDSB SRC3C
43 9
1
C709 *33P/50V_4 CG_XOUT GNDSATA SRC4T
46 GNDCPU SRC4C 8
52 6 CLK_VGA_27M_SS R441 *33_4 OSC_SPREAD
GNDHTT SRC7T/27M_SS CLK_VGA_27M_NSS R442 *75/F_4
60 GNDREF SRC7C/27M 5 E_XTALI 18
42 R150 *100/F_4 XTALIN --for Park-S3-1.8V level input
SRC6T/SATAT
SRC6C/SATAC 41 27Mhz for Dis only
CG_XIN 61
CG_XOUT X1
62 X2
54 E_NBHT_CLKP RP23 4 3 *0_4P2R_4
HTT0T/66M E_NBHT_CLKP 12
can remove MOSFET level shift 53 E_NBHT_CLKN 2 1
HTT0C/66M E_NBHT_CLKN 12
SB/clock gen / DDR3 is 3.3V/S0 5,6,7,13,29,31,33 PCLK_SMB 2 SMBCLK
power level 5,6,7,13,29,31,33 PDAT_SMB 3 SMBDAT
64 CLK48MUSB R443 *22_4 modify SI
48MHz_0 E_48M_USB 13
R446 *22_4
E_48M_CR 12
CLK_PD# 51 PD# SEL_HT66 R449 *158/F_4
REF0/SEL_HTT66 59
58 SEL_SATA R479 *33_4
REF1/SEL_SATA E_SB_OSC 12
CLKREQ0# 23 57 SEL_27 R450 *90.9/F_4
B *CLKREQ0# REF2/SEL_27 EXT_NB_OSC 10 B
CLKREQ4# 38
CLKREQ3# *CLKREQ4#
39 *CLKREQ3#
CLKREQ2# 44
CLKREQ1# *CLKREQ2#
45 *CLKREQ1#
TGND
+3V
*RTM880N-796_QFN64
65
For EMI
R493 *8.2K_4 CLKREQ1#
NEW_CLKREQ# 13,29
R484 *8.2K_4 CLK_PD#
+3V_CLKVDD
C670 *10P/50V_4 E_48M_USB +3V
IDT ICS9LPRS480AKLFT--ALPRS480000
R477 *8.2K_4 CLKREQ0#
R492 *8.2K_4 CLKREQ2#
LAN_CLKREQ# 13,28 SLG SLG8SP628VTR--AL8SP628000
WLAN_CLKREQ# 13,33
C184 *10P/50V_4 E_XTALI R491 *8.2K_4 CLKREQ3#
R490 *8.2K_4 CLKREQ4# RTL RTM880N-796-- AL000880001
C667 *10P/50V_4 OSC_SPREAD
if use clock * default R485 R478 Clock chip has internal serial
request pin , need *8.2K_4 *8.2K_4
66 MHz 3.3V single ended HTT clock terminations
to pull Hi for
default sttting 1 SEL_27 for differencial pairs, external resistors
SEL_HTT66 SEL_SATA
0* 100 MHz differential HTT clock SEL_HT66
are
A A
reserved for debug purpose.
100 MHz non-spreading differential SRC clock not need to
SEL_SATA 1 R476
*8.2K_4 R467 stuff ,
0* 100 MHz spreading differential SRC clock *8.2K_4 SEL_HT66 have
SEL_27 1* 27MHz non-spreading singled clock
pull LOW
0 100 MHz spreading differential SRC clock RS880M
Size Document Number Rev
Custom 3A
Clock Generator
Date: Monday, March 15, 2010 Sheet 2 of 43
5 4 3 2 1
5 4 3 2 1
BLM21PG221SN1D(220,100M,2A)_8
03
+CPUVDDA
W/S= 15 mil/20mil 0.1U/10V_4 C541
+2.5V modify MV
L33 CPU CLK
2.5V@250mA CPU_LDT_RST# 300/F_4 R11
+1.1V +1.1V_VLDT C293 LS0805-100M-N C305 C324 C323 CPUCLKP CPU_PWRGD 300/F_4 R12
[email protected] 4.7U/6.3V_6 4.7U/6.3V_6 0.22U/6.3V_4 3300P/50V_4
12 CPUCLKP
CPUCLKN CPU_LDT_REQ#_CPU *300/F_4 R237
12 CPUCLKN +1.5V
R251 *0_6/S
Keep trace from resisor to CPU within 0.6" CPU_LDT_STOP# 2.2K_4 R246 modify MV
R253 *0_6/S +1.1V_VLDT +CPUVDDA 250mA
keep trace from caps to CPU within 1.2" U4D
U4A W/S= 15 mil/20mil
+CPUVDDA F8 M11
C306 10U/6.3V_8 +1.1V_VLDT +1.1V_VLDT 10U/6.3V_8 C457 CPUCLKIN R13 169/F_4 CPUCLKIN# +CPUVDDA VDDA1 VSS
D1 VLDT_A0 HT LINK VLDT_B0 AE2 F9 VDDA2 RSVD11 W18
C307 10U/6.3V_8 +1.1V_VLDT D2 AE3 +1.1V_VLDT 0.22U/6.3V_4 C427
D C315 0.22U/6.3V_4 +1.1V_VLDT VLDT_A1 VLDT_B1 +1.1V_VLDT 180P/50V_4 C433 CPUCLKP C18 3900P/25V_4 CPUCLKIN CPU_SVC_R D
D3 VLDT_A2 VLDT_B2 AE4 A9 CLKIN_H SVC A6
C316 180P/50V_4 +1.1V_VLDT D4 AE5 +1.1V_VLDT CPUCLKN C17 3900P/25V_4 CPUCLKIN# A8 A4 CPU_SVD_R
VLDT_A3 VLDT_B3 CLKIN_L SVD
HT_NB_CPU_CAD_H0 E3 AD1 HT_CPU_NB_CAD_H0 CPU_LDT_RST# B7
L0_CADIN_H0 L0_CADOUT_H0 12 CPU_LDT_RST# RESET_L
HT_NB_CPU_CAD_L0 E2 AC1 HT_CPU_NB_CAD_L0 CPU_PWRGD A7
L0_CADIN_L0 L0_CADOUT_L0 12 CPU_PWRGD PWROK
HT_NB_CPU_CAD_H1 E1 AC2 HT_CPU_NB_CAD_H1 CPU_LDT_STOP# F10 AF6 CPU_THERMTRIP_L#
L0_CADIN_H1 L0_CADOUT_H1 10,12 CPU_LDT_STOP# LDTSTOP_L THERMTRIP_L
HT_NB_CPU_CAD_L1 F1 AC3 HT_CPU_NB_CAD_L1 CPU_LDT_REQ#_CPU C6 AC7 CPU_PROCHOT_L#
HT_NB_CPU_CAD_H2 L0_CADIN_L1 L0_CADOUT_L1 HT_CPU_NB_CAD_H2 LDTREQ_L PROCHOT_L CPU_MEMHOT_L#
G3 L0_CADIN_H2 L0_CADOUT_H2 AB1 MEMHOT_L AA8
HT_NB_CPU_CAD_L2 G2 AA1 HT_CPU_NB_CAD_L2 CPU_SIC AF4 modify PV
L0_CADIN_L2 L0_CADOUT_L2 5,13 CPU_SIC SIC
HT_NB_CPU_CAD_H3 G1 AA2 HT_CPU_NB_CAD_H3 SideBand Temp sense I2C CPU_SID AF5
HT_NB_CPU_CAD_H[15..0] L0_CADIN_H3 L0_CADOUT_H3 5,13 CPU_SID SID
HT_NB_CPU_CAD_L3 H1 AA3 HT_CPU_NB_CAD_L3 CPU_ALERT AE6 W7 CPU_THERMDC
8 HT_NB_CPU_CAD_H[15..0] L0_CADIN_L3 L0_CADOUT_L3 5 CPU_ALERT ALERT_L THERMDC T44
HT_NB_CPU_CAD_H4 J1 W2 HT_CPU_NB_CAD_H4 W8 CPU_THERMDA
HT_NB_CPU_CAD_L[15..0] L0_CADIN_H4 L0_CADOUT_H4 THERMDA T45
HT_NB_CPU_CAD_L4 K1 W3 HT_CPU_NB_CAD_L4 R289 44.2/F_4 CPU_HTREF0 R6
8 HT_NB_CPU_CAD_L[15..0] HT_NB_CPU_CAD_H5 L0_CADIN_L4 L0_CADOUT_L4 HT_CPU_NB_CAD_H5 R286 44.2/F_4 CPU_HTREF1 HT_REF0
L3 L0_CADIN_H5 L0_CADOUT_H5 V1 +1.1V_VLDT P6 HT_REF1
HT_NB_CPU_CLK_H[1..0] HT_NB_CPU_CAD_L5 L2 U1 HT_CPU_NB_CAD_L5 place them to CPU within 1.5"
8 HT_NB_CPU_CLK_H[1..0] HT_NB_CPU_CAD_H6 L0_CADIN_L5 L0_CADOUT_L5 HT_CPU_NB_CAD_H6 VDDIO_FB_H
L1 L0_CADIN_H6 L0_CADOUT_H6 U2 42 CPU_VDD0_RUN_FB_H F6 VDD0_FB_H VDDIO_FB_H W9 VDDIO_FB_H 40
HT_NB_CPU_CLK_L[1..0] HT_NB_CPU_CAD_L6 M1 U3 HT_CPU_NB_CAD_L6 E6 Y9 VDDIO_FB_L
8 HT_NB_CPU_CLK_L[1..0] L0_CADIN_L6 L0_CADOUT_L6 42 CPU_VDD0_RUN_FB_L VDD0_FB_L VDDIO_FB_L VDDIO_FB_L 40
HT_NB_CPU_CAD_H7 N3 T1 HT_CPU_NB_CAD_H7
HT_NB_CPU_CTL_H[1..0] HT_NB_CPU_CAD_L7 L0_CADIN_H7 L0_CADOUT_H7 HT_CPU_NB_CAD_L7
8 HT_NB_CPU_CTL_H[1..0] N2 L0_CADIN_L7 L0_CADOUT_L7 R1 42 CPU_VDD1_RUN_FB_H Y6 VDD1_FB_H VDDNB_FB_H H6 CPU_VDDNB_RUN_FB_H 42
HT_NB_CPU_CAD_H8 E5 AD4 HT_CPU_NB_CAD_H8 AB6 G6
HT_NB_CPU_CTL_L[1..0] L0_CADIN_H8 L0_CADOUT_H8 42 CPU_VDD1_RUN_FB_L VDD1_FB_L VDDNB_FB_L CPU_VDDNB_RUN_FB_L 42
HT_NB_CPU_CAD_L8 F5 AD3 HT_CPU_NB_CAD_L8
8 HT_NB_CPU_CTL_L[1..0] HT_NB_CPU_CAD_H9 L0_CADIN_L8 L0_CADOUT_L8 HT_CPU_NB_CAD_H9 CPU_DBRDY
F3 L0_CADIN_H9 L0_CADOUT_H9 AD5 G10 DBRDY +1.5V
HT_CPU_NB_CAD_H[15..0] HT_NB_CPU_CAD_L9 F4 AC5 HT_CPU_NB_CAD_L9 CPU_TMS AA9 E10 CPU_DBREQ# R234 *300/F_4
8 HT_CPU_NB_CAD_H[15..0] HT_NB_CPU_CAD_H10 L0_CADIN_L9 L0_CADOUT_L9 HT_CPU_NB_CAD_H10 CPU_TCK TMS DBREQ_L R233 300/F_4
G5 L0_CADIN_H10 L0_CADOUT_H10 AB4 AC9 TCK +1.5VSUS
HT_CPU_NB_CAD_L[15..0] HT_NB_CPU_CAD_L10 H5 AB3 HT_CPU_NB_CAD_L10 CPU_TRST# AD9 AE9 CPU_TDO
8 HT_CPU_NB_CAD_L[15..0] HT_NB_CPU_CAD_H11 L0_CADIN_L10 L0_CADOUT_L10 HT_CPU_NB_CAD_H11 CPU_TDI TRST_L TDO add +1.5VSUS option R233
H3 L0_CADIN_H11 L0_CADOUT_H11 AB5 AF9 TDI
HT_CPU_NB_CLK_H[1..0] HT_NB_CPU_CAD_L11 HT_CPU_NB_CAD_L11 for Cas