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ZZZ1




PCB

DA80000B000
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Compal Confidential
Amazon Schematics Document
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Menlow-Silverthorne with Poulsbo
Monday, April 28, 2008

REV:0.2
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4 4




Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2006/08/04 Deciphered Date 2006/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Sheet
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom Amazon(Menlow) 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Sheet 1 of 43
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1 1




CPU-Silverthrone


PAGE 04 Clock Gen.
9UMS9633PAGE 15
H_A#(3..35)
FSB
H_D#(0..63) 400MHz




DDR2 -400/533 DDR2 64MX16X4pcs
K4T1G164QD
PAGE 13

LVDS I/F SingleChannel
LVDS
Connector AMP&Audio Jack
2


LED Driver SCH- Poulsbo PCM 3G Minicard
2




AZALIA Audio Codec
SDIO USB2.0 ALC 262PAGE 26

(Port 7)
USB2.0
PAGE 07 ATA100
Camera 2M

(Port 3)
SD card WIFI-AD1111
Camera 0.3M(Web)
(Port 4) LPC BUS (Port 5)

3G Minicard BlueTooth
I2C G-Sensor LBMA46LCS1
3
PS2
EC MMA7450L 3
(Port 1)
ENE KB926 GPS
page33 NEO-4S-0-000-2

(Port 2)
Touch Screen DCIN/CHARGER
MC9S08QG4CFFE
USB Client X1
SPI (Port 0)
USB Standard X1 BQ24100

BIOS Int.KBD SSD
T-9
BATT Conn/OTP
Joy Stick
+1.8/+1.5/+1.05/+0.9
ADBM-2100 +3VALW
MAX17017
PAGE 40
INT KB/CMOS LTC3442EDE
PAGE 33
4
+CPU_CORE +5VALW 4




RTCRST#/ PWR BTN
VOL_UP & DOWN/LID MAX8796GTJ+ TPS61030RSAR
PAGE 41
Shutter BTN
PAGE 33 Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2006/08/04 Deciphered Date 2006/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Block Diagram
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C Amazon 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, April 28, 2008 Sheet 2 of 43
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A




Voltage Rails O MEANS ON X MEANS OFF SKU ID Table
Vcc 3.3V +/- 5%
Ra 100K +/- 5%
+5VS Board ID Rb V AD_BID min V AD_BID typ V AD_BID max
power
+3VS
plane * 0 0 0 V 0 V 0 V
+1.8VS 1 8.2K +/- 5% 0.216 V 0.250 V 0.289 V
+VBAT
+1.5VS 2 18K +/- 5% 0.436 V 0.503 V 0.538 V
+5VALW +1.8V
+CPU_CORE CLOCK 3 33K +/- 5% 0.712 V 0.819 V 0.875 V
+3VALW +0.9V
+VCCP 4 56K +/- 5% 1.036 V 1.185 V 1.264 V
State
5 100K +/- 5% 1.453 V 1.650 V 1.759 V
6 200K +/- 5% 1.935 V 2.200 V 2.341 V
7 NC 2.500 V 3.300 V 3.300 V


S0 O O O O O SKU ID MB ID(H) MB ID(L)
0
S3 * 1 IEL10
O O O X X 2 IDL11 IDL01
S5 S4/AC
3 HDL10 HDL00 TBD
O O X X X 4 HDL20
S5 S4/ Battery only
5 IDL12 HDL30
O X X X X 6
S5 S4/AC & Battery
7
don't exist X X X X X
MB ID
H JAX10
L JAX60

O MEANS ON S3 : STR
X MEANS OFF S4 : STD
S5 : SOFT OFF
1
BOM Structure USB PORT LIST 1




MARK FUNCTION
@ NC FOR ALL PORT DEVICE
0 SPR
1 Client
2 SPR
3 CMOS
Address
4 3G, GPS
5 BT
6
EC SM Bus1 address EC SM Bus2 address 7
Device Address Device Address
ADM1032 1001 100X b
EEPROM(24C16/02) 1010 000X b




Poulsbo SM Bus address
Device Address
Clock Generator
( ICS954226) 1101 001Xb




Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2006/08/04 Deciphered Date 2006/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom Amazon(Menlow) 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, April 28, 2008 Sheet 3 of 43
A
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U57
XDP Reserve
+1.05VS

1300MHz@
SA00002BA00 XDP_TDI R2 1 2 56_0402_5%

XDP_TMS R3 1 2 56_0402_5%
+1.05VS XDP_TDO R4 1 2 56_0402_5%
D D
@
XDP_BPM#5 R5 1 2 56_0402_5%
+1.05VS_C6


R14 XDP_TRST# R6 1 2 56_0402_5%
H_INIT# 1 2
(7) H_A#[3..16] XDP_TCK
U57A 1K_0402_5% R7 1 2 56_0402_5%
H_A#3 E22 C26 H_ADS#
H_A#4 A[3]# ADS# H_BNR# H_ADS# (7)
A22
A[4]# BNR#
H25 H_BNR# (7) Intel WW25 change to mount




0
0
ADDR GROUP
H_A#5 D21 G24 H_BPRI#
H_A#6 A[5]# BPRI# H_BPRI# (7)
E24 A[6]#
H_A#7 B17 B27 H_DEFER#
H_A#8 A[7]# DEFER# H_DRDY# H_DEFER# (7)
A18 A[8]# DRDY# W28 H_DRDY# (7)
H_A#9 B23 D29 H_DBSY#
H_A#10 A[9]# DBSY# H_DBSY# (7)
A16 A[10]#
H_A#11 E18 C28 H_BR0# R8
H_A#12 A[11]# BR0# H_BR0# (7)
D15 56_0402_5%




CONTROL
H_A#13 A[12]# H_IERR#
B19 H1 2 1
H_A#14 A[13]# IERR# H_INIT# +1.05VS
A20 A[14]# INIT# F31 H_INIT# (7,30)
H_A#15 D17
H_A#16 A[15]# H_LOCK#
B15 A[16]# LOCK# D25 H_LOCK# (7)
H_ADSTB#0 D19
(7) H_ADSTB#0 ADSTB[0]# H_RESET#
RESET# M5 H_RESET# (7)
H_REQ#0 B25 D27 H_RS#0
(7) H_REQ#0 H_REQ#1 REQ[0]# RS[0]# H_RS#1 H_RS#0 (7)
(7) H_REQ#1 D23 REQ[1]# RS[1]# E28 H_RS#1 (7)
H_REQ#2 E20 E26 H_RS#2
(7) H_REQ#2 H_REQ#3 REQ[2]# RS[2]# H_TRDY# H_RS#2 (7)
(7) H_REQ#3 A24 F25 H_TRDY# (7)
H_REQ#4 REQ[3]# TRDY#
(7) H_REQ#4 B21
REQ[4]# H_HIT#
(7) H_A#[17..31] E30 H_HIT# (7)
H_A#17 HIT# H_HITM#
B5 F29 H_HITM# (7)
C H_A#18 A[17]# HITM# C
A12
H_A#19 A[18]# XDP_BPM#0 R884 0_0201_5%
D5 A[19]# BPM[0]# F1 1 2
+3VS
ADDR GROUP 1




H_A#20 E12 E2 XDP_BPM#1 R885 1 2 0_0201_5%
H_A#21 A[20]# BPM[1]# XDP_BPM#2 R886 0_0201_5%
B9 A[21]# BPM[2]# F5 1 2 C1
H_A#22 A6 D3 XDP_BPM#3 R887 1 2 0_0201_5%
H_A#23 A[22]# BPM[3]# XDP_BPM#4 R10 0_0201_5%
B13 A[23]# PRDY# E4 1 2 1 2




2
H_A#24 E14 F7 XDP_BPM#5
A[24]# PREQ#
XDP/ITP SIGNALS




H_A#25 A10 L2 XDP_TCK 0.1U_0402_16V4Z R9
H_A#26 A[25]# TCK XDP_TDI U2
B7 A[26]# TDI N2 10K_0402_5%
H_A#27 D13 M1 XDP_TDO H_THERMDA 2 1
H_A#28 A[27]# TDO XDP_TMS C2 2200P_0201_16V7K D+ VDD1
A8 P1




1
H_A#29 A[28]# TMS XDP_TRST# H_THERMDC THERM_SCI#
C4 J4 H_PROCHOT# (41) 1 2 3 6 2 1 EC_THERM# (10,30)
H_A#30 A[29]# TRST# D- ALERT# R11 @ 0_0402_5%
A14 G26
H_A#31 A[30]# RSVD14 T19 PAD EC_SMB_CK2 THERM#
B11 (30,31) EC_SMB_CK2 8 4 2 1 +3VS
H_ADSTB#1 A[31]# SCLK THERM#
(7) H_ADSTB#1 D11
ADSTB[1]# PROCHOT#
H5 10K_0402_5% R12 Check : to sb
T5 H_PROCHOT# 2 1 EC_SMB_DA2 7 5
THERM




THRMDA +1.05VS (30,31) EC_SMB_DA2 SDATA GND
H_A20M# G30 U4 R13 56_0402_5%
(30) H_A20M# A20M# THRMDC
H_PBE# J28
(7) H_PBE# FERR# S IC G780P81U MSOP 8P
H_IGNNE# H27 T1 H_THERMDA
IGNNE# THERMTRIP# H_THERMDC Address:100_1100
H_STPCLK# K1
(7) H_STPCLK# STPCLK#
H_INTR H31 H_THERMTRIP# SA00002BO00
(7) H_INTR H_NMI LINT0 H_THERMTRIP# (7)
(7) H_NMI L28 P29
H_SMI# LINT1 BCLK[0]
H CLK




(7) H_SMI# J26 R28
SMI# BCLK[1]
AE16
RSVD7 CLK_CPU_BCLK
AF17 RSVD8 VSS0 K31 CLK_CPU_BCLK (15)
AD15 CLK_CPU_BCLK#
RSVD9 CLK_CPU_BCLK# (15)
R1092 AD17 RSVD10
+1.05VS_C6 1 2 D9 A26
10K_0201_5% RSVD0 RSVD11
D7 E6 H_THERMDA, H_THERMDC routing together,
NC




RSVD1 RSVD6 +1.05VS_C6
E8
B
E10
RSVD2
G28 Trace width / Spacing = 10 / 10 mil B
RSVD3 RSVD15
L30 U30
RSVD4 TEST4
1




J30
RSVD5 R561
V27
TEST3 1K_0402_1%
K29 AE26
RSVD13 CMREF[1]
SILVERTHORNE_FCBGA8-441
2




800MHz@ +CMREF
1




1
R560
+1.05VS_C6 C624 1K_0402_1%
0.1U_0402_25V4K
2 R566
2




H_RESET# 1 2
1K_0402_1%
120_0402_5%
R562 1 2 H_PBE#

1K_0402_5% 1 2
(5,7) H_PWRGOOD
R563 1 2 H_A20M# R585 1K_0402_1%

R564 1 2 H_IGNNE#
1K_0402_5%




A A




Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2006/08/04 Deciphered Date 2006/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Silverthorne(1/3)-AGTL+/XDP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom JAX60 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, April 28, 2008 Sheet 4 of 43
5 4 3 2 1
5 4 3 2 1




(7) H_D#[0..15] H_D#[32..47] (7)
U57B
H_D#0 Y27 AE8 H_D#32
H_D#1 D[0]# D[32]# H_D#33
AH27 D[1]# D[33]# AD7
H_D#2 Y31 AH15 H_D#34
H_D#3 D[2]# D[34]# H_D#35
AC30 D[3]# D[35]# AF9




DATA GRP 0
H_D#4 AE30 AH9 H_D#36
H_D#5 D[4]# D[36]# H_D#37
AF29 AE10
H_D#6 D[5]# D[37]# H_D#38
AA26 AJ16
D H_D#7 D[6]# D[38]# H_D#39 D
AB31 AF13




DATA GRP 2
H_D#8 D[7]# D[39]# H_D#40
W30