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Stackup
R53 AMD Comal UMA/Muxless SYSTEM DIAGRAM TOP
GND
IN1
A
DDR3
ATI DDR3 900MHz IN2
A
PCI-E x 8 ( 0 ~ 7 ) VCC
SODIMM1 Channel A THAMES XT VRAM
Max. 4GB 128x16x8,64bit BOT
PG.12
AMD 29mm X 29mm
PG.21,22
DDR3 TDP 25W
SODIMM2 Channel B Trinity APU PG.14~20 +3V/+5V
Max. 4GB
PG.35
PG.13 35mm X 35mm DP Port 2
HDMI PG.25 +1.1V/+1.1VS5
PCI-E x 1 PG.36
FS1r2 socket 722 pin uPGA ANX3110
B DP Port 0 LVDS B
LAN0
DP to LVDS LVDS PG.23 +1.2V/+2.5V
WLAN TDP 35W Translator PG.11 PG.36
BT COMBO PG.2~5
EE PG.32
+VCC_CORE M1
DP Port 1 UMI PG.38
+VDDNB_CORE
CRT CRT PG.39
Card reader LAN PORT8 PG.24
USB 2.0 +1.5VSUS
RTS5229-GRT RTL8105E AMD FCH
10/100 PG.26 10/100 PG.29 USB2.0 Webcam +1.0V_VGA
LAN0 LAN1 PCI-E x 2 Ports X 1PG.28 TOP PG.23 +1.8V_VGA
C
Hudson M2/M3 USB 2.0
PORT0 PORT2
PG.43,44
C
PORT1,2 PORT11,12
USB 3.0 USB 2.0 24.5mm X 24.5mm +VGACore
656pin FCBGA SATA0
HDD PG.31 +1.5V_VGA
USB3.0 combo Accelerometer TDP 4.7W
Ports X 2 PG.28 PG.32
+3V_VGA
SMBUS PG.6~10 SATA1 PG.42
LPC ODD PG.31
KBC ITE8518 Charger
PG.33 Azalia PG.34
Speaker Discharger
KB TP ROM FAN PG.27
AUDIO PG.41
D D
CODEC HP/MIC
PG.28
IDT92HD87
Analog MIC PROJECT : R53
M1 PG.27 PG.28 Quanta Computer Inc.
Size Document Number Rev
Custom BLOCK EE DIAGRAM 1A
Date: Tuesday, November 22, 2011 Sheet 1 of 44
1 2 3 4 5 6 7 8
5 4 3 2 1
U25F
14
14
14
14
14
PEG_RXP0
PEG_RXN0
PEG_RXP1
PEG_RXN1
PEG_RXP2
PEG_RXP0
PEG_RXN0
PEG_RXP1
PEG_RXN1
PEG_RXP2
AB8
AB7
AA9
AA8
AA5
P_GFX_RXP0
P_GFX_RXN0
P_GFX_RXP1
P_GFX_RXN1
P_GFX_RXP2
PCI EXPRESS
P_GFX_TXP0
P_GFX_TXN0
P_GFX_TXP1
P_GFX_TXN1
P_GFX_TXP2
AB2
AB1
AA3
AA2
Y5
PEG_TXP0_C
PEG_TXN0_C
PEG_TXP1_C
PEG_TXN1_C
PEG_TXP2_C
C723 0.1U/10V_4
C726 0.1U/10V_4
C736 0.1U/10V_4
C725
C727
0.1U/10V_4
0.1U/10V_4
PEG_TXP0
PEG_TXN0
PEG_TXP1
PEG_TXN1
PEG_TXP2
PEG_TXP0
PEG_TXN0
PEG_TXP1
PEG_TXN1
PEG_TXP2
14
14
14
14
14
02
PEG X 8
14 PEG_RXN2 PEG_RXN2 AA6 Y4 PEG_TXN2_C C738 0.1U/10V_4 PEG_TXN2 PEG_TXN2 14
PEG_RXP3 P_GFX_RXN2 P_GFX_TXN2 PEG_TXP3_C C729 0.1U/10V_4 PEG_TXP3
14 PEG_RXP3 Y8 P_GFX_RXP3 P_GFX_TXP3 Y2 PEG_TXP3 14
14 PEG_RXN3 PEG_RXN3 Y7 Y1 PEG_TXN3_C C731 0.1U/10V_4 PEG_TXN3 PEG_TXN3 14
PEG_RXP4 P_GFX_RXN3 P_GFX_TXN3 PEG_TXP4_C C746 0.1U/10V_4 PEG_TXP4
14 PEG_RXP4 W9 P_GFX_RXP4 P_GFX_TXP4 W3 PEG_TXP4 14
14 PEG_RXN4 PEG_RXN4 W8 W2 PEG_TXN4_C C750 0.1U/10V_4 PEG_TXN4 PEG_TXN4 14
PEG_RXP5 P_GFX_RXN4 P_GFX_TXN4 PEG_TXP5_C C776 0.1U/10V_4 PEG_TXP5
14 PEG_RXP5 W5 P_GFX_RXP5 P_GFX_TXP5 V5 PEG_TXP5 14
PEG_RXN5 W6 V4 PEG_TXN5_C C777 0.1U/10V_4 PEG_TXN5
D
14 PEG_RXN5 P_GFX_RXN5 P_GFX_TXN5 PEG_TXN5 14 D
14 PEG_RXP6 PEG_RXP6 V8 V2 PEG_TXP6_C C773 0.1U/10V_4 PEG_TXP6 PEG_TXP6 14
PEG_RXN6 P_GFX_RXP6 P_GFX_TXP6 PEG_TXN6_C C770 0.1U/10V_4 PEG_TXN6
14 PEG_RXN6 V7 P_GFX_RXN6 P_GFX_TXN6 V1 PEG_TXN6 14
GRAPHICS
PEG_RXP7 U9 U3 PEG_TXP7_C C787 0.1U/10V_4 PEG_TXP7
14 PEG_RXP7 P_GFX_RXP7 P_GFX_TXP7 PEG_TXP7 14
PEG_RXN7 U8 U2 PEG_TXN7_C C782 0.1U/10V_4 PEG_TXN7
14 PEG_RXN7 P_GFX_RXN7 P_GFX_TXN7 PEG_TXN7 14
U5 P_GFX_RXP8 P_GFX_TXP8 T5
U6 P_GFX_RXN8 P_GFX_TXN8 T4
T8 P_GFX_RXP9 P_GFX_TXP9 T2
T7 P_GFX_RXN9 P_GFX_TXN9 T1
R9 P_GFX_RXP10 P_GFX_TXP10 R3 UMA can remove
R8 P_GFX_RXN10 P_GFX_TXN10 R2
R5 P_GFX_RXP11 P_GFX_TXP11 P5
R6 P_GFX_RXN11 P_GFX_TXN11 P4
P8 P_GFX_RXP12 P_GFX_TXP12 P2
P7 P_GFX_RXN12 P_GFX_TXN12 P1
N9 P_GFX_RXP13 P_GFX_TXP13 N3
N8 P_GFX_RXN13 P_GFX_TXN13 N2
N5 P_GFX_RXP14 P_GFX_TXP14 M5
N6 P_GFX_RXN14 P_GFX_TXN14 M4
M8 P_GFX_RXP15 P_GFX_TXP15 M2
M7 P_GFX_RXN15 P_GFX_TXN15 M1
PCIE_RXP0_WLAN AE5 AD5 PCIE_TXP0_C C156 0.1U/10V_4 PCIE_TXP0_WALN 32
32 PCIE_RXP0_WLAN P_GPP_RXP0 P_GPP_TXP0
TO WLAN PCIE_RXN0_WLAN AE6 AD4 PCIE_TXN0_C C164 0.1U/10V_4 PCIE_TXN0_WLAN 32 TO WLAN
32 PCIE_RXN0_WLAN P_GPP_RXN0 P_GPP_TXN0
AD8 P_GPP_RXP1 P_GPP_TXP1 AD2
AD7 P_GPP_RXN1 P_GPP_TXN1 AD1 TO PCIE-LAN
AC9 P_GPP_RXP2 P_GPP_TXP2 AC3
Move from APU to PCH TO PCIE CARD READER
GPP
Move from APU to PCH AC8
AC5
P_GPP_RXN2
P_GPP_RXP3
P_GPP_TXN2
P_GPP_TXP3
AC2
AB5
AC6 P_GPP_RXN3 P_GPP_TXN3 AB4
C AG8 AG2 UMI_TXP0_C C177 0.1U/10V_4 UMI_TXP0 C
7 UMI_RXP0 P_UMI_RXP0 P_UMI_TXP0 UMI_TXP0 7
7 UMI_RXN0 AG9 AG3 UMI_TXN0_C C167 0.1U/10V_4 UMI_TXN0 UMI_TXN0 7
P_UMI_RXN0 P_UMI_TXN0 UMI_TXP1_C C185 0.1U/10V_4 UMI_TXP1
7 UMI_RXP1 AG6 P_UMI_RXP1 P_UMI_TXP1 AF4 UMI_TXP1 7
AG5 AF5 UMI_TXN1_C C193 0.1U/10V_4 UMI_TXN1
UMI-LINK
7 UMI_RXN1 P_UMI_RXN1 P_UMI_TXN1 UMI_TXN1 7
7 UMI_RXP2 AF7 AF1 UMI_TXP2_C C208 0.1U/10V_4 UMI_TXP2 UMI_TXP2 7
P_UMI_RXP2 P_UMI_TXP2 UMI_TXN2_C C217 0.1U/10V_4 UMI_TXN2
7 UMI_RXN2 AF8 P_UMI_RXN2 P_UMI_TXN2 AF2 UMI_TXN2 7
AE8 AE2 UMI_TXP3_C C224 0.1U/10V_4 UMI_TXP3
7 UMI_RXP3 P_UMI_RXP3 P_UMI_TXP3 UMI_TXP3 7
7 UMI_RXN3 AE9 AE3 UMI_TXN3_C C238 0.1U/10V_4 UMI_TXN3 UMI_TXN3 7
P_UMI_RXN3 P_UMI_TXN3
+1.2V_VDDP R340 196/F_6 P_ZVDDP AG11 AH11 P_ZVSS R339 196/F_6
P_ZVDDP P_ZVSS
4/19 For Comal.
Trinity APU
+3V
HDT+ Connector for Debug only VID Override Circuit
BOOT VOLTAGE
+1.5V
R250
*0_4/S 4/19 For Comal. SVC SVD VFIX_+VDD VFIX_+VDD
=VCC/GND =OPEN
R243 R244
1K/F_4 1K/F_4 0 0 1.1 1.1
U18 0 1 1.0 1.2
B APU_RST# 1 6 APU_RST_L_BUF B
4,7 APU_RST# A1 Y1
2 GND VCC 5 1 0 0.9 1.0
Note:
APU_PWRGD 3 4 APU_PWROK_BUF
4,7 APU_PWRGD A2 Y2 To override VID,Remove Rd, Re, Rf, install Rc
1 1 0.8 0.8
set VID via SVC & SVD option RES.
74LVC2G07
+1.5VSUS +1.5V
R224 R227
J5 *1K/F_4 *1K/F_4 4/19 For Comal. R239 R242 R336
+1.5VSUS *1K_4 *1K_4 *2.2K_4
20
APU_TEST18 19
close to HDT 4 APU_TEST18 18
Rd
+1.5VSUS APU_TEST19 SVC R225 0_4 CPU_SVC
debug HEADER 4 APU_TEST19 17 4 SVC CPU_SVC 38
APU_RST_L_BUF Re Wait for power
APU_TDI R213 1K/F_4 CPU_LDT_RST_HTPA# 16 SVD R226 0_4 CPU_SVD
TP38 15 4 SVD CPU_SVD 38
APU_TCK R209 1K/F_4 APU_DBREQ# Rf
4 APU_DBREQ# 14
APU_TMS R212 1K/F_4 APU_DBRDY APU_PWRGD R338 0_4 CPU_PWRGD_SVID_REG CPU_PWRGD_SVID_REG 38
4 APU_DBRDY 13 4,7 APU_PWRGD
APU_TRST# R208 1K/F_4 APU_TCK
4 APU_TCK 12
APU_TMS APU_PWRGD have pull up 300ohm
4 APU_TMS 11
APU_TDI
4 APU_TDI
APU_TRST# 10 to +1.5V on page 4 R240 R241 R335
4 APU_TRST# APU_TDO 9 *220/F_4 *220/F_4 *220/F_4
4 APU_TDO 8
APU_DBREQ# R207 1K/F_4 APU_PWROK_BUF for normal operation Ra Rb Rc
7
A 6 open Ra , Rb,Rc A
5
4/19 For Comal. 4
3
2
1
*HDT CONN
88511-2001-20p-l
PROJECT : R53
Quanta Computer Inc.
Size Document Number Rev
Custom 1A
Llano PCIE/UMI/GPP
Date: Monday, November 14, 2011 Sheet 2 of 44
5 4 3 2 1
5 4 3 2 1
U25A M_A_DQ[0..63] 12
U25B M_B_DQ[0..63]
03 13
12 M_A_A[15:0] M_A_A0 MEMORY CHANNEL A M_A_DQ0 13 M_B_A[15:0]
U20 MA_ADD0 MA_DATA0 E13 MEMORY CHANNEL B
M_A_A1 R20 J13 M_A_DQ1 M_B_A0 T27 A14 M_B_DQ0
M_A_A2 MA_ADD1 MA_DATA1 M_A_DQ2 M_B_A1 MB_ADD0 MB_DATA0 M_B_DQ1
R21 MA_ADD2 MA_DATA2 H15 P24 MB_ADD1 MB_DATA1 B14
M_A_A3 P22 J15 M_A_DQ3 M_B_A2 P25 D16 M_B_DQ2
M_A_A4 MA_ADD3 MA_DATA3 M_A_DQ4 M_B_A3 MB_ADD2 MB_DATA2 M_B_DQ3
P21 MA_ADD4 MA_DATA4 H13 N27 MB_ADD3 MB_DATA3 E16
D M_A_A5 N24 F13 M_A_DQ5 M_B_A4 N26 B13 M_B_DQ4 D
M_A_A6 MA_ADD5 MA_DATA5 M_A_DQ6 M_B_A5 MB_ADD4 MB_DATA4 M_B_DQ5
N23 MA_ADD6 MA_DATA6 F15 M28 MB_ADD5 MB_DATA5 C13
M_A_A7 N20 E15 M_A_DQ7 M_B_A6 M27 B16 M_B_DQ6
M_A_A8 MA_ADD7 MA_DATA7 M_B_A7 MB_ADD6 MB_DATA6 M_B_DQ7
N21 MA_ADD8 M24 MB_ADD7 MB_DATA7 A16
M_A_A9 M21 H17 M_A_DQ8 M_B_A8 M25
M_A_A10 MA_ADD9 MA_DATA8 M_A_DQ9 M_B_A9 MB_ADD8 M_B_DQ8
U23 MA_ADD10 MA_DATA9 F17 L26 MB_ADD9 MB_DATA8 C17
M_A_A11 M22 E19 M_A_DQ10 M_B_A10 U26 B18 M_B_DQ9
M_A_A12 MA_ADD11 MA_DATA10 M_A_DQ11 M_B_A11 MB_ADD10 MB_DATA9 M_B_DQ10
L24 MA_ADD12 MA_DATA11 J19 L27 MB_ADD11 MB_DATA10 B20
M_A_A13 AA25 G16 M_A_DQ12 M_B_A12 K27 A20 M_B_DQ11
M_A_A14 MA_ADD13 MA_DATA12 M_A_DQ13 M_B_A13 MB_ADD12 MB_DATA11 M_B_DQ12
L21 MA_ADD14 MA_DATA13 H16