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Inter-Office Memorandum
To Mesa Users Date May 31, 1978
From Roy Levin Location Palo Alto
Subject Mesa 4.0 Microcode Update Organization CSL
XEROX
Filed on: [IRIS]
This memo outlines the differences in the (Alto) Mesa microcode for release 4.0. The DIS
Processor Principles of Operation [1] ("PrincOps") is scheduled to be revised soon, and
some of the changes indicated below will be incorporated in that revision. Others are
peculiar to the Alto implementation of Mesa and are indicated as, such. This document is
only a summary of the changes in Mesa 4.0; additional details may be found in the
references cited at the end of this memo.
Definitions of New Notions
Two new instruction properties have been introduced in the Mesa 4.0 instruction set:
Alignment
An aligned I-byte instruction must be the last significant byte in the word. Thus, if an
aligned, I-byte instruction appears in an even byte position, the microcode will ignore
the contents of the odd byte in the same word. An aligned 2-byte instruction must
have both bytes in the same memory word. An aligned 3-byte instruction consists of
an aligned I-byte opcode followed by a word containing the a and f3 bytes. In this
case, the a byte must be in the odd byte of the word following the opcode. In the 2-byte
case, padding is accomplished by use of the new instruction NOOP, which is discussed below.
Minimal stack
A minimal stack instruction expects its operands to be the only quantities on the stack,
and leaves the stack empty, except for any results it explicitly supplies.
These properties are peculiar to the Alto implementation of Mesa and will not be included
in the revision of the PrincOps.
Changes to the Instruction Set
Many of the changes in the Mesa 4.0 microcode bring the instruction set closer to the
PrincOps. In some cases, however, constraints imposed by the Alto architecture have
prevented an exact emulation of the PrincOps semantics. The following sections define the
differences between the Mesa 3.0 and 4.0 instruction sets, and relate those differences to the
PrincOps.
,Mesa 4.0 Microcode Update 2
Mesa 3.0 bytecodes not present in Mesa 4.0
LGS, SGS, LLS, SLS
LGDS, SGDS, LLDS, SLDS
WSDS
Space constraints in the Alto implementation have forced the elimination of these
bytecodes.
ADDL, ADDG
These instructions have been superseded by the PrincOps instructions LADRB and
GADRB (see below).
RXLO-3, WXLO
RIGO-3, WIGO, WILO
These instructions have been superseded by the PrincOps instructions RXLP, WXLP,
RIGP, RILP, and WILP (see below). Note that RILO has been retained, because of its
high static frequency.
RILl-3
Space constraints in the Alto implementation have forced the elimination of these
bytecodes. They will, however, remain in the PrincOps when it is revised. Note that
RILO has been retained in the Alto implementation.
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