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1 2 3 4 5 6 7 8
PCB STACK UP KL1 BLOCK DIAGRAM 01
8L
LAYER 1 : TOP
LAYER 2 : SGND1 CPU (Penryn) CPU THERMAL SENSOR
A PAGE 5 A
478P (uPGA)/35W 14.318MHz
LAYER 3 : IN1
LAYER 4 : IN2 CPU CORE(MAX17021)
PAGE 4,5 CLK_CPU_BCLK,CLK_CPU_BCLK#
LAYER 5 : VCC PAGE 41
CLK_MCH_BCLK,CLK_MCH_BCLK# CLOCK GEN
LAYER 6 : IN3 DREFCLK,DREFCLK# ICS9LPRS365BGLFT
FSB 667/800/1066 DREFSSCLK,DREFSSCLK#
LAYER 7 : SGND2 PAGE 3
VCCP +1.05V AND GMCH PCI-Express
LAYER 8 : BOT +1.5V(RT8204) 1X
Level-Shifter(PS8101)
PAGE 28
PAGE 22 GDDR3 X 2
(256MB)
PAGE 18
NORTH BRIDGE 27MHz FBA
GDDR3 X 2
DDRIII-SODIMM1 DDRIII 800/1066 MHz FBC (256MB)
PAGE 19
HDMI CONN
DDR III (TPS51116REGR) PAGE 11
1.5VSUS/SMDDR_VTERM
Cantiga NVIDIA PAGE 22
PCI-Express
B
/SMDDR_VREF 16X
B
PAGE 39 DDRIII-SODIMM2 DDRIII 800/1066 MHz
N10M-GS1(64bit) CRT CONN VGACORE(OZ8119)
PAGE 20 PAGE 42
PAGE 12 N10P-GE1(128bit)
Single link LCD CONN
PAGE 6~10 PAGE 13~19
PAGE 21
32.768KHz
DMI LINK NBSRCCLK, NBSRCCLK#
USB2.0
SATA0 150MB
SATA - HDD
0,1,8 9 4 2 6,10,11
PAGE 35
USB2.0 Ports USB+eSATA Port BlueTooth CCD Module Mini PCI-E Card X 2
SOUTH BRIDGE X3 X1 Express Card
PAGE 32 PAGE 32 PAGE 36 PAGE 37
SATA1 150MB
SATA - CD-ROM PAGE 33,36
PAGE 35
ICH-9M PCI-E
C SATA5 150MB C
USB+eSATA X2 X1 X1 X1
Azalia
PAGE 32
Mini PCI-E Card Express Card
PAGE 23,24,25,26 LAN Card Reader
(WLAN/ WWAN) BCM5784M JMB380
(10/100/1G LAN) (NEW CARD)
AUDIO CODEC
SYSTEM POWER(ISL6237) LPC
32.768KHz ALC269Q-GR PAGE 27
PAGE 40
PAGE 33 PAGE 29,30 PAGE 36
PAGE 31
24.576MHz
25MHz
Touch Pad EC
SYSTEM CHARGER(ISL6251A) PAGE 36 RJ45 CONN
IT8512E
PAGE 28 1394 CONN 6-IN-1 Card
PAGE 30 Reader CONN
Keyboard
PAGE 37 PAGE 34 PAGE 27 PAGE 28
D D
CIR Digital MIC Audio Jack Head-Phone Jack
PAGE 34 (Internal MIC) (External MIC) + SPDIF
PAGE 31 PAGE 31 PAGE 31
FAN SPI BIOS PROJECT : KL1
PAGE 37 PAGE 34 Quanta Computer Inc.
Size Document Number Rev
Custom A1A
BLOCK DIAGRAM
Date: Friday, March 06, 2009 Sheet 1 of 43
1 2 3 4 5 6 7 8
5 4 3 2 1
Board Stack up Description 02
PCB Layers Voltage Rails
Layer 1 TOP Voltage Rails ON S0~S2 ON S3 ON S4 ON S5 Control signal
Layer 2 GND VCC_CORE V VRON
D D
+1.5V V MAINON
Layer 3 IN1
+1.05V V MAINON
Layer 4 IN2
5V_S5/3V_S5 V V V V S5_ON
Layer 5 SVCC
Layer 6 IN3 5VSUS/3VSUS/1.5VSUS V V SUSON
Layer 7 GND
SMDDR_VTERM/+3V/+5V/+15V/+1.8V V MAINON
Layer 8 BOTTOM +VGACORE/+VGA1.1V V MAINON
LANVCC V V LAN_ON
Power On Sequencing Timing Diagram 3VPCU V V V V VL
5VPCU V V V V VL
VID
VRON Tsft_star_vcc
Vboot Vid
C VCC_CORE Tboot C
Tboot-vid-tr
CPU_UP Tcpu_up
Vccp
Vccp_UP Tvccp_up
Vccgmch ACIN POWER ON TIMING
GMCHPWRGD Tgmch_pwrgd
ACIN
CLK_ENABLE# 5VPCU/3VPCU
IMVP6_PWRGD Tcpu_pwrgd NBSWON# From IT8512E
DNBSWON# To ICH9-M
From IT8512E
Penryn Power-up Timing Specifications
S5_ON
To ICH9-M
Td
RSMRST#
B From ICH9-M B
RESET#
SUSB#,SUSC#
From IT8512E
SUSON
BCLK From IT8512E
MAINON
Tc
VSUS,VCC
Te
PWRGOOD +1.5V/+1.05V
VRON
Tf
Ta Tb
VCC_CORE
VCC
Vcc,boot CLK_EN# To clock generator
VID[6:0] 99ms < t 214
PWROK
To GMCH/other PCI device
PLTRST#\PCIRST#
A A
+1.05V
Ta=VCC and VCCP asseration to VID[6:0] vaild PROJECT : KL1
Tb=VID[6:0] stable to VCC vaild
Tc=BCLK stable to PWRGOOD assertion
Td=PWRGOOD to RESET# de-assertion time
Quanta Computer Inc.
Te=Vcc,boot vaild to PWRGOOD assertion time Size Document Number Rev
Custom A1A
SYSTEM INFORMATION
Date: Friday, March 06, 2009 Sheet 2 of 43
5 4 3 2 1
1 2 3 4 5 6 7 8
03
+3V
RP28 4P2R-S-0@EV
R_DOT96 2 1 CLK_PCIE_VGA (13)
L67 R_DOT96# 4 3 CLK_PCIE_VGA# (13)
1 2
HI0805R800R-00
1
1
1
1
1
C713 C706 C373 C705 C372 C375
10U/6.3V_8 .1U/10V_4 .1U/10V_4 .1U/10V_4 .1U/10V_4 .1U/10V_4 RP9 4P2R-S-33@EV
2
2
2
2
2
R_DREFSSCLK 4 3 27M_NONSS (15)
R_DREFSSCLK# 2 1 27M_SS (15)
A L64 A
1 2
HI0805R800R-00 U34
1
+CK_VDD_MAIN 16 54 CLK_CPU_BCLK
VDDPLL3 CPUCLKT0 CLK_CPU_BCLK (4)
C710 C703 9 53 CLK_CPU_BCLK#
VDD48 CPUCLKC0 CLK_CPU_BCLK# (4)
10U/6.3V_8 .1U/10V_4 2
2
61
VDDPCI
VDDREF
CK505 CPUCLKT1
51 CLK_MCH_BCLK
CLK_MCH_BCLK (6)
39 50 CLK_MCH_BCLK#
VDDSRC CPUCLKC1 CLK_MCH_BCLK# (6)
VDDCPU 55 C-TEST DEL RP32
VDDCPU CPU_ITP
47 CLK_PCIE_MINI_C (33)
+CK_VDD_MAIN2 CPUT2_ITP/SRCT8 CPU_ITP#
12 46 CLK_PCIE_MINI_C# (33)
VDD96I/O CPUT2_ITP/SRCC8
20
L65 VDDPLL3I/O R_DOT96 RP10 4
26 13 3 *4P2R-S-0@IV DREFCLK (7)
VDDSRCI/O DOTT_96/SRCT0 R_DOT96#
1 2 45 14 2 1 DREFCLK# (7)
HI0805R800R-00 VDDSRCI/O DOTC_96/SRCC0
36
VDDSRCI/O R_DREFSSCLK RP29 2
17 1 *4P2R-S-0@IV DREFSSCLK (7)
1
1
1
1
1
1
27MHz_Nonss/SRCCLK1/SE1 R_DREFSSCLK#
49 18 4 3 DREFSSCLK# (7)
C711 C708 C704 C707 C377 C376 C374 VDDCPU_IO 27Mhz_ss/SRCCLC1/SE2
48
10U/6.3V_8 .1U/10V_4 .1U/10V_4 .1U/10V_4 .1U/10V_4 .1U/10V_4 .1U/10V_4 NC CLK_PCIE_SATA
21
2
2
2
2
2
2
SRCCLKT2/SATACL CLK_PCIE_SATA (23)
22 CLK_PCIE_SATA#
CG_XIN SRCCLKC2/SATACL CLK_PCIE_SATA# (23)
60
CG_XOUT X1 CLK_PCIE_CARD
59 24 CLK_PCIE_CARD (27)
X2 SRCCLKT3/CR#_C CLK_PCIE_CARD#
25 CLK_PCIE_CARD# (27)
SRCCLKC3/CR#_D
+3V 27 CLK_PCIE_LAN
SRCCLKT4 CLK_PCIE_LAN# CLK_PCIE_LAN (29)
28 CLK_PCIE_LAN# (29)
SRCCLKC4
56 38 PM_STPPCI#
(25) CK_PWG CK_PWRGD/PD# PCI_STOP# PM_STPPCI# (25)
2
CLK_BSEL1 FSB 57 37 PM_STPCPU#
B Y4 FSLB/TEST_MODE CPU_STOP# PM_STPCPU# (25) B
R541 CG_XIN 1 2 CG_XOUT C-TEST DEL R574 41 CLK_PCIE_ICH
SRCCLKT6 CLK_PCIE_ICH# CLK_PCIE_ICH (24)
*10K_4 40
SRCCLKC6 CLK_PCIE_ICH# (24)
14.318MHZ+/- 10ppm
1
1
1
CGCLK_SMB 64 44 CLK_PCIE_MINI
TME (11,12,25,33,36) CGCLK_SMB CGDAT_SMB SCLK SRCCLKT7/CR#_F CLK_PCIE_MINI# CLK_PCIE_MINI (33)
C701 C692 63 43
(11,12,25,33,36) CGDAT_SMB SDATA SRCCLKC7/CR#_E CLK_PCIE_MINI# (33)
27P/50V/NPO_4 27P/50V/NPO_4 C-TEST DEL RP30 & RP31
2
2
30 RSRC_MCH
SRCCLKT9 CLK_PCIE_3GPLL (7)
15 31 RSRC_MCH#
GND SRCCLKC9 CLK_PCIE_3GPLL# (7)
19
R549 GND CLK_PCIE_NEW
11 34 CLK_PCIE_NEW_C (36)
4.7K_4 GND48 SRCCLKT10 CLK_PCIE_NEW#
52 35 CLK_PCIE_NEW_C# (36)
GNDCPU SRCCLKC10
8
GNDPCI NEW-CARD_CLK_REQ#_R R563 475/F_4
58 33 NEW-CARD_CLK_REQ# (36)
GNDREF SRCCLKT11/CR#_H CLK_3GPLLREQ#_R R539 475/F_4
23 32 CLK_MCH_OE# (7)
GNDSRC SRCCLKC11/CR#_G
29
GNDSRC
42
GNDSRC PCLK_MINI_LPC R552 33_4
1 PCLK_LPC_DEBUG (33)
PCICLK0/CR#_A PCIE_LANREQ#_R R551 475/F_4
3 PCIE_LANREQ# (29)
PCICLK1/CR#_B TME
0=overclocking PCICLK2/TME
4
R_PCLK_8512 R537 33_4
5 PCLK_LPC_8512 (34)
of CPU and PCICLK3 FCTSEL1
6
PCICLK4/27_SELECT
SRC Allowed
1 = overclocking 7 ITP_EN R542 33_4
PCI_F5/ITP_EN PCLK_ICH (24)
R546 22/F_4
CLK_48M_USB (25)
of CPU and SRC USB_48MHZ/FSLA
10 FSA R547 2.2K_4 CLK_BSEL0
FSC R567 10K_4 CLK_BSEL2
not Allowed 62 R568 22/F_4
C FSLC/TST_SL/REF CLK_14M_ICH (25) C
GCLK_SEL = FCTSEL1 ICS9LPRS365BGLFT/SLG8SP512T
+3V
FCTSEL1 PIN13 PIN14 PIN17 PIN18
(PIN13)
CK505 TSSOP64
2
0=UMA DOT96T DOT96C SRCT1/LCDT_100 SRCT1/LCDT_100 +3V
R530
Realtek RTM875T-606-VD-GRT AL000875K00
10K_4@EV 1 = External ICS ICS9LPRS365BGLFT ALPRS365K13 NEW-CARD_CLK_REQ# R559 2 1 10K_4
SRCT0 SRCC0 27Mout-NSS 27Mout-SS
1
FCTSEL1 VGA CLK_MCH_OE# R548 2 1 10K_4
2
R531 FSC FSB FSA CPU SRC PCI
*10K_4@IV
CPU Clock select
1 0 1 100 100 33 C687 *27P/50V_4 PCLK_LPC_8512
1
CLK_BSEL0
(4,7) CPU_BSEL0 MCH_BSEL0 (4,7)
0 0 1 133 100 33 C685 *27P/50V_4 PCLK_ICH
C-TEST DEL R533 SOVT DEL R528
0 1 1 166 100 33 C688 *27P/50V_4 PCLK_LPC_DEBUG
0=UMA R538 *1K/F_4
1 = External VGA C686 27P/50V_4 CLK_48M_USB
CLK_BSEL1
0 1 0 200 100 33
(4,7) CPU_BSEL1 MCH_BSEL1 (4,7) CLK_14M_ICH
0 0 0 266 100 33 C709 *27P/50V_4
C-TEST DEL R580 SOVT DEL R573