Clevo_W830T_W840T.pdf part of Clevo Clevo W830T W840T Clevo_W830T_W840T.pdf, Clevo Clevo_W830T

Text preview for : Clevo_W830T_W840T.pdf part of Clevo Clevo W830T W840T Clevo Clevo_W830T_W840T.pdf

Back to : Clevo_W830T_W840T.pdf | Home

Schematic Diagrams

System Block Diagram

CLEVO W830T/W840T System Block Diagram W8X0T MB BOARD
CPU,NB,SB,EC,LCD,RAM,HDD
CLOCK GEN. M/B BOARD MULTI BOARD BLUETOOTH,K/B
6-71-W83T0-D02A
SILEGO PROCESSOR 6-71-W84T0-D02A
6-71-W83T7-D02A
6-71-W84T7-D02A 6-71-W84T0-D02A
SLG8SP513V I n te l C el er o n 7 23 6-71-W83T0-D02A
64-Pin QFN HDMI W8X0T I/O BOARD
9.0x9.0 mm 956 FCPGA New Card,Lan,Wlan,3G,
22X 22mm Card Reader,CCD,Fan,
14.318 MHz CRT/RGB USB3
Socket P 6-71-W83T1-D02A
MEMORY TERMINATIONS FSB 6-71-W84T1-D02A
B.Schematic Diagrams

667/800/1067MHz Vtt=1.05V USB0 W830T MULTI BOARD
PCIE 100 MHz MIC,SPK,DC_IN,HDMI
DDR3 SDRAM SOCKET
NORTH BRIDGE LVDS USB1 BATTERY,USB0,USB1
,CRT
Cantiga-SFF 6-71-W83T7-D02A
Sheet 1 of 46

IN
MI
GS40 LVDS AZALIA W840T MULTI BOARD

C
System Block SO-DIMM1 1363 FCBGA CODE
Realtek
MIC,SPK,DC_IN,HDMI
27x25 mm BATTERY,USB0,USB1

OUT
HP
DDRIII ALC272
9x9x1.6 mm ,CRT
Diagram 667/800 MHz
Controller Link 0
6-71-W84T7-D02A

1.5V DMI X4 AUDIO W830T CLICK BOARD
USB 1.1/2.0 480 MHz AMP INT.
TPA SPK Click Conn,LED
6-71-W83T2-D02
SYSTEM SMBUS AZALIA LINK 24 MHz 6017A2
THERMAL SMART W840T CLICK BOARD
SATA HDD
SATA I/II SOUTH BRIDGE BATTERY
SENSOR Click Conn
3.0Gb/s ICH9M-SFF LPC 33 MHz ASC75 25 6-71-W84T2-D02

100 MHz PCIE
569 BGA 32.768 EC SMBUS
16x16 mm
KHz VCORE
EC
IT8502E
SPI
TOUCH
PAD
CIiCK BOARD
6-71-W83T2-D02
INT. K/B 128pins LQFP 6-71-W84T2-D02 1.5V/1.5VS/0.75V
BT
1 4x 1 4x 1 .6 mm
USB4 32.768 1.8V/1.05VS
KHz

EC SMBUS
I/O BOARD
6-71-W83T1-D02A
VGFX_CORE
NEW CARD Mini CARD 6-71-W84T1-D02A
CARD READER SOCKET
USB5 5VS/3VS/3.3V/5V
JMICRO USB2 CCD
JMB251 WLAN USB6
7x7 mm 80Port VDD3/VDD5
25 MHz U SB 1. 1/ 2 .0 480 MHz
AC_IN,CHARGE
SI M Ca rd Mini CARD
CARD SOCKET SMART
R J-45 READER FAN
7 IN 1 USB10 USB3
3G
MMC/SD/MS/MS Pro

B - 2 System Block Diagram

http://hobi-elektronika.net
Schematic Diagrams

Clock Generator

CLOCK GENERATOR
LAYOUT NOTE:
Sheet 2 of 46
3 .3 VS_ G 1 .0 5 V S 1. 05 V S _ G

C2 6 4
? ? Pin? ? ? , ? ? ? ? ? ? ? ? ? 0.1u? CAP
C 42 C 2 66 C 2 63 C 26 5 C2 6 8 C 26 2 C 27 4 C2 6 9
R1 8 2 * H C B 1 00 5 K F -1 2 1T 2 0 _1 0 m li _ s ho rt

C 41 C2 7 2 C2 7 0 C 44 C4 3 C2 6 7 C2 7 3
Clock Generator
1 u_ 6 . 3 V _X 5 R _ 0 4 0 . 1u _ 1 6V _Y 5V _0 4 0 . 1u _ 1 6V _Y 5 V _0 4 *0 . 1 u _1 6 V _ Y 5 V _ 0 4 *0 . 1 u_ 1 6 V _Y 5 V _0 4 * 0. 1 u _ 16 V _ Y 5 V _ 0 4 0. 1 u _ 1 6V _ Y 5V _ 0 4 1 0 u _6 . 3 V _ X5 R _0 6 1 u_ 6 . 3 V _ X5 R _ 0 4 1 u _ 6. 3V _ X 5 R _ 0 4 0 . 1 u_ 1 6 V _Y 5 V _ 04 0. 1 u _ 16 V _ Y 5 V _ 0 4 0 . 1 u_ 1 6 V _ Y 5 V _ 04 *0 . 1 u_ 1 6 V _ Y 5 V _ 04 *0 . 1 u _1 6 V _ Y 5 V _ 04 *0 . 1 u _1 6 V _ Y 5 V _ 0 4

0.1uF near the every power pin.

B.Schematic Diagrams
3. 3V S
PLACE CRYSTAL WITHIN 500 MILS OF CK410M
XT A L _ I N 3. 3 V S _ G 1 . 05 V S _ G 3. 3 V S 3 .3 VS_ G
C 25 9 C2 5 8 R1 7 9
X3 U 12 * H C B 10 0 5 K F -1 21 T 2 0_ 1 0 m li _ sh o rt
1 2 XT A L _ OU T 1 0 u_ 6 . 3 V _ X5 R _ 0 6 1u _ 6 . 3V _X 5 R _ 0 4
10mil
X 8 A 0 14 3 1 A F K 1 H _ 1 4. 3 1 8 18 M H z 4 19
9 V DD_ R E F V D D _I /O 27
V DD_ P C I V D D _P L L 3 _I /O
16 33
C2 6 1 C 2 60 23 V DD_ 4 8 V DD_ S R C_ I/O _1 43
V DD_ P L L 3 V DD_ S R C_ I/O _2
3 3p _ 5 0V _ N P O_ 0 4 3 3 p _5 0 V _ N P O _ 04 46 52
62 V DD_ S R C V DD_ S R C_ I/O _3 56
V DD_ C P U V D D _ C P U _I /O
44 P M_ S T P C P U #
C P U _ S T OP # P M_ S T P C P U # 1 5
45 P M_ S T P P C I # Zo =50O
AL
XT _ OU T 2 P C I _ S T OP # 63 CL K _ P W RG D P M_ S T P P C I # 15
X T A L _ OU T C K P W R GD / P D # C L K _ P W R GD 15
X TA L _ I N 3
C 2 57 * 1 0p _ 5 0V _ N P O_ 0 4 P CL K _ T P M 8 XT AL _ IN 61 C L K _ C P U _B C L K
P CI_ 0 /CL K RE Q _ A # C P U _0 C LK _C P U _ B C LK 3
*3 3 _0 4 R1 7 5 T 47 10 60 C L K _ C P U _B C L K #
11 P CI_ 1 /CL K RE Q _ B # C P U _ 0# 58 C L K _ MC H _ B C L K C LK _C P U _ B C LK # 3
T 48 P CI_ 2 C P U _ 1 _ MC H C LK _M C H _B C L K 6
P C LK _ K B C R1 7 6 3 3_ 0 4 12 57 C L K _ MC H _ B C L K #
18 PCL K _ KB C R1 7 7 1 0K _0 4 13 P CI_ 3 C P U _1 _ MC H # 54 C LK _ P C I E _ N E W _ C A R D C LK _M C H _B C L K # 6
^P C I _ 4 / LC D C L K _S E L S R C _ 8/ C P U _ I T P C LK _P C I E _ N E W _C A R D 2 6
R1 7 3 3 3_ 0 4 14 53 C LK _ P C I E _ N E W _ C A R D #
14 P C LK _I C H R1 7 8 4 . 7 K _1 % _ 04 P C I F _ 5 / I TP _E N S R C _ 8 # / C P U _I T P # C LK _P C I E _ N E W _C A R D # 26
Zo =50O
R1 8 1 2 . 2 K _0 4 FSL A 17 55
3 CL K _ B S E L 0 U S B _ 4 8M H z / F S _ A N C
C L K _ I C H 48 R1 8 0 3 3_ 0 4 64
1 5 C L K _ I C H 48 CL K_ BSEL 1 F S _B / TE S T _ MO D E

3 CL K _ B S E L 1 C L K _ I C H 14 FSL C CL K _ DR E F S S
1 5 C L K _ I C H 14 R1 7 4 3 3_ 0 4 5 24 C LK _D R E F _ S S 7
R1 7 2 2 . 2 K _0 4 R E F / F S _ C / TE S T_ S E L L CD CL K /2 7 M 25 CL K _ DR E F S S #
3 CL K _ B S E L 2 L C D C L K # / 2 7 M_ S S C LK _D R E F _ S S # 7 Zd iff=95O
CL K _ DR E F 20
7 CL K _ DR E F CL K _ DR E F # S R C _ 0 / D O T _9 6
7 CL K _ DR E F # 21
S R C _ 0 # / D O T_ 9 6 # 28 CL K_ SA T A
I C H _S M B C LK 0 S R C _2 CL K_ SA T A# C LK _S A TA 13
Zdi ff=95O 1 2, 1 5 I C H _ S MB C L K 0 7 29 C LK _S A TA # 1 3
I C H _S M B D A T0 6 S CL S R C _ 2# 31 CL K_ PCIE_ IC H
1 2, 1 5 I C H _ S MB D A T 0 S DA S R C _ 3 / C L K R E Q_ C # CL K_ PCIE_ IC H# C LK _P C I E _ I C H 1 4
32 C LK _P C I E _ I C H # 14
1 S R C _ 3 # / C L K R E Q_ D # 34
V S S _R E F S R C _4
15 35
18 V S S _P C I S R C _ 4# 48 CL K_ PCIE_ C R
V S S _4 8 S R C _6 CL K _ P CIE _ C R# C LK _P C I E _ C R 2 6
22 47 C LK _P C I E _ C R # 26
26 V S S _I / O S R C _ 6# 51 R 1 83 4 7 0 _0 4
V S S _P LL 3 S R C _7 / C LK R E Q_ F # N E W _ C A R D _ R E Q# 2 6
30 50 R 1 84 * 4 70 _ 0 4 L A N _C L K R E Q # 26
36 V S S _S R C _ 1 S R C _ 7# / C LK R E Q_ E # 37
V S S _S R C _ 2 S R C _9 CL K_ PCIE_ W L A N # C LK _P C I E _ W L A N 2 6
49 38 C LK _P C I E _ W L A N # 2 6
59 V S S _S R C _ 3 S R C _ 9# 41 CL K_ PCIE_ 3 GP L L
V S S _C P U S R C _ 10 C L K _ P C I E _ 3 GP LL # C LK _P C I E _ 3 GP L L 7
65 42 C LK _P C I E _ 3 GP L L # 7
66 T H R M _P A D _ 1 S R C _ 1 0# 40 R 52 4 7 0 _0 4
T H R M _P A D _ 2 S R C _ 1 1 / C L K R E Q_ H # M C H _C L K R E Q # 7
67 39 R 53 4 7 0 _0 4 W L A N _C L K R E Q # 26
68 T H R M _P A D _ 3 S R C _1 1 # / C L K R E Q_ G#
T H R M _P A D _ 4
69
70 T H R M _P A D _ 5
T H R M _P A D _ 6

S L G8 S P 5 13 V

FS LC F SL B FS LA C K5 05
Pin54/53 Pin28/29 Pin31/32 Pin34/35 Pin48/47 Pin37/38 Pin41/42
H os t Cl ock
BS EL 2 BS EL 1 BS EL 0 Fr eq ue ncy
0 0 0 26 6 MH z 10 66 M Hz
SRC8 SRC2 SRC3 SRC4 SRC6 SRC9 SRC10
0 1 0 20 0 MH z 80 0 MH z NEW_CARD CLK_SATA# PCIE_ICH PCIE_GLAN PCIE_CR PCIE_WLAN PCIE_3GPLL
3 .3 VS 3 , 6 , 7 , 10 , 1 2 , 1 3, 1 4 , 1 5, 16 , 1 8 , 19 , 2 1 , 2 2, 2 3 , 2 5, 2 6
0 1 1 16 6 MH z 66 7 MH z 1 .0 5 VS 3 , 4 , 5 , 6, 7, 9 , 1 0 , 13 , 1 6 , 2 1, 2 2

Pin51 Pin50 Pin39 Pin40

CR#_F CR#_E CR#_G CR#_H

NEW_CARD_REQ# LAN_CLKREQ# WLAN_CLKREQ# MCH_CLK_REQ

Clock Generator B - 3

http://hobi-elektronika.net
Schematic Diagrams

Penryn SFF 1/3

U1 A U1 B
6 H _ A # [ 3 5 : 3] 6 H_ D# [6 3 :0 ] H _ D # [ 6 3: 0] 6
H_ A # 3 P2 M4 H _ D #0 F 40 AP4 4 H _ D# 3 2
H_ A # 4 V4 A [ 3] # AD S# J5 H_ A D S # 6 H _ D #1 G 43 D [0 ]# D[3 2 ]# AR4 3 H _ D# 3 3
A [ 4] # B NR # H_ B N R# 6 D [1 ]# D[3 3 ]#
H_ A # 5 W1 L5 H _ D #2 E 43 AH4 0 H _ D# 3 4
H_ A # 6 A [ 5] # BPR I# H_ B P R I # 6 H _ D #3 D [2 ]# D[3 4 ]# H _ D# 3 5
T4 J 43 AF 4 0
A [ 6] # D [3 ]# D[3 5 ]#

AD

DATA GROUP 0
H_ A # 7 AA1 N5 H _ D #4 H 40 AJ 4 3 H _ D# 3 6
H_ A # 8 A [ 7] # D EF ER # H_ D E F E R # 6 H _ D #5 D [4 ]# D[3 6 ]# H _ D# 3 7
AB4 F38 H 44 A G4 1

DR GROUP 0
H_ D RD Y # 6

OUP 2
H_ A # 9 T2 A [ 8] # DR DY # J1 H _ D #6 G 39 D [5 ]# D[3 7 ]# AF 4 4 H _ D# 3 8
H _A # 1 0 A [ 9] # DB S Y # H_ D B S Y # 6 H _ D #7 D [6 ]# D[3 8 ]# H _ D# 3 9
A C5 E 41 AH4 4
A [ 10 ] # D [7 ]# D[3 9 ]#

CONTROL
H _A # 1 1 A D2 M2 H _ D #8 L 41 A M4 4 H _ D# 4 0
H_ B R 0 # 6

DATA GR
H _A # 1 2 A D4 A [ 11 ] # B R0 # H _ D #9 K 44 D [8 ]# D[4 0 ]# AN4 3 H _ D# 4 1
H _A # 1 3 A [ 12 ] # H _ I E RR # H _D # 10 D [9 ]# D[4 1 ]# H _ D# 4 2
AA5 B4 0 N 41 A M4 0
H _A # 1 4 AE5 A [ 13 ] # IE RR # D8 H _ I NIT # H _D # 11 T 40 D [ 1 0] # D[4 2 ]# AK4 0 H _ D# 4 3
H _A # 1 5 A [ 14 ] # IN IT # H_ IN IT # 1 3 H _D # 12 D [ 1 1] # D[4 3 ]# H _ D# 4 4
AB2 M 40 A G4 3
H _A # 1 6 A C1 A [ 15 ] # N1 H _D # 13 G 41 D [ 1 2] # D[4 4 ]# AP4 0 H _ D# 4 5
A [ 16 ] # L OC K # H _ L OC K # 6 H _D # 14 D [ 1 3] # D[4 5 ]# H _ D# 4 6
Y4 M 44 AN4 1
6 H _ A DS T B # 0 A DS T B [0 ] # G5 H _D # 15 L 43 D [ 1 4] # D[4 6 ]# AL 4 1 H _ D# 4 7
6 H _ R E Q# [ 4 : 0 ] R ESET # H_ C P UR S T # 6