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A B C D E
Garda-5 Block Diagram Project code: 91.4Q201.001
PCB P/N : 55.4Q201.XXX
SYSTEM DC/DC
TPS51120
INPUTS OUTPUTS
41
REVISION : 06206-SA 5V_S5
Mobile CPU
DCBATOUT
4
CLK GEN. (Hannstar, GCE) 3D3V_S5
4
ICS951413 G792 SYSTEM DC/DC
Yonah 478
-1-0426
(RTM865T-300/CY28RS400) 20 TPS51124RGER 42
3 PCB STACKUP
INPUTS OUTPUTS
4, 5 TOP
DCBATOUT 1D8V_S3
AGTL+ 133/166MHz VCC 1D2V_S0
SVIDEO/COMP S APL5312 120mA
TVOUT 14
ATI RC410ME LVDS
S
3D3V_S0 1D5V_CPU_S0
AGTL+ CPU I/F 14"WXGA+ LCD 13 43
GND
SINGAL DDR2 CHANNEL
533/667MHz RGB CRT APL5332 1A
DDR2 x 2 INTEGRATED GRAPHICS
LVDS/TVOUT/CRT
CRT 14 BOTTOM
3D3V_S0 1D5V_NEW_
11,12 1 X4 PCIE SB I/F PCIE x 1 Mini Card*1 MINI_S0 43
802.11A/B/G 27
3 6 X1 PCIE GPP I/F APL5912 3A 3
Ver.:A13, 71.RC410.D0U 6,7,8,9,10 PCIE x 1 PWR SW
New card32
1D2V_S0 1D05V_S0
TPS223132 43
A-Link Express TPS51100 1A
Line In X4
PCMCIA I/F DDR_VREF_S3
31 PCMCIA 1D8V_S3 DDR_VREF_S0
Codec AZALIA CARDBUS SLOT 43
ENE PWR SW
31 ALC883 ATI SB460 CB1410 25 TPS2211
Support
APL5308 300mA
30 26 TypeII
USB2.0 8Ports
26
MIC In 3D3V_S5 1D8V_S5
SATA II (4 PORTS) RICOH 1394 43
AZALIA HD AUDIO 1.0 PCI BUS R5C832
1394 CONN 29 MS/MS Pro/xD/
INT.MIC AC97 2.3 MAXIM CHARGER
ATA 66/100/133 CardReader MMC/SD/SDIO MAX8725 44
6 in 1
LPC I/F
28,29 29
2 31 OP AMP Mini-PCI INPUTS OUTPUTS 2
G1432Q 31 ACPI 1.2
802.11A/B/G 32
INT RTC CHG_PWR
INT.SPKR PCI/PCI BDGE LAN 18V 4.0A
DCBATOUT
Reltek10/100 TXFM RJ45 UP+5V
31 24 24 5V 100mA
MAX4411 RTL8100CL 23
Line Out
LPC BUS CPU DC/DC
(SPDIF) Lab Ver. :A11, 71.SB460.A0U ISL6262
Eng Ver. :A12, 71.SB460.B0U 39,40
MODEM INPUTS OUTPUTS
RJ11 MDC Card 15,16,17,18,19 SIO KBC
ENE
BIOS LPC
22 MX29LV800 VCC_CORE_S0
NS87381 3910 DEBUG DCBATOUT
SATA
PATA
35 33 36 CONN. 36 0~1.3V 48A
1
USB FIR 35 Touch INT.
1
3 PORT
22 Pad 34 KB 34
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
22 Taipei Hsien 221, Taiwan, R.O.C.
MINI USB
HDD 21 CDROM Blue-tooth
Title
21 BLOCK DIAGRAM
Size Document Number Rev
A3
Garda-5 -1
Date: Wednesday, April 26, 2006 Sheet 1 of 46
A B C
History D E
===========================================================
2006/04/26 (-1 Modify)
USB PCI ROUTING TABLE 1. page 27, change R8/R226 to 100 ohm due to power/email to dark.
2. page 15, change C286/C287 from 18pf to 15pf due to frequence shift(from -6.7 to 4ppm).
Pair Device 3. page 23, change C295/C294 from 15p to 12p due to frequence shift(from -23.3 to 7.9ppm).
DEVICE IDSEL IRQ(Default) REQ# / GNT#
0 USB1 4. EMI Solution for USB/MDC
AD22 H REQ#1/ GNT#1
a. Change L23, L24, L31, L32 to "69.10084.071".
1 BT MiniPCI b. del R353,R354,R356,R360,R445,R446.
2 USB2 F : 1394 c. Change L1, L2 to "68.00331.011".
4 R5C832 AD20 H : 6 in 1 REQ#3/ GNT#3 5. Page 44, change C12/C14 to 78.10699.43L due to 78.10699.42L Obsoleted. 4
3 NEW C
===========================================================
4 USB3 LAN(RTL8100CL) AD17 E REQ#2/ GNT#2 2006/04/13 (-1 Modify)
5 CCD 1. Page 31, R447/R448 tp 33ohm.
CARDBUS CB1410 AD16 G REQ#0 / GNT#0 2. Page 45, Add D4:83.P4SSM.0AM.
6 MINIC1 3. Page 44, Change C321 from 78.10492.4BL to 78.10224.2BL(1000P, 50V, K0603).
7 NC USB UHCI AD29 A, B, C, D 4. Page 23, change R209 from 5.6K to 5.37K.
5. Page 24, change XF1 from 68.68161.30A to 68.01201.30A.
USB 2.0 EHCI AD29 A 6. Page 46, Mini card stand-off() need to be changed from 34.4P401.001 to 34.4A907.001.
7. change 84.27002.L04 to 84.27002.F31.
DMI-to-PCI AD30 REQ#1 / GNT#1 ===========================================================
PCI_CLK0 PCM
AC97 Modem B 2006/04/10 (-1 Modify)
PCI_CLK1 IEEE1394 A 1. Page 8, add "LVDS_DIGON" solution from ATI PA note.
AC97 Audio
PCI_CLK2 LAN 2. Page 31, Add R to GND and serial R for U60 pin13/15.
PCI_CLK3 MINI LPC Bridge ===========================================================
PCI_CLK4 KBC IDE AD31 2006/04/03 (SB Modify)
SATA A
PCI_CLK5 FWH B 1. Page 40, Dummy C593.
SMBus 2. Page 44, Del C32.
PCI_CLK6 SIO B
PCI_CLK7 SPDIFOUT 3. Page 41, DCBATOUT_51120 change to DCBATOUT (Del G4,G5,G6,G7,G8)
PCI Express AD28 A, B, C, D 4. Page 4/5, updae CPU symbol.
5. Page 15, Change X5 to same as X1 due to ME high limit issue, Cap. the same as X1 but should fine-tune.
3 Azalia Controller AD27 A 6. Page 39/41/42, change "GAP-CLOSE-PWR" to 0 ohm PAD due to layout concern. 3
===========================================================
2006/03/31 (SB Modify)
1. Page 3, change R139 to bead and C211 to 2.2u for CRT Jitter.
2. Page 6, change R105 from 1.8K to 4.7K.
3. Page 8, change C165 to 2.2u for ATI recommend.
4. Page 8, SIV EDID_CLK/DAT issue, change RN53 to 4.7K.
5. Page 14, SIV RBG fail:
6. Page 15,
RESISTOR a. PCIRST1#(1394) shoulder: Add 33 ohm @ SB.
b. PLT_RST1# overshot : change R144 to 33ohm & R141 to 100P.
Symbol name Value Tolerance Rating Size c. Add 0ohm for RTC power for ATI recommend.
0402=> 1/16W, 25V 2=>0402, 3=>0603, 5=>0805, 7. Page 40 , add 10U Cap.
(J: 5%, F: 1%, D: 0.5%, B: 0.1 %) 0603 => 1/16W, 75V 6=>1206, 0=>1210 8. Page 13/27, change Green LED4/LED5/LED1 to 83.00190.L70.
0805 => 1/10W, 100V (manual change yellow LED6/LED3/LED8/LED2 to 83.00190.S70).
9. EMI request:
10KR3 10K Ohm If no letter, it means J: 5% 1/16W, 75V 0603 a. Page 13, USB_PP5,USB_PN5 add COMMON CHOKE.
b. EC28,EC34,C208 add O.1Cap.
33D3R5 33.3 Ohm If no letter, it means J: 5% 1/10W, 100V 0805 c. CLK48_ICH( near CLK GEN.),SB_CLK33_FWH(near R177) add 20p Cap..
===========================================================
1KR3F 1K Ohm F: 1% 1/16W, 75V 0603 2006/03/28 (SB Modify)
2 1. Page 14, change Q15/Q14 to 2N7002 for SIV CRT SMBus bug. 2
The naming rule is value + R + size + tolerance 2. Page 15, Change C248/C261/C264/C263/C252 from 78.10491.4FL to 78.10523.5F1,
For the value, it can be read by the number before R. (R means resistor) and C262 from 78.10693.41L to 78.10623.51L.
For the tolerance, it can be read from the last letter. 3. Page 8, Add "LCDVDD_ON" PL 100K.
For the rating, we don't show on the symbol name. 4. Page 41, change U7 to AO4406(84.04406.A37).
For the size, R2=>0402, R3=>0603, R5=>0805,.... 5. Page 33, KBC GPIO09 for 1394.
6. Page 33, add 1u Cap. for ENE ECRST# spec. 2ms.
7. Page 31, add audio popo noise solution.
CAPACITOR 8. Page 25, change C520 to 1U for "GBRST#".
9. Page 28, change "GBUS_GRST#_1" timing.
Symbol name Value Tolerance Rating Size ===========================================================
(J: +/-5, K: +/-10, ( X5R / X7R < 80%, 2=>0402, 3=>0603, 5=>0805,
M: +/-20, Z: +80/-20) Y5V/Y5U/Z5U < 1/3 ) 6=>1206, 0=>1210
SCD1U10V2MX-1 0.1uF M/X5R 10V 0402
SC10U6D3V5MX 10uF M/X5R 6.3V 0805
SC2D2U16V5ZY 2.2uF Z/Y5V 16V 0805
The naming rule is
1 Capacitor type + value + rating + size + tolerance + material 1
SCD1U10V2MX-1 Wistron Corporation
SC=> SMT Ceremic, TC=> POS cap or SP cap 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
D1U => 0.1uF Taipei Hsien 221, Taiwan, R.O.C.
10V => the voltage rating is 10V Title
2=> 0402, 3=>0603, 5=>0805
M=>tolerance J, K, M, Z Reference
X=> X7R/X5R, Y=> Y5V Size Document Number Rev
A3
-1 => symbol version, nonsense to EE characteristic Garda-5 -1
Date: Wednesday, April 26, 2006 Sheet 2 of 46
A B C D E
Bead: Bead: Bead: 3D3V_S0
3D3V_S0 200ohm, 200mA. 3D3V_S0 200ohm, 200mA. 26ohm, 600mA.
R128 500mA R139
2 R377 1 3D3V_CLKPLL_S0 2 1 3D3V_48MPWR_S0 3D3V_CLKGEN_S0 2 1 SB Modify
0R3-0-U-GP 50mA 50mA HCB1608K-300T10GP
1
1
1
1
1
1
1
1
1
1
1
C483 0R3-0-U-GP 68.00214.111
SCD1U16V2ZY-2GP C211 C202 C210 C212 C216 C209 C201 C203 C207 C208
SC2D2U10V3ZY-1GP SC2D2U10V3ZY-1GP SCD1U16V2ZY-2GP
SC4D7U10V5ZY-3GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
DY At least 2.2u*1
2
2
2
2
2
2
2
2
2
2
2
4 4
At least
22u*1, 0.1U*1
At least
Ioh = 6 * Iref (2.32mA) 22u*1, 0.1u*7.
Voh = 0.7V @ 50 ohm
U29
C200
1 2 GEN_XTAL_IN 2 39 3D3V_CLKPLL_S0
X2 VDDA
1 X1
1
1
SC27P50V2JN-2-GP X2 GEN_XTAL_OUT_R 1 R140 2 CLK_IREF 37 3 3D3V_48MPWR_S0
475R2F-L1-GP IREF VDD48
11,18,27,32 SMB_CLK 7 SCLK
X-14D31818M-31GP R127 8 32 3D3V_CLKGEN_S0
11,18,27,32 SMB_DATA SDATA VDDATI
82.30005.831 1MR2J-1-GP FS_C 9
2
C199 FS_C
32 CLKREQ_NEW# 10 45
2
CLKREQA# VDDCPU
1 2 27 CLKREQ_MINI# 11 CLKREQB#
18 CLK48_ICH 1 2 CLK48 4 51
SC27P50V2JN-2-GP R134 33R2J-2-GP FS_B USB_48MHZ VDDPCI
2 1 53 FS_B/REF1
C594 DYSC20P50V2JN-1GP FS_A 54 56
FS_A/REF0 VDDREF
SMbus Table: 8 OSC14M 1 R132 2 33R2J-2-GP OSC14M_R 52 TEST_SEL/REF2
SEL_CK410# 50 35
Byte4 bit 4, CLKREQA#. 39 CLK_EN# CLK_EN# 6
CK410#/PCICLK0 VDDSRC
21
CPU_STP#_R VTT_PWRGD#/PD VDDSRC
Byte2 bit 3, CLKREQB#. 15 CPU_STP# 1 2 48 CPU_STOP# VDDSRC 14
R133 0R0402-PAD
"0": not controlled, "1": controlled. CPU_STP# CLK GEN Internal PH 120K 41 CPUCLKT2_ITP
PL: always output 40 CPUCLKC2_ITP SRCCLKC7 13
3 12 3
SRN33J-5-GP-U SRCCLKT7
8 CLK_MCH_BCLK 4 1 RN9CLK_MCH_BCLK_1 43 CPUCLKT1
NB free-running: 8 CLK_MCH_BCLK# 3 2 CLK_MCH_BCLK_1# 42 CPUCLKC1 SRCCLKC6 17
Byte5 bit5 =0. SRCCLKT6 16
4 CLK_CPU_BCLK SRN33J-5-GP-U 4 1 RN7CLK_CPU_BCLK_1 47
CLK_CPU_BCLK_1# CPUCLKT0
4 CLK_CPU_BCLK# 3 2 46 CPUCLKC0 SRCCLKC5 19
SRCCLKT5 18
36 23 CLK_PCIE_NEW_1# RN12 1 4 SRN33J-5-GP-U CLK_PCIE_NEW# 32
GNDSRC SRCCLKC4 CLK_PCIE_NEW_1
26 GNDSRC SRCCLKT4 22 2 NEW 3 CLK_PCIE_NEW 32
1 R137 2 CLKREQ_NEW# 20 GNDSRC
15 25 CLK_PCIE_MINI1_1# RN19 1 4 SRN33J-5-GP-U CLK_PCIE_MINI1# 27
1KR2J-1-GP GNDSRC SRCCLKC3 CLK_PCIE_MINI1_1
SRCCLKT3 24 2 MINIC 3 CLK_PCIE_MINI1 27
49 GNDPCI
1 R138 2 CLKREQ_MINI#
SRCCLKC0 33 CLK_PCIE_ICH_1# RN15 2 3 SRN33J-5-GP-U CLK_PCIE_ICH# 15
44 34 CLK_PCIE_ICH_1 1 4 CLK_PCIE_ICH 15
1KR2J-1-GP GNDCPU SRCCLKT0
31 GNDATI
27 CLK_NB_ALINK_1 RN22 2 3 SRN33J-5-GP-U CLK_NB_ALINK 9
FS_A ATIGCLKT1 CLK_NB_ALINK_1#
4,9 CPU_SEL0 1 2 38 GNDA ATIGCLKC1 28 1 4 CLK_NB_ALINK# 9
R129 4K7R2J-2-GP
55 30 CLK_NB_GFX_1 RN23 1 4 SRN33J-5-GP-U CLK_NB_GFX 9
GND ATIGCLKT0 CLK_NB_GFX_1#
18 SB_OSCIN 1 2 5 GND ATIGCLKC0 29 2 3 CLK_NB_GFX# 9
R126 33R2J-2-GP
ICS951413CGLF 71.95143.A0W
1 2 FS_B ICS951413 Ver C /CY28RS400 Ver.B /CV136
4,9 CPU_SEL1
R131 4K7R2J-2-GP 2nd source: 71.00865.A0W
2 2
35 CLK14_SIO 1 2
R130 33R2J-2-GP
4 CPU_SEL2 1 2 FS_C
R136 4K7R2J-2-GP
CK410# = 0, CK410 MODE 1 DY 2 33R2J-2-GP SEL_CK410#
R135
CK410# = 1, CK409 MODE CK410# CLK GEN Internal PL 120K
CLOCK FREQUENCY SELECT TABLE (MHz)
FSC FSB FSA CPU SRC PCI REF RN18 RN21
CLK_PCIE_MINI1# 1 4 CLK_NB_ALINK# 1 4
CLK_PCIE_MINI1 MINIC CLK_NB_ALINK
1 0 1 100 100 33 14.31 2
SRN49D9F-GP
3 2