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PRELIMINARY GUAM S1G4 SCHEMATIC DESIGN
DDR III, 1333MT/S UNBUFFERED DDR3 Optional CPU
Channel A NEAR SODIMM Temperature sensor
HDT 18,19 16
16
Channel B UNBUFFERED DDR3
FAR SODIMM
D
EXTERNAL CLOCK GENERATOR SCAN AMD S1G4 CPU D
16 18,19
SLG8LP625
20 SB-TSI
14,15,16,17 16
OUT
IN
HyperTransport
LINK0
16x16
LVDS CON LVDS MUX RS880M
43
HyperTransport LINK0 CPU I/F
PARK_XT_S3 X16 PCIE MUX
31--40 DX10 IGP
LVDS/TVOUT/TMDS Ambient Light Sensor
I2C I/F BOOTSTRAPS
VGA CON CRT MUX DISPLAY PORT X2 ROM(NB)
C
44 24 52 C
Side Port Memory
1 X16 PCIE I/F
1 X4 PCIE I/F WITH SB
6 X1 PCIE I/F
GPP PCIE INTERFACE
21,22,23,24,25
PCIE
LAN&CARDREADER JMC261
48 X4
USB 2.0
MINIPCIE WIFI AZALIA CODEC
47 HD AUDIO I/F
GPP INTERFACE SB820M CX20671
USB#4 42
USB2.0 (14)+1.1(2)
SATA III (6 PORTS)
SIM
card MINIPCIE USB 2.0 4 X1 PCIE GEN2 I/F
49
socket USB#8
B
INT. CLK GEN. SATA III I/F Mobile 2.5" HDD Mobile ODD 41 B
41
GB MAC
Bluetooth Finger Print CAM HW MONITOR
Reader USB#3 USB#1 USB#0 USB 2.0
USB#7 45 USB#6 45 USB#5 45 46 46 46 PCI/PCI BDGE
HW MONITOR I/F HW MONITOR CPU Tempreture Sensor
INT. RTC 28
EC 26,27,28,29
HD AUDIO
SPI I/F SPI ROM
LPC I/F 28
SPI I/F
ACPI 1.1 I2C I/F BOOTSTRAPS
ROM (SB) 30
BATTERY CHAGER CPU CORE CPU MEMORY POWER
7 8 9
DISCHARGE CIRCUIT
A
SYSTEM MAIN POWER 1V1DUAL/VLDT/ 1.5V/1.5VDUAL/ A
13 VCC_NB/+1.1V 10 1.8V/3.3V/5V 11
SCANNED IT8502E
MATRIX PS2 EC
KEYBOARD TOUCH PAD Bitland Information Techonogy Co.,Ltd.
RESET,FAN 49 49 49 Notebook R&D Division
& ENABLES 55
Title
BLOCK DIAGRAM
Size Document Number Rev
Custom 1.0
BM5016
5
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1
Sheet 1 of 54
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D
TABLE OF CONTENTS D
C C
B B
A A
Bitland Information Techonogy Co.,Ltd.
Notebook R&D Division
Title
TABLE OF CONTENTS
Size Document Number Rev
Custom 1.0
BM5016
5
http://pc-120.taobao.com/
4 3 2
Date: Thursday, August 05, 2010
1
Sheet 2 of 54
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AMD S1G4
CPU_VDDA_RUN CPU_VDDIO_SUS
DDRiII SODIMMX2--SYSTEM
BATTERY BATTERY +VIN CPU core CPU_VDD_RUN@38A VCCA 2.5V VDD MEM 4A
11.1V 62WHr CHARGER PWM MEM_VTT
VTT_MEM 0.5A
ISL6251 ISL6265A
CPU_VDD_RUN VDD CORE
1.375-1.500V 36A CLOCK GEN
AC ADAPTOR CPU core CPU_VDDNB_RUN@4A CPU_VDDNB_RUN VDDNB CORE
15-16V 90W PWM 0.9V 4A +3.3V BEAD 3.3V
ISL6265A VLDT
D
BEAD VLDT 1.2V TPDA D
CPU_VDDIO_SUS@9A CPU_VDDIO_SUS HD CODEC
DDR3 PWM VDD MEM TPDA +5V
LDO VTT [email protected] BEAD 5V AUDIO
VDDR +3.3V OP
TPS51128&RT9199GSP AOZ1024 VDDR 1.5A BEAD 3V
+5V PWM +3.3VDUAL
BEAD
+1.1VDUAL@10A RS880M
+1V~1.2V SW VLDT
+1.1V SW +VCC_NB_RUN BEAD VDDHTTX 1.2V 0.68A
+1.1V
ISL6228 BEAD VDDHTRX+HT 1.1V 0.68A
+1.1V SMSC1100--EC
BEAD VDDPCIE 1.1V 1.1A +3.3VDUAL
+1.8V 3.3V 0.5A
+1.8V SW [email protected] BEAD VDDA18 1.8V 0.64A
MAX8716-2/2 +VCC_NB
VDDC 1.0V-1.1V 7.6A LCD PANEL
+3.3V +3.3V
VDDG33 3.3V 0.06A SW 3.3V 1.5A
+1.8V
+3.3VALW BEAD VDDG18 1.8V 0.005A
+1.5V
+5VALW BEAD VDD18_MEM 1.8V 0.005A
+5V SW +1.5V BACK LIGHT
+3V SW BEAD VDD_MEM 1.8V 0.23A
C
+3.3V C
+5V LDO +3.3VDUAL@8A BEAD AVDD 3.3V 0.125A
+3V LDO +1.8V +VIN LED_BL
+5VDUAL@8A BEAD VDDLT18 0.22A
tps51125 +3.3V +VDD_MAIN
BEAD VDDLT33 0A
+1.8V USB X2 FR
BEAD PLLs 1.8V 0.1A +5VDUAL
+1.1V 5VDual
BEAD PLLs 1.1/1.2V 0.23A
VDDC PWM VDDC@15A
AMD SB800
TPS51128 +3.3V
VDDIO_33_PCIGP 3.3V 0.020A
+1.8V
VDDIO_18_FC 1.8V 0.050A
+1.1V
BEAD VDDAN_11_PCIE 1.1V 1A
CPU_VDDIO_SUS MVDDQ +1.5V 4A +3.3V
SWITCH BEAD VDDPL_33_PCIE 3.3V 0.030A
+1.1V MINI PCIE SLOT0,1,2
BEAD VDDAN_11_SATA 1.1V 0.8A +1.5V
+3.3V 1.5V (S0, S1) 0.5A
CPU_VDDIO_SUS 1.1V_1.0V_PWR 2.6A BEAD VDDPL_33_SATA 3.3V 0.020A each
SWITCH +3.3VDUAL
BEAD VDDAN_33_USB_S 3.3V 0.2A +3.3VDUAL 3.3V (S3, S5) 2.75A
+1.1VDUAL each
BEAD VDDAN_11_USB_S 1.2V 0.2A
+3.3VDUAL +3VRUN +1.1V SATA HD0,1
B
SWITCH VDDCR_11 1.1V 0.5A B
+1.1V
BEAD VDDAN_11_CLK 1.1V 0.4A
VDDIO_GBE_S/2 VDDRF_GBE_S +5V
+3.3VDUAL 1.8V_REG 1.5A +3.3VDUAL 5V (S3, S5) TBD
SWITCH VDDIO_33_GBE_S 3.3V
+1.5V +1.1VDUAL SATA ODD
VDDCR_11_GBE_S 1.1V +5V
PHY_VDDIO_DUAL 5V (S0, S1) TBD
VDDIO_GBE_S 3.3V
+3.3VDUAL
VDDIO_33_S 3.3V
CPU_VDDIO_SUS +1.5V@1A +1.1VDUAL
SWITCH VDDCR_11_S 1.1V
+1.1VDUAL VDDCD_11_USB 1.1V
BEAD
+5VDUAL +5V AZ_VDDIO_DUAL
VDDIO_AZ_S 3.3V OR 1.5V
SWITCH +1.1VDUAL
BEAD VDDCR_11_USB_S 1.1V
+3.3V
BEAD VDDPL_33_SYS 3.3V SYS PLL
+3.3VDUAL +3.3V +1.1V
SWITCH BEAD VDDPL_11_SYS 1.1 V SYS PLL
+3.3VDUAL
BEAD VDDPL_33_USB_S 3.3 V USB PLL
+3.3V CPU_VDDA_RUN +3.3VDUAL
BEAD VDDAN_33_S 3.3V HWM
2.5V LDO +3.3VDUAL
A BEAD VDDXL_33_S 3.3V A
+1.1V DUAL +1.1V
SWITCH AMD SB800
VDDC
MVDDQ Bitland Information Techonogy Co.,Ltd.
+3.3VDUAL S3,S4,S5 Notebook R&D Division
1.5V LDO 1.1V_1.0V_PWR PARK_XT_S3 Title
POWER DELIVERY CHART
+1.5VDUAL 1.8V_REG Size Document Number Rev
+3.3VDUAL SWITCH Custom 1.0
+3VRUN BM5016
5
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Date: Thursday, August 05, 2010
1
Sheet 3 of 54
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Power on Sequence required:
SB800:
1, +3.3VDUAL ramp before +1.1VDUAL
2, +3.3V ramp before +1.8v CPU_LDT_RST#
3, +1.8V ramp before +1.1v (SB TO CPU)
4, +3.3v ramp before +1.1v
5, +3.3VALW_R ramping down time > 300us
6, 50uS <= All power rails except +3.3VALW_R <= 40mS
7, 100uS <= +3.3VALW_R <= 40mS CPU_PWROK
(SB TO CPU) >1 mS Req.
RS880: CPU_CLKP/N running
1, 0 <(+3.3V) - (+1.8v) < 2.1
2, +1.8V ramp before +1.1v >1 mS Req.
3. +1.1V ramp before VCC_NB
running
D D
>1 mS Req. VCC_NB(all NB power) valid before NB_PWRGD.
SB OUTPUT NB_PWRGD
NB_PWRGD_IN
SLP_S3# 1V1DUAL_PWRGD
SB INPUT SB_PWRGD 1)+1.5V SWITCH TO +1.5VDUAL 2)LASSO_PWRON 3)LPCPD# for TPM 4) TO SB&KBC SYS_RST# 1V5_PWRGD/DNI
+1.2V_PWRGD KBC_GPIO77/DNI
+1.2V_PWRGD
PARK-XT_PGOOD
T3>0
1.8V_REG
T2>0
1.1V_1.0V_PWR RC=~ms
PCIE_REFCLKP/N RC=~ms
VDD_CT
T1>=0
RC=~ms
VDDC
RC=~ms
MVDDQ
RC=~22ms VCC_NB should not ramp before 1.1v
VCC_NB
RC=~4.7ms
VLDT
GROUP B
VRM_PWRGD AND 1V8_PWRGD
+1.1V
VRM_PWRGD
C RC=0 C
CPU_VDDR
RC=0
CPU_VDD_RUN
RC=0
CPU_VDDNB_RUN
VDDA_PWRGD
GROUP A
+2.5V_LDO
(CPU_VDDA_2.5_RUN)
+1.5V
1V8_PWRGD
RC=0
+1.8V
+5V/+3.3V
5V/3.3V_GATE
to S3
SLP_S3#
VDRAM_PWRGD
CPU MEM CTL &
DDR3 SODIMM PWRS
MEM_VTT VTT only will be shut down in S3 mode, and VTT for DDR3 SODIMM only.
MEM_VREF
CPU_VDDIO_SUS
SLP_S5#
Power button from EC to SB
PWR_BTN#_EC
20mS
CPU_THM/SB/SB_SCL1/2 delay
B RSMRST# B
SB_KB/SPI/LPC ROM PWRS
V3V5DUAL_PWRGD
1V1DUAL_PWRGD
SYSTEM_DUAL_PG_DELAY
+5VDUAL/+3.3VDUAL/+1.5VDUAL/+1.1VDUAL
DUAL RAILS When IMC, always on at all time( always PWR)
VDD_DUAL_EN
Power button pressed
Power button pressed
KBC is ready
AC not present scenario = LOW AC present= high
AC_OK
(ACIN detect)
KBC is powered by
A_VBAT & +3.3VALW +5VALW/+3.3VALW
LDO:5.4V
(from DCIN)
Battery inserted/AC IN
+VIN/+12V_HD
A_VBAT
A A
Bitland Information Techonogy Co.,Ltd.
Notebook R&D Division
Title
POWER SEQUENCE CHART
Size Document Number Rev
D 1.0
BM5016
Date: Thursday, August 05, 2010 Sheet 4 of 54
5 4 3 2 1
http://pc-120.taobao.com/
5 4 3 2 1
EXTERNAL CLOCK MODE NB CLOCK INPUT TABLE
NB CLOCKS RS880M
HT_REFCLKP
100M DIFF
AMD NORTHBRIDGE HT_REFCLKN
100M DIFF
REFCLK_P
A-LINK
RS880M REFCLK_N
14M SE (1.1V)
GPP_REFCLK vref
GFX_REFCLK
100M DIFF(IN/OUT)*
NB_GFX_REFCLKP/N
GPP_REFCLK
GPP REF_CLK
NBLINK_RCLKP/N
D D
HT_REFCLKP/N
NC or 100M DIFF OUTPUT
14.318MHZ
GPPSB_REFCLK 100M DIFF
NB_OSC
100MHZ
100MHZ
100MHZ
100MHZ
A_SODIMM
B_SODIMM
* RS880M can be used as clock buffer to output two PCIE referecence clocks
By deault, chip will configured as input mode, BIOS can program it to output mode.
CLK_REQ in CLK GEN
PCIE_REFCLKP/N PCIE GFX PARK_XT(RS880M, 16 LANES) 25M Hz
100MHZ EXT_PCIE_PE2_CLKREQ# PARK_XT
MEM_MB_CLK1_P/N
MEM_MB_CLK2_P/N
MEM_MA_CLK1_P/N
MEM_MA_CLK2_P/N
25M_X1
25M_X2
PCI_CLK0
PCICLK0 FOR DEBUG PORT
33MHZ
27M Hz
SMSC_CLK
PCICLK1 STRAPS SETTING,
33MHZ PCIE GEN1/PCIE GEN2
AMD CPU_CLKP/N EXTERNAL