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8 7 6 5 4 3 2 1
Last Schematic Update Date:
09/28/2001
D Cover Sheet 1 D
MS-6559 VERSION:1.0
Block Diagram
MAIN CLOCK GEN
2
3
SIS 645/650 CHIPSET
DDR CLOCK BUFFER MS-3 (D-LED) 4
Willamette/Northwood 478pin mPGA-B Processor Schematics
mPGA478-B INTEL CPU Sockets 5-6
SIS 645/650 NORTH BRIDGE 7- 10
CPU: SDR SLOT 11-12
Willamette/Northwood mPGA-478B Processor 13
SIS 961A SOUTH BRIDGE 14-17
System Brookdale Chipset: AGP SLOT 18
C SIS 645/650 (North Bridge) C
+961A (South Bridge) PCI SLOTS 19-21
On Board Chipset: IDE CONNECTOR 22
USB CONNECTOR 23
LPC Super I/O -- W83697HF
KB/MS CONNECTOR 24
Expansion Slots: AC'97 CODEC 25
AGP2.0 SLOT * 1
AUDIO CONNECTOR 26
PCI2.2 SLOT* 5
CNR CONNECTOR 27
CNR SLOT * 1
LPC I/O(W83697HF) 28
HARDWARE MONITOR 29
B
PARALLEL PORT 30 B
SERIAL PORT 31
FLASH MEMORY 32
VRM 9.X 33
VOLTAGE REGULATOR 34-35
ATX POWER CON & VGA CON 36
FRONT PANEL 37
Decoupling Capacitor 38
39
A A
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8 7 6 5 4 3 2 1
System Block Diagram
D D
SOCKET-478
Host Bus
Support Dual Monitor
SSTL-2 Termination
VGA VGA SLOT SDR SDRAM
D-SUB
SIS645/650
DIMM 1 DIMM 2 DIMM 3
C VGA Connector VGA CONNECTOR VGA C
HyperZip Analog In
S u pport Max to six-PCI Devices
512 MB
AC'97
Audio Codec
PCI SLOT 5 PCI SLOT 4 PCI SLOT 3 PCI SLOT 2 PCI SLOT 1 Analog Out
SiS961 ACR
IDE 1 IDE 2
KEYBOARD PS/2
/MOUSE
B USB 0 USB 2 B
USB 1 USB 4
LPC Bus USB 3 USB 5
FAN FAN FAN CONTROL VOLTAGE MONITOR
1 2
TEMPERATURE MONITOR
LPC Super I/O
Legacy FAN CONTROL
ROM
A GPIOs IR/CIR GAME/MIDI SERIAL PARALLEL FLOPPY
A
M I C R O - S T A R I N T ' L CO.,LTD.
Title
S y s t e m B l o c k Diagram
Size D o c u m e n t Number Rev
B MS-6559 10
Date: M o n d a y , N o v e m b e r 1 9 , 2001 Sheet 2 of 33
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
CPU SIGNAL BLOCK CPU GTL REFERNCE VOLTAGE BLOCK
VCCP
VCCPS+ 5
8 HA#[3..31] VCCPS- 5
Length < 1.5inch. R61
2/3*Vccp 49.9
VID[0..4] 31
GTLREF1
HA#31
HA#30
HA#29
HA#28
HA#27
HA#26
HA#25
HA#24
HA#23
HA#22
HA#21
HA#20
HA#19
HA#18
HA#17
HA#16
HA#15
HA#14
HA#13
HA#12
HA#11
HA#10
HA#9
HA#8
HA#7
HA#6
HA#5
HA#4
HA#3
VID2
VID1
VID0
C21 C22 C30 R62
VID4
VID3
D D
220p 220p 1u 100
AD26
AC26
AE25
AB1
AE1
AE2
AE3
AE4
AE5
W2
W1
M1
M4
M3
M6
T5
T4
T2
T1
U4
R6
U3
U1
R3
R2
N5
N4
N2
N1
Y1
V3
V2
P6
P4
P3
K1
K4
K2
A5
A4
L2
L3
L6
U4A
A35#
A34#
A33#
A32#
A31#
A30#
A29#
A28#
A27#
A26#
A25#
A24#
A23#
A22#
A21#
A20#
A19#
A18#
A17#
A16#
A15#
A14#
A13#
A12#
A11#
A10#
DBR#
A9#
A8#
A7#
A6#
A5#
A4#
A3#
VCC_SENSE
VID4#
VID3#
VID2#
VID1#
VID0#
VSS_SENSE
ITP_CLK1
ITP_CLK0
HDBI#0 E21 VCCP
8 HDBI#[0..3] DBI0#
HDBI#1 G25 AA21 GTLREF1
HDBI#2 DBI1# GTLREF3 GTLREF2
P26 AA6 Length < 1.5inch.
HDBI#3 V21 DBI2# GTLREF2 F20 R12
DBI3# GTLREF1 2/3*Vccp X_49.9
F6
GTLREF0 GTLREF2
AC3
IERR# BPM#5
V6 AB4
MCERR# BPM5# BPM#4 C16 C17 C4 R19
17 FERR# B6 AA5
Y4 FERR# BPM4# Y6 220p 220p X_1u X_100
17 STPCLK# STPCLK# BPM3#
AA3 AC4
BINIT# BPM2# BPM#1
17 INIT# W5 AB5
INIT# BPM1# BPM#0
AB2 AC6
RSP# BPM0#
8 HDBSY# H5 H3 HREQ#4 HREQ#[0..4] 8
DBSY# REQ4# HREQ#3
8 HDRDY# H2 J3
DRDY# REQ3# HREQ#2
8 HTRDY# J6 J4
TRDY# REQ2# HREQ#1
K5 Every pin put one 220pF cap near it.
REQ1# HREQ#0
C 8 HADS# G1 J1 C
G4 ADS# REQ0#
8 HLOCK#
G2
LOCK#
AD25 Trace Width 15mils, Space 15mils.
8 HBNR# BNR# TESTHI12 R60 4.7K
8 HIT# F3 A6 Keep the voltage dividers within 1.5 inches of the
HIT# TESTHI11
8 HITM# E3 Y3
HITM# TESTHI10 R26 4.7K
8 HBPRI# D2 W4 first GTLREF Pin
E2 BPRI# TESTHI9 U6
8 HDEFER# DEFER# TESTHI8
AB22
ITP_TDI TESTHI7
C1 AA20
ITP_TDO TDI TESTHI6 R59 4.7K
Trace : 10 D5 AC23
ITP_TMS TDO TESTHI5
F7 AC24
mil width ITP_TRST# E6 TMS
TRST#
TESTHI4
TESTHI3
AC20 CPU ITP BLOCK
10mil space ITP_TCK D4 AC21
VTIN2 TCK TESTHI2 R58 4.7K ITP_TMS R28 39
28 VTIN2 B3 AA2 VCCP VCCP
VAGND THERMDA TESTHI1 ITP_TDO R29 75
28 VAGND C4 AD24
THERMTRIP# THERMDC TESTHI0
A2
R63 X_33 AF26 THERMTRIP# AF23 ITP_TCK R31 27
PROCHOT# C3 GND/SKTOCC# BCLK1# CPUCLK-0 7
17 PROCHOT# AF22 CPUCLK0 7
IGNNE# PROCHOT# BCLK0#
17 IGNNE# B2
SMI# IGNNE# RS#2
B5 F4
17 SMI#
17 A20M# A20M# C6
SMI# RS2#
G5 RS#1
RS#[0..2] 8 CPU STRAPPING RESISTORS
CPUSLP# AB26 A20M# RS1# F1 RS#0
17 CPUSLP# SLP# RS0#
A22 V5
ALL COMPONENTS CLOSE TO CPU
RESERVED0 AP1#
A7 AC1
RESERVED1 AP0# PROCHOT# R14 62
B AD2 H6 HBR#0 8 VCCP B
AD3 RESERVED2 BR0# CPU_GD R64 300
RESERVED3 R38 49.9 HBR#0 R48 49.9
AE21 P1
RESERVED4 COMP1 R66 49.9 CPURST# R65 49.9
AF24 L24
AF25
RESERVED5 COMP0 * Short trace THERMTRIP# R50 62
RESERVED6
L25
AD6 DP3# K26 BPM#0 R22 49.9
BSEL0 DP2# BPM#1 R23 49.9 VCCP
AD5 K25
BSEL1 DP1# BPM#4 R25 49.9
J26
CPU_GD DP0# BPM#5 R24 49.9
8 CPU_GD AB23
PWRGOOD
R5 HADSTB#1 8
CPURST# AB25 ADSTB1# L5 ITP_TDI R49 150
8 CPURST# RESET# ADSTB0# HADSTB#0 8 VCCP
W23 HDSTBP#3 8
HD#63 DSTBP3# ITP_TRST# R30 680
8 HD#[0..63] AA24 P23 HDSTBP#2 8
HD#62 AA22 D63# Differential DSTBP2#
J23
D62# DSTBP1# HDSTBP#1 8
HD#61 AA25 F21
D61# Host Data DSTBP0# HDSTBP#0 8
HD#60 Y21 W22 HDSTBN#3 8
CPU_GD C33 X_1000p
HD#59 Y24 D60# Strobes DSTBN3#
R22 CPURST# C34 X_1000p
HD#58 D59# DSTBN2# HDSTBN#2 8 CPUSLP# C3 X_0.022u
Y23 K22 HDSTBN#1 8
HD#57 D58# DSTBN1#
W25 E22 HDSTBN#0 8
HD#56 D57# DSTBN0#
Y26
HD#55 W26 D56# E5
HD#54 D55# LINT1/NMI NMI 17
V24 D1 INTR 17
D54# LINT0/INTR
D53#
D52#
D51#
D50#
D49#
D48#
D47#
D46#
D45#
D44#
D43#
D42#
D41#
D40#
D39#
D38#
D37#
D36#
D35#
D34#
D33#
D32#
D31#
D30#
D29#
D28#
D27#
D26#
D25#
D24#
D23#
D22#
D21#
D20#
D19#
D18#
D17#
D16#
D15#
D14#
D13#
D12#
D11#
D10#
A A
D9#
D8#
D7#
D6#
D5#
D4#
D3#
D2#
D1#
D0#
M26
M24
M23
M21
G26
G23
G22
U21
U23
U24
U26
R24
R25
R21
N25
N26
N23
N22
H25
H24
D26
H22
D25
D23
C26
H21
C24
C23
D22
C21
MICRO-STAR INT'L CO.,LTD.
V22
V25
P24
P21
K23
E25
E24
B25
B24
A25
A23
B22
B21
T23
T22
T25
T26
F26
F24
F23
L22
L21
J24
J21
PGA-S478-F02
Title
HD#53
HD#52
HD#51
HD#50
HD#49
HD#48
HD#47
HD#46
HD#45
HD#44
HD#43
HD#42
HD#41
HD#40
HD#39
HD#38
HD#37
HD#36
HD#35
HD#34
HD#33
HD#32
HD#31
HD#30
HD#29
HD#28
HD#27
HD#26
HD#25
HD#24
HD#23
HD#22
HD#21
HD#20
HD#19
HD#18
HD#17
HD#16
HD#15
HD#14
HD#13
HD#12
HD#11
HD#10
HD#9
HD#8
HD#7
HD#6
HD#5
HD#4
HD#3
HD#2
HD#1
HD#0
mPGA478 CPU-1
Size Document Number Rev
MS-6559 10
Custom
Date: Friday, January 04, 2002 Sheet 3 of 33
8 7 6 5 4 3 2 1
A
B
C
D
AB8
AB6
AB3
AA9
AA7
AA4
AA1
AB24
AB21
AB20
AB18
AB16
AB14
AB12
AB10
AA26
AA23
AA19
AA17
AA15
AA13
AA11