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5 4 3 2 1
DDR2 PWR CHARGER
BOM MARK TPS51116 P35 ISL6251 P31
IV@: INT VGA
EV@: STUFF FOR EXT VGA THERMAL 3/5V SYS PWR
SP@: STUFF FOR UMA or VGA X'TAL PROTECTION P38 ISL6237 P32
14.318MHz
Penryn 479 Thermal Sensor Fan Driver
DISCHARGER CPU CORE PWR
D
CLOCK GENERATOR uFCPGA (G780-1P81U) (G991) P37 OZ8116LN P34
D
P3, P4 P3 P24
ICS:
SELGO: SLG8SP512TTR VGA CORE
+1.05V
P2 OZ8118 P36 UP6111AQDD P33
FSB
667/800 MHz
NVIDIA EXT_LVDS
N10M-GE1 EXT_CRT CRT
PCIE 16X P23
VRAM DDRII SWITCH
DDRII NB 1GB P17-P23 LVDS
P23
SO-DIMM 0 Dual Channel DDR2 CIRCUIT
Cantiga LVDS INT_LVDS
SO-DIMM 1 667/800 MHz
P16 (GM45/ PM45/ GL40) RGB INT_CRT P23
C C
P5, P6, P7, P8, P9, P10, P11
X4 DMI interface
HDD (SATA) *1
P24
Ext USB Port x 2
USB 0,1 P25 SATA0
PCI-Express PCIE-1 Mini Card
Int USB Port x 1 ODD (SATA) SATA1 WLAN
USB 7 P25
P24
SB P25
USB 2.0 ICH9M
Bluetooth USB8
USB5 P25
B
X'TAL PCIE-6 B
32.768KHz X'TAL
CCD Azalia P12,P13,P14,P15
25MHz
USB11 P23
Media Atheros
LPC Cardreader Giga-LAN
(RTS5159)
(AR8131)
USB2 P29 P27
Audio CODEC EC (WPC775LDG)
(CX20561) P26
P30
X'TAL
32.768KHz
Card Reader Transformer P28
Connector
P29
SPI ROM
P30
RJ45
A
Audio Amplifier MIC Jack Int. MIC P28 A
P26 P26
G1453L P26 Touch Pad K/B COON.
P24 P30
Int. Quanta Computer Inc.
Speaker
P26
PROJECT : ZR6E
Size Document Number Rev
1A
Block Diagram
Date: Tuesday, May 19, 2009 Sheet 1 of 39
5 4 3 2 1
5 4 3 2 1
Clock Generator (CLK)
+3V
BKP1608HS181T_6_1.5A
L44
C645 C399 C637 C635
+3V_CLK
C642 C649 C634 2
U13
12 +1V05_CLK
CLK VDD power range 1.05V~3.3V
L26
02
VDD_PCI VDD_I/O +1.05V
9 20 BKP1608HS181T_6_1.5A
.1u/10V_4 .1u/10V_4 .1u/10V_4 10u/6.3V_6 VDD_48 VDD_PLL3_I/O C409 C403 C655 C384 C646 C387 C383
16 VDD_PLL3 VDD_SRC_I/O_1 26
*.1u/10V_4 *.1u/10V_4 .1u/10V_4 39 36
VDD_SRC VDD_SRC_I/O_2 10u/6.3V_6 .1u/10V_4 .1u/10V_4 .1u/10V_4
55 VDD_CPU VDD_SRC_I/O_3 45
D C368 33p/50V_4 61 49 .1u/10V_4 *.1u/10V_4 .1u/10V_4 D
VDD_REF VDD_CPU_I/O
1
CG_XIN 60 37 PM_STPCPU# [14]
Y2 The trace within 500mil XTAL_IN CPU_STOP#
14.318MHz CG_XOUT PCI_STOP# 38 PM_STPPCI# [14] Pin 56 : It acts as a
59 56 CK_PWRGD [14]
XTAL_OUT CKPWRGD/PD# level sensitive strobe
2
C367 33p/50V_4 54 to latch the FS pins
CPU_0 CLK_CPU_BCLK [3]
PCI/48M RS=33 ohm when one loading CPU_0# 53 CLK_CPU_BCLK# [3]
[14] SATACLKREQ# R222 475/F_4 SATACLKREQ#_R 1 51 and other multiplexed
=22 ohm when two loading R496 475/F_4 LAN_CLKREQ#_R 3 PCI_0/CLKREQ_A# CPU_1_MCH CLK_MCH_BCLK [5]
[28] LAN_CLKREQ#
PCLK_DEBUG_R PCI_1/CLKREQ_B# CPU_1_MCH# 50 CLK_MCH_BCLK# [5] inputs.
4 PCI_2 SRC_8/CPU_ITP 47
R237 33_4 PCLK_DEBUG_R PCLK_591_R 5 46
[26] PCLK_DEBUG PCI_3 SRC_8#/CPU_ITP#
R242 33_4 PCLK_591_R PCLK_PCM_R 6
[31] PCLK_591 ^PCI_4/LCDCLK_SEL
R251 33_4 PCLK_ICH_R PCLK_ICH_R 7
[13] PCLK_ICH PCIF_5/ITP_EN
CPU_BSEL0 R254 2.2K_4 48
R258 22_4 NC
[14] CLKUSB_48 R507 22_4 FSA 10
C647 *10p/50V_4 PCLK_DEBUG_R [30] CLK_Card48 CPU_BSEL1 USB_48MHz/FS_A
57 FS_B/TEST_MODE
17 CLK_DREFSSCLK_R
C371 *10p/50V_4 PCLK_591_R CPU_BSEL2 R243 10K_4 LCDCLK/27M CLK_DREFSSCLK#_R
LCDCLK#/27M_SS 18
R504 33_4 FSC 62
[14] 14M_ICH REF/FS_C/TEST_SEL
C641 *10p/50V_4 PCLK_ICH_R C638 *30p/50V_4
C648 *10p/50V_4 FSA CLK_DREFCLK_R 13 21
SRC_0/DOT_96 SRC_2 CLK_PCIE_SATA [12]
CLK_DREFCLK#_R 14 22
SRC_0#/DOT_96# SRC_2# CLK_PCIE_SATA# [12]
24 CLK_PCIE_SRC4
SRC_3/CLKREQ_C# T32
+3V CGCLK_SMB 64 25 CLK_PCIE_SRC4#
C SCL SRC_3#/CLKREQ_D# T33 C
CGDAT_SMB 63 27
SDA SRC_4 CLK_PCIE_LAN [28]
SRC_4# 28 CLK_PCIE_LAN# [28]
SRC_6 41 CLK_PCIE_ICH [13]
SRC_6# 40 CLK_PCIE_ICH# [13]
Q12 R238 R217 44 CLK_PCIE_SRC7
SRC_7/CLKREQ_F# T30
DMN601K-7 8 43 CLK_PCIE_SRC7#
VSS_PCI SRC_7#/CLKREQ_E# T31
2
10K_4 10K_4 11 30
VSS_48 SRC_9 CLK_PCIE_MINI1 [26]
15 VSS_I/O SRC_9# 31 CLK_PCIE_MINI1# [26]
3 1 CGDAT_SMB 19 34
[14,16,26,28] PDAT_SMB VSS_PLL3 SRC_10 CLK_PCIE_3GPLL [6]
23 VSS_SRC_1 SRC_10# 35 CLK_PCIE_3GPLL# [6]
29 33 CLK_MCH_OE#_C R270 475/F_4
VSS_SRC_2 SRC_11/CLKREQ_H# CLK_MCH_OE# [6]
42 32 CLK_PCIE_SRC11# R582 475/F_4 MINI_CLKREQ# [26]
+3V VSS_SRC_3 SRC_11#/CLKREQ_G#
52 VSS_CPU
58 RN37
Q11 VSS_REF CLK_DREFCLK_R IV@0_4P2R
1 2 CLK_DREFCLK [6]
DMN601K-7 CLK_DREFCLK#_R 3 4 CLK_DREFCLK# [6]
2
From GMCH RN38
CLK-GEN_SLG8SP512TTR CLK_DREFSSCLK_R 1 2 IV@0_4P2R
CLK_DREFSSCLK [6]
3 1 CGCLK_SMB CLK_DREFSSCLK#_R 3 4
[14,16,26,28] PCLK_SMB CLK_DREFSSCLK# [6]
RN16
CLK_DREFCLK_R 3 4 EV@0_4P2R
CLK_PCIE_VGA [18]
CLK_DREFCLK#_R 1 2 CLK_PCIE_VGA# [18]
From Deisceret RN17
CLK_DREFSSCLK_R 3 4 EV@33_4P2R 27M_NONSS [20]
B CLK_DREFSSCLK#_R 1 2 B
27M_SS [20]
+3V Strap table
CLKREQ_A# Control SRC_0 & SRC_2
CPU Clock select BSEL Frequency Select Table
R494 10K_4 SATACLKREQ#_R
CLKREQ_B# Control LCDCLK & SRC_4
R495 10K_4 LAN_CLKREQ#_R
FSC FSB FSA Frequency
R501 *10K_4 PCLK_DEBUG_R R502 *10K_4 Reserve overclocking
Pin 10/57/62 : For Pin CPU frequency selection 0 0 0 266Mhz
R511 10K_4 CLK_PCIE_SRC11#
0 0 1 133Mhz R246 EV@10K_4 PCLK_PCM_R R500 IV@10K_4
CPU_BSEL0 R252 *short0402
[3] CPU_BSEL0 MCH_BSEL0 [6]
0 1 1 166Mhz
Pin 6 : For Pin 13/14 and 17/18 selection
0 1 0 200Mhz 0 = LCDCLK & DOT96 for internal graphic controller support
CPU_BSEL1 R244 *short0402 1 = 27M & 27M_SS &SRC_0 for external graphic controller support
[3] CPU_BSEL1 MCH_BSEL1 [6]
1 1 0 400Mhz
PCLK_ICH_R R503 10K_4
A A
1 1 1 Reserved
CPU_BSEL2 R499 *short0402
[3] CPU_BSEL2 MCH_BSEL2 [6]
1 0 1 100Mhz
Pin 7 : For Pin 46/47 selection
1 = CPU_ITP
Quanta Computer Inc.
1 0 0 333Mhz
0 = SRC_8 PROJECT : ZR6E
Size Document Number Rev
1A
CLOCK GENERATOR
Date: Tuesday, May 19, 2009 Sheet 2 of 39
5 4 3 2 1
5 4 3 2 1
[5] H_A#[3..16]
H_A#3 J4
U22A
A[3]# ADS# H1 H_ADS# [5]
03
ADDR GROUP_0
H_A#4 L5 E2 H_D#[0..15] U22B H_D#[32..47]
A[4]# BNR# H_BNR# [5] [5] H_D#[0..15] H_D#[32..47] [5]
H_A#5 L4 G5 H_D#0 E22 Y22 H_D#32
A[5]# BPRI# H_BPRI# [5] D[0]# D[32]#
H_A#6 K5 H_D#1 F24 AB24 H_D#33
H_A#7 A[6]# H_D#2 D[1]# D[33]# H_D#34
M3 H5 H_DEFER# [5] E26 V24
A[7]# DEFER# D[2]# D[34]#
DATA GRP 0
H_A#8 N2 F21 H_D#3 G22 V26 H_D#35
H_DRDY# [5]
DATA GRP 2
H_A#9 A[8]# DRDY# H_D#4 D[3]# D[35]# H_D#36
J1 A[9]# DBSY# E1 H_DBSY# [5] F23 D[4]# D[36]# V23
H_A#10 N3 H_D#5 G25 T22 H_D#37
H_A#11 A[10]# H_D#6 D[5]# D[37]# H_D#38
P5 A[11]# BR0# F1 H_BREQ# [5] E25 D[6]# D[38]# U25
H_A#12 P2 H_D#7 E23 U23 H_D#39
D A[12]# D[7]# D[39]# D
CONTROL
H_A#13 L2 D20 H_IERR# R47 56_4 +1.05V H_D#8 K24 Y25 H_D#40
H_A#14 A[13]# IERR# H_D#9 D[8]# D[40]# H_D#41
P4 A[14]# INIT# B3 H_INIT# [12] G24 D[9]# D[41]# W22
H_A#15 P1 H_D#10 J24 Y23 H_D#42
H_A#16 A[15]# H_D#11 D[10]# D[42]# H_D#43
R1 A[16]# LOCK# H4 H_LOCK# [5] J23 D[11]# D[43]# W24
M1 H_D#12 H22 W25 H_D#44
[5] H_ADSTB#0 ADSTB[0]# D[12]# D[44]#
C1 H_D#13 F26 AA23 H_D#45
[5] H_REQ#[0..4] RESET# H_CPURST# [5] D[13]# D[45]#
H_REQ#0 K3 F3 H_D#14 K22 AA24 H_D#46
REQ[0]# RS[0]# H_RS#0 [5] D[14]# D[46]#
H_REQ#1 H2 F4 H_D#15 H23 AB25 H_D#47
REQ[1]# RS[1]# H_RS#1 [5] D[15]# D[47]#
H_REQ#2 K2 G3 J26 Y26
REQ[2]# RS[2]# H_RS#2 [5] [5] H_DSTBN#0 DSTBN[0]# DSTBN[2]# H_DSTBN#2 [5]
H_REQ#3 J3 G2 H26 AA26
REQ[3]# TRDY# H_TRDY# [5] [5] H_DSTBP#0 DSTBP[0]# DSTBP[2]# H_DSTBP#2 [5]
H_REQ#4 L1 H25 U22
REQ[4]# [5] H_DINV#0 DINV[0]# DINV[2]# H_DINV#2 [5]
[5] H_A#[17..35] G6 H_HIT# [5]
H_A#17 HIT# H_D#[16..31] H_D#[48..63]
Y2 A[17]# HITM# E4 H_HITM# [5] [5] H_D#[16..31] H_D#[48..63] [5]
H_A#18 U5 H_D#16 N22 AE24 H_D#48
H_A#19 A[18]# XDP_BPM#0 H_D#17 D[16]# D[48]# H_D#49
R3 A[19]# BPM[0]# AD4 T1 K25 D[17]# D[49]# AD24
ADDR GROUP_1
H_A#20 W6 AD3 XDP_BPM#1 T4 H_D#18 P26 AA21 H_D#50
H_A#21 A[20]# BPM[1]# XDP_BPM#2 H_D#19 D[18]# D[50]# H_D#51
H_A#22
U4
A[21]# BPM[2]#
AD1
XDP_BPM#3