28_WD60C40A.pdf part of Western Digital 28 WD60C40A 28_WD60C40A.pdf, Western Digital _dataBooks 1992_SystemLogic_Imaging_Storage 28

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WD60C40A

TABLE OF CONTENTS
Section Title Page

1.0 INTRODUCTION 28-1
1.1 Architectural Description 28-1
1.2 Features 28-3
1.2.1 Longitudinal Redundancy Checking 28-3
1.2.2 Through Parity 28-3
1.2.3 Western Digital Bus Mode 28-3

2.0 PIN DESCRIPTION 28-6

3.0 NON-CHANNEL REGISTERS 28-8
3.1 Option Register 28-8
3.1.1 RRC3 thru RRCO Refresh Rate Count Field 28-8
3.1.2 SRAM Static RAM Mode (Bit 4) 28-8
3.1.3 CAW1, CAWO Column Address Width Field (Bits 6,5) 28-9
3.1.4 MPAR Memory Parity Enable (Bit 7) 28-9
3.2 Option Register 2